@c Copyright (C) 1988, 1989, 1992, 1994, 1997, 1998, 1999, 2000, 2001, 2002,
-@c 2003, 2004, 2005, 2006, 2007
+@c 2003, 2004, 2005, 2006, 2007, 2008
@c Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@cindex representation of RTL
@cindex Register Transfer Language (RTL)
-Most of the work of the compiler is done on an intermediate representation
-called register transfer language. In this language, the instructions to be
-output are described, pretty much one by one, in an algebraic form that
-describes what the instruction does.
+The last part of the compiler work is done on a low-level intermediate
+representation called Register Transfer Language. In this language, the
+instructions to be output are described, pretty much one by one, in an
+algebraic form that describes what the instruction does.
RTL is inspired by Lisp lists. It has both an internal form, made up of
structures that point at other structures, and a textual form that is used
perhaps with the help of base registers.
Stored in the @code{unchanging} field and printed as @samp{/u}.
-@findex CONST_OR_PURE_CALL_P
+@findex RTL_CONST_CALL_P
@cindex @code{call_insn} and @samp{/u}
@cindex @code{unchanging}, in @code{call_insn}
-@item CONST_OR_PURE_CALL_P (@var{x})
-In a @code{call_insn}, @code{note}, or an @code{expr_list} for notes,
-indicates that the insn represents a call to a const or pure function.
-Stored in the @code{unchanging} field and printed as @samp{/u}.
+@item RTL_CONST_CALL_P (@var{x})
+In a @code{call_insn} indicates that the insn represents a call to a
+const function. Stored in the @code{unchanging} field and printed as
+@samp{/u}.
+
+@findex RTL_PURE_CALL_P
+@cindex @code{call_insn} and @samp{/i}
+@cindex @code{return_val}, in @code{call_insn}
+@item RTL_PURE_CALL_P (@var{x})
+In a @code{call_insn} indicates that the insn represents a call to a
+pure function. Stored in the @code{return_val} field and printed as
+@samp{/i}.
+
+@findex RTL_CONST_OR_PURE_CALL_P
+@cindex @code{call_insn} and @samp{/u} or @samp{/i}
+@item RTL_CONST_OR_PURE_CALL_P (@var{x})
+In a @code{call_insn}, true if @code{RTL_CONST_CALL_P} or
+@code{RTL_PURE_CALL_P} is true.
+
+@findex RTL_LOOPING_CONST_OR_PURE_CALL_P
+@cindex @code{call_insn} and @samp{/c}
+@cindex @code{call}, in @code{call_insn}
+@item RTL_LOOPING_CONST_OR_PURE_CALL_P (@var{x})
+In a @code{call_insn} indicates that the insn represents a possibly
+infinite looping call to a const or pure function. Stored in the
+@code{call} field and printed as @samp{/c}. Only true if one of
+@code{RTL_CONST_CALL_P} or @code{RTL_PURE_CALL_P} is true.
@findex INSN_ANNULLED_BRANCH_P
@cindex @code{jump_insn} and @samp{/u}
Stored in the @code{jump} field and printed as @samp{/j}.
@findex MEM_SCALAR_P
-@cindex @code{mem} and @samp{/f}
-@cindex @code{frame_related}, in @code{mem}
+@cindex @code{mem} and @samp{/i}
+@cindex @code{return_val}, in @code{mem}
@item MEM_SCALAR_P (@var{x})
In @code{mem} expressions, nonzero for reference to a scalar known not
to be a member of a structure, union, or array. Zero for such
to scalar types. If both this flag and @code{MEM_IN_STRUCT_P} are clear,
then we don't know whether this @code{mem} is in a structure or not.
Both flags should never be simultaneously set.
-Stored in the @code{frame_related} field and printed as @samp{/f}.
+Stored in the @code{return_val} field and printed as @samp{/i}.
@findex MEM_VOLATILE_P
@cindex @code{mem} and @samp{/v}
In @code{mem}, nonzero for memory references that will not trap.
Stored in the @code{call} field and printed as @samp{/c}.
+@findex MEM_POINTER
+@cindex @code{mem} and @samp{/f}
+@cindex @code{frame_related}, in @code{mem}
+@item MEM_POINTER (@var{x})
+Nonzero in a @code{mem} if the memory reference holds a pointer.
+Stored in the @code{frame_related} field and printed as @samp{/f}.
+
@findex REG_FUNCTION_VALUE_P
@cindex @code{reg} and @samp{/i}
-@cindex @code{integrated}, in @code{reg}
+@cindex @code{return_val}, in @code{reg}
@item REG_FUNCTION_VALUE_P (@var{x})
Nonzero in a @code{reg} if it is the place in which this function's
value is going to be returned. (This happens only in a hard
-register.) Stored in the @code{integrated} field and printed as
+register.) Stored in the @code{return_val} field and printed as
@samp{/i}.
@findex REG_POINTER
This flag is required for exception handling support on targets with RTL
prologues.
-@cindex @code{insn} and @samp{/i}
-@cindex @code{call_insn} and @samp{/i}
-@cindex @code{jump_insn} and @samp{/i}
-@cindex @code{barrier} and @samp{/i}
-@cindex @code{code_label} and @samp{/i}
-@cindex @code{insn_list} and @samp{/i}
-@cindex @code{const} and @samp{/i}
-@cindex @code{note} and @samp{/i}
-@cindex @code{integrated}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, @code{code_label}, @code{insn_list}, @code{const}, and @code{note}
-@code{code_label}, @code{insn_list}, @code{const}, or @code{note} if it
-resulted from an in-line function call.
-Stored in the @code{integrated} field and printed as @samp{/i}.
-
@findex MEM_READONLY_P
@cindex @code{mem} and @samp{/u}
@cindex @code{unchanging}, in @code{mem}
@findex SYMBOL_REF_WEAK
@cindex @code{symbol_ref} and @samp{/i}
-@cindex @code{integrated}, in @code{symbol_ref}
+@cindex @code{return_val}, in @code{symbol_ref}
@item SYMBOL_REF_WEAK (@var{x})
In a @code{symbol_ref}, indicates that @var{x} has been declared weak.
-Stored in the @code{integrated} field and printed as @samp{/i}.
+Stored in the @code{return_val} field and printed as @samp{/i}.
@findex SYMBOL_REF_FLAG
@cindex @code{symbol_ref} and @samp{/v}
Most uses of @code{SYMBOL_REF_FLAG} are historic and may be subsumed
by @code{SYMBOL_REF_FLAGS}. Certainly use of @code{SYMBOL_REF_FLAGS}
is mandatory if the target requires more than one bit of storage.
+
+@findex PREFETCH_SCHEDULE_BARRIER_P
+@cindex @code{prefetch} and @samp{/v}
+@cindex @code{volatile}, in @code{prefetch}
+@item PREFETCH_SCHEDULE_BARRIER_P (@var{x})
+In a @code{prefetch}, indicates that the prefetch is a scheduling barrier.
+No other INSNs will be moved over it.
+Stored in the @code{volatil} field and printed as @samp{/v}.
@end table
These are the fields to which the above macros refer:
@item call
In a @code{mem}, 1 means that the memory reference will not trap.
+In a @code{call}, 1 means that this pure or const call may possibly
+infinite loop.
+
In an RTL dump, this flag is represented as @samp{/c}.
@findex frame_related
In @code{reg} expressions, 1 means that the register holds a pointer.
+In @code{mem} expressions, 1 means that the memory reference holds a pointer.
+
In @code{symbol_ref} expressions, 1 means that the reference addresses
this function's string constant pool.
-In @code{mem} expressions, 1 means that the reference is to a scalar.
-
In an RTL dump, this flag is represented as @samp{/f}.
@findex in_struct
In an RTL dump, this flag is represented as @samp{/s}.
-@findex integrated
+@findex return_val
@cindex @samp{/i} in RTL dump
-@item integrated
-In an @code{insn}, @code{insn_list}, or @code{const}, 1 means the RTL was
-produced by procedure integration.
-
+@item return_val
In @code{reg} expressions, 1 means the register contains
the value to be returned by the current function. On
machines that pass parameters in registers, the same register number
may be used for parameters as well, but this flag is not set on such
uses.
+In @code{mem} expressions, 1 means the memory reference is to a scalar
+known not to be a member of a structure, union, or array.
+
In @code{symbol_ref} expressions, 1 means the referenced symbol is weak.
+In @code{call} expressions, 1 means the call is pure.
+
In an RTL dump, this flag is represented as @samp{/i}.
@findex jump
In a @code{symbol_ref} expression, 1 means that this symbol addresses
something in the per-function constant pool.
-In a @code{call_insn}, @code{note}, or an @code{expr_list} of notes,
-1 means that this instruction is a call to a const or pure function.
+In a @code{call_insn} 1 means that this instruction is a call to a const
+function.
In an RTL dump, this flag is represented as @samp{/u}.
In @code{label_ref} and @code{reg_label} expressions, 1 means a reference
to a non-local label.
+In @code{prefetch} expressions, 1 means that the containing insn is a
+scheduling barrier.
+
In an RTL dump, this flag is represented as @samp{/v}.
@end table
@code{constm1_rtx} will point to the same object.
@findex const_double
-@item (const_double:@var{m} @var{addr} @var{i0} @var{i1} @dots{})
+@item (const_double:@var{m} @var{i0} @var{i1} @dots{})
Represents either a floating-point constant of mode @var{m} or an
integer constant too large to fit into @code{HOST_BITS_PER_WIDE_INT}
bits but small enough to fit within twice that number of bits (GCC
does not provide a mechanism to represent even larger constants). In
the latter case, @var{m} will be @code{VOIDmode}.
+@findex CONST_DOUBLE_LOW
+If @var{m} is @code{VOIDmode}, the bits of the value are stored in
+@var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro
+@code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}.
+
+If the constant is floating point (regardless of its precision), then
+the number of integers used to store the value depends on the size of
+@code{REAL_VALUE_TYPE} (@pxref{Floating Point}). The integers
+represent a floating point number, but not precisely in the target
+machine's or host machine's floating point format. To convert them to
+the precise bit pattern used by the target machine, use the macro
+@code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}).
+
@findex const_fixed
-@item (const_fixed:@var{m} @var{addr})
+@item (const_fixed:@var{m} @dots{})
Represents a fixed-point constant of mode @var{m}.
-The data structure, which contains data with the size of two
-@code{HOST_BITS_PER_WIDE_INT} and the associated fixed-point mode,
-is access with the macro @code{CONST_FIXED_VALUE}. The high part of data
-is accessed with @code{CONST_FIXED_VALUE_HIGH}; the low part is accessed
-with @code{CONST_FIXED_VALUE_LOW}.
+The operand is a data structure of type @code{struct fixed_value} and
+is accessed with the macro @code{CONST_FIXED_VALUE}. The high part of
+data is accessed with @code{CONST_FIXED_VALUE_HIGH}; the low part is
+accessed with @code{CONST_FIXED_VALUE_LOW}.
@findex const_vector
@item (const_vector:@var{m} [@var{x0} @var{x1} @dots{}])
Represents a vector constant. The square brackets stand for the vector
containing the constant elements. @var{x0}, @var{x1} and so on are
-the @code{const_int} or @code{const_double} elements.
+the @code{const_int}, @code{const_double} or @code{const_fixed} elements.
The number of units in a @code{const_vector} is obtained with the macro
@code{CONST_VECTOR_NUNITS} as in @code{CONST_VECTOR_NUNITS (@var{v})}.
where @var{v} is the vector constant and @var{n} is the element
desired.
-@findex CONST_DOUBLE_MEM
-@findex CONST_DOUBLE_CHAIN
-@var{addr} is used to contain the @code{mem} expression that corresponds
-to the location in memory that at which the constant can be found. If
-it has not been allocated a memory location, but is on the chain of all
-@code{const_double} expressions in this compilation (maintained using an
-undisplayed field), @var{addr} contains @code{const0_rtx}. If it is not
-on the chain, @var{addr} contains @code{cc0_rtx}. @var{addr} is
-customarily accessed with the macro @code{CONST_DOUBLE_MEM} and the
-chain field via @code{CONST_DOUBLE_CHAIN}.
-
-@findex CONST_DOUBLE_LOW
-If @var{m} is @code{VOIDmode}, the bits of the value are stored in
-@var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro
-@code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}.
-
-If the constant is floating point (regardless of its precision), then
-the number of integers used to store the value depends on the size of
-@code{REAL_VALUE_TYPE} (@pxref{Floating Point}). The integers
-represent a floating point number, but not precisely in the target
-machine's or host machine's floating point format. To convert them to
-the precise bit pattern used by the target machine, use the macro
-@code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}).
-
-@findex CONST0_RTX
-@findex CONST1_RTX
-@findex CONST2_RTX
-The macro @code{CONST0_RTX (@var{mode})} refers to an expression with
-value 0 in mode @var{mode}. If mode @var{mode} is of mode class
-@code{MODE_INT}, it returns @code{const0_rtx}. If mode @var{mode} is of
-mode class @code{MODE_FLOAT}, it returns a @code{CONST_DOUBLE}
-expression in mode @var{mode}. Otherwise, it returns a
-@code{CONST_VECTOR} expression in mode @var{mode}. Similarly, the macro
-@code{CONST1_RTX (@var{mode})} refers to an expression with value 1 in
-mode @var{mode} and similarly for @code{CONST2_RTX}. The
-@code{CONST1_RTX} and @code{CONST2_RTX} macros are undefined
-for vector modes.
-
@findex const_string
@item (const_string @var{str})
Represents a constant string with value @var{str}. Currently this is
The @code{label_ref} contains a mode, which is usually @code{Pmode}.
Usually that is the only mode for which a label is directly valid.
+@findex const
@item (const:@var{m} @var{exp})
Represents a constant that is the result of an assembly-time
arithmetic computation. The operand, @var{exp}, is an expression that
@var{m} should be @code{Pmode}.
@end table
+@findex CONST0_RTX
+@findex CONST1_RTX
+@findex CONST2_RTX
+The macro @code{CONST0_RTX (@var{mode})} refers to an expression with
+value 0 in mode @var{mode}. If mode @var{mode} is of mode class
+@code{MODE_INT}, it returns @code{const0_rtx}. If mode @var{mode} is of
+mode class @code{MODE_FLOAT}, it returns a @code{CONST_DOUBLE}
+expression in mode @var{mode}. Otherwise, it returns a
+@code{CONST_VECTOR} expression in mode @var{mode}. Similarly, the macro
+@code{CONST1_RTX (@var{mode})} refers to an expression with value 1 in
+mode @var{mode} and similarly for @code{CONST2_RTX}. The
+@code{CONST1_RTX} and @code{CONST2_RTX} macros are undefined
+for vector modes.
+
@node Regs and Memory
@section Registers and Memory
@cindex RTL register expressions
@end table
@findex subreg
-@item (subreg:@var{m} @var{reg} @var{bytenum})
+@item (subreg:@var{m1} @var{reg:m2} @var{bytenum})
+
@code{subreg} expressions are used to refer to a register in a machine
mode other than its natural one, or to refer to one register of
a multi-part @code{reg} that actually refers to several registers.
-Each pseudo-register has a natural mode. If it is necessary to
-operate on it in a different mode---for example, to perform a fullword
-move instruction on a pseudo-register that contains a single
-byte---the pseudo-register must be enclosed in a @code{subreg}. In
-such a case, @var{bytenum} is zero.
-
-Usually @var{m} is at least as narrow as the mode of @var{reg}, in which
-case it is restricting consideration to only the bits of @var{reg} that
-are in @var{m}.
-
-Sometimes @var{m} is wider than the mode of @var{reg}. These
-@code{subreg} expressions are often called @dfn{paradoxical}. They are
-used in cases where we want to refer to an object in a wider mode but do
-not care what value the additional bits have. The reload pass ensures
-that paradoxical references are only made to hard registers.
-
-The other use of @code{subreg} is to extract the individual registers of
-a multi-register value. Machine modes such as @code{DImode} and
-@code{TImode} can indicate values longer than a word, values which
-usually require two or more consecutive registers. To access one of the
-registers, use a @code{subreg} with mode @code{SImode} and a
-@var{bytenum} offset that says which register.
-
-Storing in a non-paradoxical @code{subreg} has undefined results for
-bits belonging to the same word as the @code{subreg}. This laxity makes
-it easier to generate efficient code for such instructions. To
-represent an instruction that preserves all the bits outside of those in
-the @code{subreg}, use @code{strict_low_part} around the @code{subreg}.
+Each pseudo register has a natural mode. If it is necessary to
+operate on it in a different mode, the register must be
+enclosed in a @code{subreg}.
+
+There are currently three supported types for the first operand of a
+@code{subreg}:
+@itemize
+@item pseudo registers
+This is the most common case. Most @code{subreg}s have pseudo
+@code{reg}s as their first operand.
+
+@item mem
+@code{subreg}s of @code{mem} were common in earlier versions of GCC and
+are still supported. During the reload pass these are replaced by plain
+@code{mem}s. On machines that do not do instruction scheduling, use of
+@code{subreg}s of @code{mem} are still used, but this is no longer
+recommended. Such @code{subreg}s are considered to be
+@code{register_operand}s rather than @code{memory_operand}s before and
+during reload. Because of this, the scheduling passes cannot properly
+schedule instructions with @code{subreg}s of @code{mem}, so for machines
+that do scheduling, @code{subreg}s of @code{mem} should never be used.
+To support this, the combine and recog passes have explicit code to
+inhibit the creation of @code{subreg}s of @code{mem} when
+@code{INSN_SCHEDULING} is defined.
+
+The use of @code{subreg}s of @code{mem} after the reload pass is an area
+that is not well understood and should be avoided. There is still some
+code in the compiler to support this, but this code has possibly rotted.
+This use of @code{subreg}s is discouraged and will most likely not be
+supported in the future.
+
+@item hard registers
+It is seldom necessary to wrap hard registers in @code{subreg}s; such
+registers would normally reduce to a single @code{reg} rtx. This use of
+@code{subreg}s is discouraged and may not be supported in the future.
+@end itemize
+
+@code{subreg}s of @code{subreg}s are not supported. Using
+@code{simplify_gen_subreg} is the recommended way to avoid this problem.
+
+@code{subreg}s come in two distinct flavors, each having its own
+usage and rules:
+
+@table @asis
+@item Paradoxical subregs
+When @var{m1} is strictly wider than @var{m2}, the @code{subreg}
+expression is called @dfn{paradoxical}. The canonical test for this
+class of @code{subreg} is:
+
+@smallexample
+GET_MODE_SIZE (@var{m1}) > GET_MODE_SIZE (@var{m2})
+@end smallexample
+
+Paradoxical @code{subreg}s can be used as both lvalues and rvalues.
+When used as an lvalue, the low-order bits of the source value
+are stored in @var{reg} and the high-order bits are discarded.
+When used as an rvalue, the low-order bits of the @code{subreg} are
+taken from @var{reg} while the high-order bits may or may not be
+defined.
+
+The high-order bits of rvalues are in the following circumstances:
+
+@itemize
+@item @code{subreg}s of @code{mem}
+When @var{m2} is smaller than a word, the macro @code{LOAD_EXTEND_OP},
+can control how the high-order bits are defined.
+
+@item @code{subreg} of @code{reg}s
+The upper bits are defined when @code{SUBREG_PROMOTED_VAR_P} is true.
+@code{SUBREG_PROMOTED_UNSIGNED_P} describes what the upper bits hold.
+Such subregs usually represent local variables, register variables
+and parameter pseudo variables that have been promoted to a wider mode.
+
+@end itemize
+
+@var{bytenum} is always zero for a paradoxical @code{subreg}, even on
+big-endian targets.
+
+For example, the paradoxical @code{subreg}:
+
+@smallexample
+(set (subreg:SI (reg:HI @var{x}) 0) @var{y})
+@end smallexample
+
+stores the lower 2 bytes of @var{y} in @var{x} and discards the upper
+2 bytes. A subsequent:
+
+@smallexample
+(set @var{z} (subreg:SI (reg:HI @var{x}) 0))
+@end smallexample
+
+would set the lower two bytes of @var{z} to @var{y} and set the upper
+two bytes to an unknown value assuming @code{SUBREG_PROMOTED_VAR_P} is
+false.
+
+@item Normal subregs
+When @var{m1} is at least as narrow as @var{m2} the @code{subreg}
+expression is called @dfn{normal}.
+
+Normal @code{subreg}s restrict consideration to certain bits of
+@var{reg}. There are two cases. If @var{m1} is smaller than a word,
+the @code{subreg} refers to the least-significant part (or
+@dfn{lowpart}) of one word of @var{reg}. If @var{m1} is word-sized or
+greater, the @code{subreg} refers to one or more complete words.
+
+When used as an lvalue, @code{subreg} is a word-based accessor.
+Storing to a @code{subreg} modifies all the words of @var{reg} that
+overlap the @code{subreg}, but it leaves the other words of @var{reg}
+alone.
+
+When storing to a normal @code{subreg} that is smaller than a word,
+the other bits of the referenced word are usually left in an undefined
+state. This laxity makes it easier to generate efficient code for
+such instructions. To represent an instruction that preserves all the
+bits outside of those in the @code{subreg}, use @code{strict_low_part}
+or @code{zero_extract} around the @code{subreg}.
+
+@var{bytenum} must identify the offset of the first byte of the
+@code{subreg} from the start of @var{reg}, assuming that @var{reg} is
+laid out in memory order. The memory order of bytes is defined by
+two target macros, @code{WORDS_BIG_ENDIAN} and @code{BYTES_BIG_ENDIAN}:
+
+@itemize
+@item
@cindex @code{WORDS_BIG_ENDIAN}, effect on @code{subreg}
-The compilation parameter @code{WORDS_BIG_ENDIAN}, if set to 1, says
-that byte number zero is part of the most significant word; otherwise,
-it is part of the least significant word.
+@code{WORDS_BIG_ENDIAN}, if set to 1, says that byte number zero is
+part of the most significant word; otherwise, it is part of the least
+significant word.
+@item
@cindex @code{BYTES_BIG_ENDIAN}, effect on @code{subreg}
-The compilation parameter @code{BYTES_BIG_ENDIAN}, if set to 1, says
-that byte number zero is the most significant byte within a word;
-otherwise, it is the least significant byte within a word.
+@code{BYTES_BIG_ENDIAN}, if set to 1, says that byte number zero is
+the most significant byte within a word; otherwise, it is the least
+significant byte within a word.
+@end itemize
@cindex @code{FLOAT_WORDS_BIG_ENDIAN}, (lack of) effect on @code{subreg}
On a few targets, @code{FLOAT_WORDS_BIG_ENDIAN} disagrees with
-@code{WORDS_BIG_ENDIAN}.
-However, most parts of the compiler treat floating point values as if
-they had the same endianness as integer values. This works because
-they handle them solely as a collection of integer values, with no
-particular numerical value. Only real.c and the runtime libraries
-care about @code{FLOAT_WORDS_BIG_ENDIAN}.
-
-@cindex combiner pass
-@cindex reload pass
-@cindex @code{subreg}, special reload handling
-Between the combiner pass and the reload pass, it is possible to have a
-paradoxical @code{subreg} which contains a @code{mem} instead of a
-@code{reg} as its first operand. After the reload pass, it is also
-possible to have a non-paradoxical @code{subreg} which contains a
-@code{mem}; this usually occurs when the @code{mem} is a stack slot
-which replaced a pseudo register.
-
-Note that it is not valid to access a @code{DFmode} value in @code{SFmode}
-using a @code{subreg}. On some machines the most significant part of a
-@code{DFmode} value does not have the same format as a single-precision
-floating value.
-
-It is also not valid to access a single word of a multi-word value in a
-hard register when less registers can hold the value than would be
-expected from its size. For example, some 32-bit machines have
-floating-point registers that can hold an entire @code{DFmode} value.
-If register 10 were such a register @code{(subreg:SI (reg:DF 10) 4)}
-would be invalid because there is no way to convert that reference to
-a single machine register. The reload pass prevents @code{subreg}
-expressions such as these from being formed.
+@code{WORDS_BIG_ENDIAN}. However, most parts of the compiler treat
+floating point values as if they had the same endianness as integer
+values. This works because they handle them solely as a collection of
+integer values, with no particular numerical value. Only real.c and
+the runtime libraries care about @code{FLOAT_WORDS_BIG_ENDIAN}.
+
+Thus,
+
+@smallexample
+(subreg:HI (reg:SI @var{x}) 2)
+@end smallexample
+
+on a @code{BYTES_BIG_ENDIAN}, @samp{UNITS_PER_WORD == 4} target is the same as
+
+@smallexample
+(subreg:HI (reg:SI @var{x}) 0)
+@end smallexample
+
+on a little-endian, @samp{UNITS_PER_WORD == 4} target. Both
+@code{subreg}s access the lower two bytes of register @var{x}.
+
+@end table
+
+A @code{MODE_PARTIAL_INT} mode behaves as if it were as wide as the
+corresponding @code{MODE_INT} mode, except that it has an unknown
+number of undefined bits. For example:
+
+@smallexample
+(subreg:PSI (reg:SI 0) 0)
+@end smallexample
+
+accesses the whole of @samp{(reg:SI 0)}, but the exact relationship
+between the @code{PSImode} value and the @code{SImode} value is not
+defined. If we assume @samp{UNITS_PER_WORD <= 4}, then the following
+two @code{subreg}s:
+
+@smallexample
+(subreg:PSI (reg:DI 0) 0)
+(subreg:PSI (reg:DI 0) 4)
+@end smallexample
+
+represent independent 4-byte accesses to the two halves of
+@samp{(reg:DI 0)}. Both @code{subreg}s have an unknown number
+of undefined bits.
+
+If @samp{UNITS_PER_WORD <= 2} then these two @code{subreg}s:
+
+@smallexample
+(subreg:HI (reg:PSI 0) 0)
+(subreg:HI (reg:PSI 0) 2)
+@end smallexample
+
+represent independent 2-byte accesses that together span the whole
+of @samp{(reg:PSI 0)}. Storing to the first @code{subreg} does not
+affect the value of the second, and vice versa. @samp{(reg:PSI 0)}
+has an unknown number of undefined bits, so the assignment:
+
+@smallexample
+(set (subreg:HI (reg:PSI 0) 0) (reg:HI 4))
+@end smallexample
+
+does not guarantee that @samp{(subreg:HI (reg:PSI 0) 0)} has the
+value @samp{(reg:HI 4)}.
+
+@cindex @code{CANNOT_CHANGE_MODE_CLASS} and subreg semantics
+The rules above apply to both pseudo @var{reg}s and hard @var{reg}s.
+If the semantics are not correct for particular combinations of
+@var{m1}, @var{m2} and hard @var{reg}, the target-specific code
+must ensure that those combinations are never used. For example:
+
+@smallexample
+CANNOT_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class})
+@end smallexample
+
+must be true for every class @var{class} that includes @var{reg}.
@findex SUBREG_REG
@findex SUBREG_BYTE
with the @code{SUBREG_REG} macro and the second operand is customarily
accessed with the @code{SUBREG_BYTE} macro.
+It has been several years since a platform in which
+@code{BYTES_BIG_ENDIAN} not equal to @code{WORDS_BIG_ENDIAN} has
+been tested. Anyone wishing to support such a platform in the future
+may be confronted with code rot.
+
@findex scratch
@cindex scratch operands
@item (scratch:@var{m})
other memories. Thus it may be used as a memory barrier in epilogue
stack deallocation patterns.
-@findex addressof
-@item (addressof:@var{m} @var{reg})
-This RTX represents a request for the address of register @var{reg}. Its mode
-is always @code{Pmode}. If there are any @code{addressof}
-expressions left in the function after CSE, @var{reg} is forced into the
-stack and the @code{addressof} expression is replaced with a @code{plus}
-expression for the address of its stack slot.
-
@findex concat
@item (concat@var{m} @var{rtx} @var{rtx})
This RTX represents the concatenation of two other RTXs. This is used
ordinary insn chain.
@findex concatn
-@item (concatn@var{m} [@var{rtx} ...])
+@item (concatn@var{m} [@var{rtx} @dots{}])
This RTX represents the concatenation of all the @var{rtx} to make a
single value. Like @code{concat}, this should only appear in
declarations, and not in the insn chain.
Represents the number of leading 0-bits in @var{x}, represented as an
integer of mode @var{m}, starting at the most significant bit position.
If @var{x} is zero, the value is determined by
-@code{CLZ_DEFINED_VALUE_AT_ZERO}. Note that this is one of
+@code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Note that this is one of
the few expressions that is not invariant under widening. The mode of
@var{x} will usually be an integer mode.
Represents the number of trailing 0-bits in @var{x}, represented as an
integer of mode @var{m}, starting at the least significant bit position.
If @var{x} is zero, the value is determined by
-@code{CTZ_DEFINED_VALUE_AT_ZERO}. Except for this case,
+@code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Except for this case,
@code{ctz(x)} is equivalent to @code{ffs(@var{x}) - 1}. The mode of
@var{x} will usually be an integer mode.
@findex fix
@item (fix:@var{m} @var{x})
-When @var{m} is a fixed point mode, represents the result of
+When @var{m} is a floating-point mode, represents the result of
+converting floating point value @var{x} (valid for mode @var{m}) to an
+integer, still represented in floating point mode @var{m}, by rounding
+towards zero.
+
+When @var{m} is a fixed-point mode, represents the result of
converting floating point value @var{x} to mode @var{m}, regarded as
signed. How rounding is done is not specified, so this operation may
be used validly in compiling C code only for integer-valued operands.
fixed point mode @var{m}, regarded as unsigned. How rounding is done
is not specified.
-@findex fix
-@item (fix:@var{m} @var{x})
-When @var{m} is a floating point mode, represents the result of
-converting floating point value @var{x} (valid for mode @var{m}) to an
-integer, still represented in floating point mode @var{m}, by rounding
-towards zero.
-
@findex fract_convert
@item (fract_convert:@var{m} @var{x})
Represents the result of converting fixed-point value @var{x} to
When a @code{clobber} expression for a register appears inside a
@code{parallel} with other side effects, the register allocator
guarantees that the register is unoccupied both before and after that
-insn. However, the reload phase may allocate a register used for one of
-the inputs unless the @samp{&} constraint is specified for the selected
-alternative (@pxref{Modifiers}). You can clobber either a specific hard
+insn if it is a hard register clobber. For pseudo-register clobber,
+the register allocator and the reload pass do not assign the same hard
+register to the clobber and the input operands if there is an insn
+alternative containing the @samp{&} constraint (@pxref{Modifiers}) for
+the clobber and the hard register is in register classes of the
+clobber in the alternative. You can clobber either a specific hard
register, a pseudo register, or a @code{scratch} expression; in the
latter two cases, GCC will allocate a hard register that is available
there for use as a temporary.
In some situations, it may be tempting to add a @code{use} of a
register in a @code{parallel} to describe a situation where the value
of a special register will modify the behavior of the instruction.
-An hypothetical example might be a pattern for an addition that can
+A hypothetical example might be a pattern for an addition that can
either wrap around or use saturating addition depending on the value
of a special control register:
@var{m} must be the machine mode for pointers on the machine in use.
The expression @var{y} must be one of three forms:
-@table @code
@code{(plus:@var{m} @var{x} @var{z})},
@code{(minus:@var{m} @var{x} @var{z})}, or
@code{(plus:@var{m} @var{x} @var{i})},
-@end table
where @var{z} is an index register and @var{i} is a constant.
Here is an example of its use:
When an @code{asm} statement has multiple output values, its insn has
several such @code{set} RTX's inside of a @code{parallel}. Each @code{set}
-contains a @code{asm_operands}; all of these share the same assembler
+contains an @code{asm_operands}; all of these share the same assembler
template and vectors, but each contains the constraint for the respective
output operand. They are also distinguished by the output-operand index
number, which is 0, 1, @dots{} for successive output operands.
@findex jump_insn
@item jump_insn
The expression code @code{jump_insn} is used for instructions that may
-jump (or, more generally, may contain @code{label_ref} expressions). If
-there is an instruction to return from the current function, it is
-recorded as a @code{jump_insn}.
+jump (or, more generally, may contain @code{label_ref} expressions to
+which @code{pc} can be set in that instruction). If there is an
+instruction to return from the current function, it is recorded as a
+@code{jump_insn}.
@findex JUMP_LABEL
@code{jump_insn} insns have the same extra fields as @code{insn} insns,
For simple conditional and unconditional jumps, this field contains
the @code{code_label} to which this insn will (possibly conditionally)
branch. In a more complex jump, @code{JUMP_LABEL} records one of the
-labels that the insn refers to; the only way to find the others is to
-scan the entire body of the insn. In an @code{addr_vec},
-@code{JUMP_LABEL} is @code{NULL_RTX}.
+labels that the insn refers to; other jump target labels are recorded
+as @code{REG_LABEL_TARGET} notes. The exception is @code{addr_vec}
+and @code{addr_diff_vec}, where @code{JUMP_LABEL} is @code{NULL_RTX}
+and the only way to find the labels is to scan the entire body of the
+insn.
Return insns count as jumps, but since they do not refer to any
labels, their @code{JUMP_LABEL} is @code{NULL_RTX}.
The @code{REG_NONNEG} note is added to insns only if the machine
description has a @samp{decrement_and_branch_until_zero} pattern.
-@findex REG_NO_CONFLICT
-@item REG_NO_CONFLICT
-This insn does not cause a conflict between @var{op} and the item
-being set by this insn even though it might appear that it does.
-In other words, if the destination register and @var{op} could
-otherwise be assigned the same register, this insn does not
-prevent that assignment.
-
-Insns with this note are usually part of a block that begins with a
-@code{clobber} insn specifying a multi-word pseudo register (which will
-be the output of the block), a group of insns that each set one word of
-the value and have the @code{REG_NO_CONFLICT} note attached, and a final
-insn that copies the output to itself with an attached @code{REG_EQUAL}
-note giving the expression being computed. This block is encapsulated
-with @code{REG_LIBCALL} and @code{REG_RETVAL} notes on the first and
-last insns, respectively.
-
-@findex REG_LABEL
-@item REG_LABEL
+@findex REG_LABEL_OPERAND
+@item REG_LABEL_OPERAND
This insn uses @var{op}, a @code{code_label} or a @code{note} of type
-@code{NOTE_INSN_DELETED_LABEL}, but is not a
-@code{jump_insn}, or it is a @code{jump_insn} that required the label to
-be held in a register. The presence of this note allows jump
-optimization to be aware that @var{op} is, in fact, being used, and flow
-optimization to build an accurate flow graph.
+@code{NOTE_INSN_DELETED_LABEL}, but is not a @code{jump_insn}, or it
+is a @code{jump_insn} that refers to the operand as an ordinary
+operand. The label may still eventually be a jump target, but if so
+in an indirect jump in a subsequent insn. The presence of this note
+allows jump optimization to be aware that @var{op} is, in fact, being
+used, and flow optimization to build an accurate flow graph.
+
+@findex REG_LABEL_TARGET
+@item REG_LABEL_TARGET
+This insn is a @code{jump_insn} but not an @code{addr_vec} or
+@code{addr_diff_vec}. It uses @var{op}, a @code{code_label} as a
+direct or indirect jump target. Its purpose is similar to that of
+@code{REG_LABEL_OPERAND}. This note is only present if the insn has
+multiple targets; the last label in the insn (in the highest numbered
+insn-field) goes into the @code{JUMP_LABEL} field and does not have a
+@code{REG_LABEL_TARGET} note. @xref{Insns, JUMP_LABEL}.
@findex REG_CROSSING_JUMP
@item REG_CROSSING_JUMP
-This insn is an branching instruction (either an unconditional jump or
+This insn is a branching instruction (either an unconditional jump or
an indirect jump) which crosses between hot and cold sections, which
could potentially be very far apart in the executable. The presence
-of this note indicates to other optimizations that this this branching
+of this note indicates to other optimizations that this branching
instruction should not be ``collapsed'' into a simpler branching
construct. It is used when the optimization to partition basic blocks
into hot and cold sections is turned on.
the inverse note pointing back to the first insn.
@table @code
-@findex REG_RETVAL
-@item REG_RETVAL
-This insn copies the value of a multi-insn sequence (for example, a
-library call), and @var{op} is the first insn of the sequence (for a
-library call, the first insn that was generated to set up the arguments
-for the library call).
-
-Loop optimization uses this note to treat such a sequence as a single
-operation for code motion purposes and flow analysis uses this note to
-delete such sequences whose results are dead.
-
-A @code{REG_EQUAL} note will also usually be attached to this insn to
-provide the expression being computed by the sequence.
-
-These notes will be deleted after reload, since they are no longer
-accurate or useful.
-
-@findex REG_LIBCALL
-@item REG_LIBCALL
-This is the inverse of @code{REG_RETVAL}: it is placed on the first
-insn of a multi-insn sequence, and it points to the last one.
-
-These notes are deleted after reload, since they are no longer useful or
-accurate.
-
@findex REG_CC_SETTER
@findex REG_CC_USER
@item REG_CC_SETTER
This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression
is used in place of the actual insn pattern. This is done in cases where
the pattern is either complex or misleading.
-
-@findex REG_LIBCALL_ID
-@item REG_LIBCALL_ID
-This is used to specify that an insn is part of a libcall. Each libcall
-in a function has a unique id, and all the insns that are part of that
-libcall will have a REG_LIBCALL_ID note attached with the same ID.
@end table
For convenience, the machine mode in an @code{insn_list} or
OSDN Git Service
