-mcaller-super-interworking -mcallee-super-interworking @gol
-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
-mword-relocations @gol
--mfix-cortex-m3-ldrd}
+-mfix-cortex-m3-ldrd @gol
+-munaligned-access}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
-mincoming-stack-boundary=@var{num} @gol
-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
-mrecip -mrecip=@var{opt} @gol
--mvzeroupper @gol
+-mvzeroupper -mprefer-avx128 @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-mavx2 -maes -mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
-msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
-m5-compact -m5-compact-nofpu @gol
-mb -ml -mdalign -mrelax @gol
-mbigtable -mfmovd -mhitachi -mrenesas -mno-renesas -mnomacsave @gol
--mieee -mbitops -misize -minline-ic_invalidate -mpadstruct -mspace @gol
--mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
+-mieee -mno-ieee -mbitops -misize -minline-ic_invalidate -mpadstruct @gol
+-mspace -mprefergot -musermode -multcost=@var{number} -mdiv=@var{strategy} @gol
-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
-madjust-unroll -mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic @gol
-mfaster-structs -mno-faster-structs -mflat -mno-flat @gol
-mfpu -mno-fpu -mhard-float -msoft-float @gol
-mhard-quad-float -msoft-quad-float @gol
--mlittle-endian @gol
-mstack-bias -mno-stack-bias @gol
-munaligned-doubles -mno-unaligned-doubles @gol
-mv8plus -mno-v8plus -mvis -mno-vis @gol
@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
@emph{TILE-Gx Options}
-@gccoptlist{-mcpu=CPU -m32 -m64}
+@gccoptlist{-mcpu=@var{cpu} -m32 -m64}
@emph{TILEPro Options}
-@gccoptlist{-mcpu=CPU -m32}
+@gccoptlist{-mcpu=@var{cpu} -m32}
@emph{V850 Options}
@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol
e.g. With -fdbg-cnt=dce:10,tail_call:0
dbg_cnt(dce) will return true only for first 10 invocations
-@itemx -fenable-@var{kind}-@var{pass}
+@item -fenable-@var{kind}-@var{pass}
@itemx -fdisable-@var{kind}-@var{pass}=@var{range-list}
@opindex fdisable-
@opindex fenable-
@option{-fdump-rtl-ce3} enable dumping after the three
if conversion passes.
-@itemx -fdump-rtl-cprop_hardreg
+@item -fdump-rtl-cprop_hardreg
@opindex fdump-rtl-cprop_hardreg
Dump after hard register copy propagation.
-@itemx -fdump-rtl-csa
+@item -fdump-rtl-csa
@opindex fdump-rtl-csa
Dump after combining stack adjustments.
@option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after
the two common sub-expression elimination passes.
-@itemx -fdump-rtl-dce
+@item -fdump-rtl-dce
@opindex fdump-rtl-dce
Dump after the standalone dead code elimination passes.
-@itemx -fdump-rtl-dbr
+@item -fdump-rtl-dbr
@opindex fdump-rtl-dbr
Dump after delayed branch scheduling.
@opindex fdump-rtl-initvals
Dump after the computation of the initial value sets.
-@itemx -fdump-rtl-into_cfglayout
+@item -fdump-rtl-into_cfglayout
@opindex fdump-rtl-into_cfglayout
Dump after converting to cfglayout mode.
@opindex fdump-rtl-rnreg
Dump after register renumbering.
-@itemx -fdump-rtl-outof_cfglayout
+@item -fdump-rtl-outof_cfglayout
@opindex fdump-rtl-outof_cfglayout
Dump after converting from cfglayout mode.
@opindex fdump-rtl-postreload
Dump after post-reload optimizations.
-@itemx -fdump-rtl-pro_and_epilogue
+@item -fdump-rtl-pro_and_epilogue
@opindex fdump-rtl-pro_and_epilogue
Dump after generating the function prologues and epilogues.
@opindex fdump-rtl-dfinish
These dumps are defined but always produce empty files.
-@item -fdump-rtl-all
+@item -da
+@itemx -fdump-rtl-all
+@opindex da
@opindex fdump-rtl-all
Produce all the dumps listed above.
@opindex dH
Produce a core dump whenever an error occurs.
-@item -dm
-@opindex dm
-Print statistics on memory usage, at the end of the run, to
-standard error.
-
@item -dp
@opindex dp
Annotate the assembler output with a comment indicating which
@file{../lib32}, or if OS libraries are present in @file{lib/@var{subdir}}
subdirectories it prints e.g.@: @file{amd64}, @file{sparcv9} or @file{ev6}.
+@item -print-multiarch
+@opindex print-multiarch
+Print the path to OS libraries for the selected multiarch,
+relative to some @file{lib} subdirectory.
+
@item -print-prog-name=@var{program}
@opindex print-prog-name
Like @option{-print-file-name}, but searches for a program such as @samp{cpp}.
generating these instructions. This option is enabled by default when
@option{-mcpu=cortex-m3} is specified.
+@item -munaligned-access
+@itemx -mno-unaligned-access
+@opindex munaligned-access
+@opindex mno-unaligned-access
+Enables (or disables) reading and writing of 16- and 32- bit values
+from addresses that are not 16- or 32- bit aligned. By default
+unaligned access is disabled for all pre-ARMv6 and all ARMv6-M
+architectures, and enabled for all other architectures. If unaligned
+access is not enabled then words in packed data structures will be
+accessed a byte at a time.
+
+The ARM attribute @code{Tag_CPU_unaligned_access} will be set in the
+generated object file to either true or false, depending upon the
+setting of this option. If unaligned access is enabled then the
+preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be
+defined.
+
@end table
@node AVR Options
@opindex mmcu
Specify Atmel AVR instruction set architectures (ISA) or MCU type.
-For a complete list of @var{mcu} values that are supported by @command{avr-gcc},
-see the compiler output when called with the @option{--help=target}
-command line option.
The default for this option is@tie{}@code{avr2}.
GCC supports the following AVR devices and ISAs:
@item avr2
``Classic'' devices with up to 8@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90c8534}, @code{at90s2313},
-@code{at90s2323}, @code{at90s2333}, @code{at90s2343},
-@code{at90s4414}, @code{at90s4433}, @code{at90s4434},
-@code{at90s8515}, @code{at90s8535}, @code{attiny22}, @code{attiny26}.
+@*@var{mcu}@tie{}= @code{attiny22}, @code{attiny26}, @code{at90c8534},
+@code{at90s2313}, @code{at90s2323}, @code{at90s2333},
+@code{at90s2343}, @code{at90s4414}, @code{at90s4433},
+@code{at90s4434}, @code{at90s8515}, @code{at90s8535}.
@item avr25
``Classic'' devices with up to 8@tie{}KiB of program memory and with
the @code{MOVW} instruction.
-@*@var{mcu}@tie{}= @code{at86rf401}, @code{ata6289}, @code{attiny13},
-@code{attiny13a}, @code{attiny2313}, @code{attiny2313a},
-@code{attiny24}, @code{attiny24a}, @code{attiny25}, @code{attiny261},
-@code{attiny261a}, @code{attiny4313}, @code{attiny43u},
+@*@var{mcu}@tie{}= @code{ata6289}, @code{attiny13}, @code{attiny13a},
+@code{attiny2313}, @code{attiny2313a}, @code{attiny24},
+@code{attiny24a}, @code{attiny25}, @code{attiny261},
+@code{attiny261a}, @code{attiny43u}, @code{attiny4313},
@code{attiny44}, @code{attiny44a}, @code{attiny45}, @code{attiny461},
@code{attiny461a}, @code{attiny48}, @code{attiny84}, @code{attiny84a},
@code{attiny85}, @code{attiny861}, @code{attiny861a}, @code{attiny87},
-@code{attiny88}.
+@code{attiny88}, @code{at86rf401}.
@item avr3
``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
@item avr31
``Classic'' devices with 128@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at43usb320}, @code{atmega103}.
+@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}.
@item avr35
``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program
memory and with the @code{MOVW} instruction.
-@*@var{mcu}@tie{}= @code{at90usb162}, @code{at90usb82},
-@code{atmega16u2}, @code{atmega32u2}, @code{atmega8u2},
-@code{attiny167}.
+@*@var{mcu}@tie{}= @code{atmega16u2}, @code{atmega32u2},
+@code{atmega8u2}, @code{attiny167}, @code{at90usb162},
+@code{at90usb82}.
@item avr4
``Enhanced'' devices with up to 8@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b},
-@code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}, @code{atmega48},
-@code{atmega48a}, @code{atmega48p}, @code{atmega8}, @code{atmega8515},
-@code{atmega8535}, @code{atmega88}, @code{atmega88a},
-@code{atmega88p}, @code{atmega88pa}, @code{atmega8hva}.
+@*@var{mcu}@tie{}= @code{atmega48}, @code{atmega48a},
+@code{atmega48p}, @code{atmega8}, @code{atmega8hva},
+@code{atmega8515}, @code{atmega8535}, @code{atmega88},
+@code{atmega88a}, @code{atmega88p}, @code{atmega88pa},
+@code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3},
+@code{at90pwm3b}, @code{at90pwm81}.
@item avr5
``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90can32}, @code{at90can64},
-@code{at90pwm216}, @code{at90pwm316}, @code{at90scr100},
-@code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{atmega16},
-@code{atmega161}, @code{atmega162}, @code{atmega163},
-@code{atmega164a}, @code{atmega164p}, @code{atmega165},
-@code{atmega165a}, @code{atmega165p}, @code{atmega168},
-@code{atmega168a}, @code{atmega168p}, @code{atmega169},
-@code{atmega169a}, @code{atmega169p}, @code{atmega169pa},
-@code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2},
-@code{atmega16hvb}, @code{atmega16m1}, @code{atmega16u4},
-@code{atmega32}, @code{atmega323}, @code{atmega324a},
-@code{atmega324p}, @code{atmega324pa}, @code{atmega325},
+@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega16a},
+@code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb},
+@code{atmega16m1}, @code{atmega16u4}, @code{atmega161},
+@code{atmega162}, @code{atmega163}, @code{atmega164a},
+@code{atmega164p}, @code{atmega165}, @code{atmega165a},
+@code{atmega165p}, @code{atmega168}, @code{atmega168a},
+@code{atmega168p}, @code{atmega169}, @code{atmega169a},
+@code{atmega169p}, @code{atmega169pa}, @code{atmega32},
+@code{atmega32c1}, @code{atmega32hvb}, @code{atmega32m1},
+@code{atmega32u4}, @code{atmega32u6}, @code{atmega323},
+@code{atmega324a}, @code{atmega324p}, @code{atmega324pa},
+@code{atmega325}, @code{atmega325a}, @code{atmega325p},
@code{atmega3250}, @code{atmega3250a}, @code{atmega3250p},
-@code{atmega325a}, @code{atmega325p}, @code{atmega328},
-@code{atmega328p}, @code{atmega329}, @code{atmega3290},
-@code{atmega3290a}, @code{atmega3290p}, @code{atmega329a},
-@code{atmega329p}, @code{atmega329pa}, @code{atmega32c1},
-@code{atmega32hvb}, @code{atmega32m1}, @code{atmega32u4},
-@code{atmega32u6}, @code{atmega406}, @code{atmega64},
-@code{atmega640}, @code{atmega644}, @code{atmega644a},
-@code{atmega644p}, @code{atmega644pa}, @code{atmega645},
-@code{atmega6450}, @code{atmega6450a}, @code{atmega6450p},
-@code{atmega645a}, @code{atmega645p}, @code{atmega649},
-@code{atmega6490}, @code{atmega649a}, @code{atmega649p},
-@code{atmega64c1}, @code{atmega64hve}, @code{atmega64m1},
+@code{atmega328}, @code{atmega328p}, @code{atmega329},
+@code{atmega329a}, @code{atmega329p}, @code{atmega329pa},
+@code{atmega3290}, @code{atmega3290a}, @code{atmega3290p},
+@code{atmega406}, @code{atmega64}, @code{atmega64c1},
+@code{atmega64hve}, @code{atmega64m1}, @code{atmega640},
+@code{atmega644}, @code{atmega644a}, @code{atmega644p},
+@code{atmega644pa}, @code{atmega645}, @code{atmega645a},
+@code{atmega645p}, @code{atmega6450}, @code{atmega6450a},
+@code{atmega6450p}, @code{atmega649}, @code{atmega649a},
+@code{atmega649p}, @code{atmega6490}, @code{at90can32},
+@code{at90can64}, @code{at90pwm216}, @code{at90pwm316},
+@code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k},
@code{m3000}.
@item avr51
``Enhanced'' devices with 128@tie{}KiB of program memory.
-@*@var{mcu}@tie{}= @code{at90can128}, @code{at90usb1286},
-@code{at90usb1287}, @code{atmega128}, @code{atmega1280},
-@code{atmega1281}, @code{atmega1284p}, @code{atmega128rfa1}.
+@*@var{mcu}@tie{}= @code{atmega128}, @code{atmega128rfa1},
+@code{atmega1280}, @code{atmega1281}, @code{atmega1284p},
+@code{at90can128}, @code{at90usb1286}, @code{at90usb1287}.
@item avr6
``Enhanced'' devices with 3-byte PC, i.e.@: with more than
@item avr1
This ISA is implemented by the minimal AVR core and supported for
assembler only.
-@*@var{mcu}@tie{}= @code{at90s1200}, @code{attiny11}, @code{attiny12},
-@code{attiny15}, @code{attiny28}.
+@*@var{mcu}@tie{}= @code{attiny11}, @code{attiny12}, @code{attiny15},
+@code{attiny28}, @code{at90s1200}.
@end table
@item -mshort-calls
@opindex mshort-calls
+This option has been deprecated and will be removed in GCC 4.8.
+See @code{-mrelax} for a replacement.
+
Use @code{RCALL}/@code{RJMP} instructions even on devices with
16@tie{}KiB or more of program memory, i.e.@: on devices that
have the @code{CALL} and @code{JMP} instructions.
-See also the @code{-mrelax} command line option.
@item -msp8
@opindex msp8
The startup code from libgcc never sets @code{EIND}.
Notice that startup code is a blend of code from libgcc and AVR-LibC.
For the impact of AVR-LibC on @code{EIND}, see the
-@w{@uref{http://nongnu.org/avr-libc/user-manual,AVR-LibC user manual}}.
+@w{@uref{http://nongnu.org/avr-libc/user-manual/,AVR-LibC user manual}}.
@item
It is legitimate for user-specific startup code to set up @code{EIND}
@table @code
+@item __AVR_ARCH__
+Build-in macro that resolves to a decimal number that identifies the
+architecture and depends on the @code{-mmcu=@var{mcu}} option.
+Possible values are:
+
+@code{2}, @code{25}, @code{3}, @code{31}, @code{35},
+@code{4}, @code{5}, @code{51}, @code{6}, @code{102}, @code{104},
+@code{105}, @code{106}, @code{107}
+
+for @var{mcu}=@code{avr2}, @code{avr25}, @code{avr3},
+@code{avr31}, @code{avr35}, @code{avr4}, @code{avr5}, @code{avr51},
+@code{avr6}, @code{avrxmega2}, @code{avrxmega4}, @code{avrxmega5},
+@code{avrxmega6}, @code{avrxmega7}, respectively.
+If @var{mcu} specifies a device, this built-in macro is set
+accordingly. For example, with @code{-mmcu=atmega8} the macro will be
+defined to @code{4}.
+
@item __AVR_@var{Device}__
Setting @code{-mmcu=@var{device}} defines this built-in macro which reflects
the device's name. For example, @code{-mmcu=atmega8} defines the
@var{Device} in the built-in macro and @var{device} in
@code{-mmcu=@var{device}} is that the latter is always lowercase.
+If @var{device} is not a device but only a core architecture like
+@code{avr51}, this macro will not be defined.
+
+@item __AVR_XMEGA__
+The device/architecture belongs to the XMEGA family of devices.
+
@item __AVR_HAVE_ELPM__
The device has the the @code{ELPM} instruction.
to be subtracted from the RAM address in order to get the
respective I/O@tie{}address.
+@item __WITH_AVRLIBC__
+The compiler is configured to be used together with AVR-Libc.
+See the @code{--with-avrlibc} configure option.
+
@end table
@node Blackfin Options
AVX to SSE transition penalty as well as remove unnecessary zeroupper
intrinsics.
+@item -mprefer-avx128
+@opindex mprefer-avx128
+This option instructs GCC to use 128-bit AVX instructions instead of
+256-bit AVX instructions in the auto-vectorizer.
+
@item -mcx16
@opindex mcx16
This option will enable GCC to use CMPXCHG16B instruction in generated code.
@option{-mhitachi} is given.
@item -mieee
+@item -mno-ieee
@opindex mieee
-Increase IEEE compliance of floating-point code.
-At the moment, this is equivalent to @option{-fno-finite-math-only}.
-When generating 16-bit SH opcodes, getting IEEE-conforming results for
-comparisons of NANs / infinities incurs extra overhead in every
-floating-point comparison, therefore the default is set to
-@option{-ffinite-math-only}.
+@opindex mnoieee
+Control the IEEE compliance of floating-point comparisons, which affects the
+handling of cases where the result of a comparison is unordered. By default
+@option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is
+enabled @option{-mno-ieee} is implicitly set, which results in faster
+floating-point greater-equal and less-equal comparisons. The implcit settings
+can be overridden by specifying either @option{-mieee} or @option{-mno-ieee}.
@item -minline-ic_invalidate
@opindex minline-ic_invalidate
@item -mdiv=@var{strategy}
@opindex mdiv=@var{strategy}
-Set the division strategy to use for SHmedia code. @var{strategy} must be
-one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call,
-inv:call2, inv:fp .
-"fp" performs the operation in floating point. This has a very high latency,
+Set the division strategy to be used for integer division operations.
+For SHmedia @var{strategy} can be one of:
+
+@table @samp
+
+@item fp
+Performs the operation in floating point. This has a very high latency,
but needs only a few instructions, so it might be a good choice if
your code has enough easily-exploitable ILP to allow the compiler to
schedule the floating-point instructions together with other instructions.
Division by zero causes a floating-point exception.
-"inv" uses integer operations to calculate the inverse of the divisor,
+
+@item inv
+Uses integer operations to calculate the inverse of the divisor,
and then multiplies the dividend with the inverse. This strategy allows
-cse and hoisting of the inverse calculation. Division by zero calculates
+CSE and hoisting of the inverse calculation. Division by zero calculates
an unspecified result, but does not trap.
-"inv:minlat" is a variant of "inv" where if no cse / hoisting opportunities
+
+@item inv:minlat
+A variant of @samp{inv} where, if no CSE or hoisting opportunities
have been found, or if the entire operation has been hoisted to the same
place, the last stages of the inverse calculation are intertwined with the
final multiply to reduce the overall latency, at the expense of using a few
more instructions, and thus offering fewer scheduling opportunities with
other code.
-"call" calls a library function that usually implements the inv:minlat
+
+@item call
+Calls a library function that usually implements the @samp{inv:minlat}
strategy.
-This gives high code density for m5-*media-nofpu compilations.
-"call2" uses a different entry point of the same library function, where it
+This gives high code density for @code{m5-*media-nofpu} compilations.
+
+@item call2
+Uses a different entry point of the same library function, where it
assumes that a pointer to a lookup table has already been set up, which
-exposes the pointer load to cse / code hoisting optimizations.
-"inv:call", "inv:call2" and "inv:fp" all use the "inv" algorithm for initial
-code generation, but if the code stays unoptimized, revert to the "call",
-"call2", or "fp" strategies, respectively. Note that the
+exposes the pointer load to CSE and code hoisting optimizations.
+
+@item inv:call
+@itemx inv:call2
+@itemx inv:fp
+Use the @samp{inv} algorithm for initial
+code generation, but if the code stays unoptimized, revert to the @samp{call},
+@samp{call2}, or @samp{fp} strategies, respectively. Note that the
potentially-trapping side effect of division by zero is carried by a
separate instruction, so it is possible that all the integer instructions
are hoisted out, but the marker for the side effect stays where it is.
-A recombination to fp operations or a call is not possible in that case.
-"inv20u" and "inv20l" are variants of the "inv:minlat" strategy. In the case
-that the inverse calculation was nor separated from the multiply, they speed
-up division where the dividend fits into 20 bits (plus sign where applicable),
+A recombination to floating-point operations or a call is not possible
+in that case.
+
+@item inv20u
+@itemx inv20l
+Variants of the @samp{inv:minlat} strategy. In the case
+that the inverse calculation is not separated from the multiply, they speed
+up division where the dividend fits into 20 bits (plus sign where applicable)
by inserting a test to skip a number of operations in this case; this test
-slows down the case of larger dividends. inv20u assumes the case of a such
-a small dividend to be unlikely, and inv20l assumes it to be likely.
+slows down the case of larger dividends. @samp{inv20u} assumes the case of a such
+a small dividend to be unlikely, and @samp{inv20l} assumes it to be likely.
+
+@end table
+
+For targets other than SHmedia @var{strategy} can be one of:
+
+@table @samp
+
+@item call-div1
+Calls a library function that uses the single-step division instruction
+@code{div1} to perform the operation. Division by zero calculates an
+unspecified result and does not trap. This is the default except for SH4,
+SH2A and SHcompact.
+
+@item call-fp
+Calls a library function that performs the operation in double precision
+floating point. Division by zero causes a floating-point exception. This is
+the default for SHcompact with FPU. Specifying this for targets that do not
+have a double precision FPU will default to @code{call-div1}.
+
+@item call-table
+Calls a library function that uses a lookup table for small divisors and
+the @code{div1} instruction with case distinction for larger divisors. Division
+by zero calculates an unspecified result and does not trap. This is the default
+for SH4. Specifying this for targets that do not have dynamic shift
+instructions will default to @code{call-div1}.
+
+@end table
+
+When a division strategy has not been specified the default strategy will be
+selected based on the current target. For SH2A the default strategy is to
+use the @code{divs} and @code{divu} instructions instead of library function
+calls.
@item -maccumulate-outgoing-args
@opindex maccumulate-outgoing-args
on SPARC-V9 processors in 64-bit environments:
@table @gcctabopt
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a processor running in little-endian mode. It is only
-available for a few configurations and most notably not on Solaris and Linux.
-
@item -m32
@itemx -m64
@opindex m32
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