-trigraphs -no-integrated-cpp -traditional -traditional-cpp @gol
-fallow-single-precision -fcond-mismatch @gol
-fsigned-bitfields -fsigned-char @gol
--funsigned-bitfields -funsigned-char @gol
--fwritable-strings}
+-funsigned-bitfields -funsigned-char}
@item C++ Language Options
@xref{C++ Dialect Options,,Options Controlling C++ Dialect}.
-Wsystem-headers -Wtrigraphs -Wundef -Wuninitialized @gol
-Wunknown-pragmas -Wunreachable-code @gol
-Wunused -Wunused-function -Wunused-label -Wunused-parameter @gol
--Wunused-value -Wunused-variable -Wwrite-strings}
+-Wunused-value -Wunused-variable -Wwrite-strings @gol
+-Wvariadic-macros}
@item C-only Warning Options
@gccoptlist{-Wbad-function-cast -Wmissing-declarations @gol
-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol
-feliminate-unused-debug-symbols -fmem-report -fprofile-arcs @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
--ftest-coverage -ftime-report @gol
+-ftest-coverage -ftime-report -fvar-tracking @gol
-g -g@var{level} -gcoff -gdwarf-2 @gol
-ggdb -gstabs -gstabs+ -gvms -gxcoff -gxcoff+ @gol
-p -pg -print-file-name=@var{library} -print-libgcc-file-name @gol
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
--mmmx -msse -msse2 -mpni -m3dnow @gol
+-mmmx -msse -msse2 -msse3 -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
-mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol
-nolibdld -static -threads}
-@emph{Intel 960 Options}
-@gccoptlist{-m@var{cpu-type} -masm-compat -mclean-linkage @gol
--mcode-align -mcomplex-addr -mleaf-procedures @gol
--mic-compat -mic2.0-compat -mic3.0-compat @gol
--mintel-asm -mno-clean-linkage -mno-code-align @gol
--mno-complex-addr -mno-leaf-procedures @gol
--mno-old-align -mno-strict-align -mno-tail-call @gol
--mnumerics -mold-align -msoft-float -mstrict-align @gol
--mtail-call}
-
@emph{DEC Alpha Options}
@gccoptlist{-mno-fp-regs -msoft-float -malpha-as -mgas @gol
-mieee -mieee-with-inexact -mieee-conformant @gol
-minline-int-divide-max-throughput -mno-dwarf2-asm @gol
-mfixed-range=@var{register-range}}
-@emph{D30V Options}
-@gccoptlist{-mextmem -mextmemory -monchip -mno-asm-optimize @gol
--masm-optimize -mbranch-cost=@var{n} -mcond-exec=@var{n}}
-
@emph{S/390 and zSeries Options}
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
-mhard-float -msoft-float -mbackchain -mno-backchain @gol
-malloc-cc -mfixed-cc -mdword -mno-dword @gol
-mdouble -mno-double @gol
-mmedia -mno-media -mmuladd -mno-muladd @gol
+-mfdpic -minline-plt -mgprel-ro -multilib-library-pic -mlinked-fp @gol
-mlibrary-pic -macc-4 -macc-8 @gol
-mpack -mno-pack -mno-eflags -mcond-move -mno-cond-move @gol
-mscc -mno-scc -mcond-exec -mno-cond-exec @gol
declaration does not use either @code{signed} or @code{unsigned}. By
default, such a bit-field is signed, because this is consistent: the
basic integer types such as @code{int} are signed types.
-
-@item -fwritable-strings
-@opindex fwritable-strings
-Store string constants in the writable data segment and don't uniquize
-them. This is for compatibility with old programs which assume they can
-write into string constants.
-
-Writing into string constants is a very bad idea; ``constants'' should
-be constant.
-
-This option is deprecated.
@end table
@node C++ Dialect Options
Therefore, the ABI obtained using version 0 will change as ABI bugs
are fixed.
-The default is version 1.
+The default is version 2.
@item -fno-access-control
@opindex fno-access-control
Give string constants type @code{char *} instead of type @code{const
char *}. By default, G++ uses type @code{const char *} as required by
the standard. Even if you use @option{-fno-const-strings}, you cannot
-actually modify the value of a string constant, unless you also use
-@option{-fwritable-strings}.
+actually modify the value of a string constant.
This option might be removed in a future release of G++. For maximum
portability, you should structure your code so that it works with
@option{-Wlong-long} and @option{-Wno-long-long} are taken into account
only when @option{-pedantic} flag is used.
+@item -Wvariadic-macros
+@opindex Wvariadic-macros
+@opindex Wno-variadic-macros
+Warn if variadic macros are used in pedantic ISO C90 mode, or the GNU
+alternate syntax when in pedantic ISO C99 mode. This is default.
+To inhibit the warning messages, use @option{-Wno-variadic-macros}.
+
@item -Wdisabled-optimization
@opindex Wdisabled-optimization
Warn if a requested optimization pass is disabled. This warning does
@item V
@opindex dV
Dump after the value profile transformations, to @file{@var{file}.13.vpt}.
+Also dump after variable tracking, to @file{@var{file}.35.vartrack}.
@item w
@opindex dw
Dump after the second flow pass, to @file{@var{file}.27.flow2}.
time spent executing operating system routines on behalf of the program.
Both numbers are in seconds.
+@item -fvar-tracking
+@opindex fvar-tracking
+Run variable tracking pass. It computes where variables are stored at each
+position in code. Better debugging information is then generated
+(if the debugging information format supports this information).
+
+It is enabled by default when compiling with optimization (@option{-Os},
+@option{-O}, @option{-O2}, ...), debugging information (@option{-g}) and
+the debug info format supports it.
+
@item -print-file-name=@var{library}
@opindex print-file-name
Print the full absolute name of the library file @var{library} that
* MIPS Options::
* i386 and x86-64 Options::
* HPPA Options::
-* Intel 960 Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
* H8/300 Options::
* AVR Options::
* MCore Options::
* IA-64 Options::
-* D30V Options::
* S/390 and zSeries Options::
* CRIS Options::
* MMIX Options::
Intel PentiumPro CPU.
@item pentium2
Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
-@item pentium3
+@item pentium3, pentium3m
Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set
support.
-@item pentium4
+@item pentium-m
+Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
+support. Used by Centrino notebooks.
+@item pentium4, pentium4m
Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
+@item prescott
+Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
+set support.
+@item nocona
+Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
+SSE2 and SSE3 instruction set support.
@item k6
AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3
@item -mfpmath=@var{unit}
@opindex march
-generate floating point arithmetics for selected unit @var{unit}. the choices
+Generate floating point arithmetics for selected unit @var{unit}. The choices
for @var{unit} are:
@table @samp
@option{-msse2} switches to enable SSE extensions and make this option
effective. For x86-64 compiler, these extensions are enabled by default.
-The resulting code should be considerably faster in majority of cases and avoid
+The resulting code should be considerably faster in the majority of cases and avoid
the numerical instability problems of 387 code, but may break some existing
code that expects temporaries to be 80bit.
-This is the default choice for x86-64 compiler.
-
-@item pni
-Use all SSE extensions enabled by @option{-msse2} as well as the new
-SSE extensions in Prescott New Instructions. @option{-mpni} also
-enables 2 builtin functions, @code{__builtin_ia32_monitor} and
-@code{__builtin_ia32_mwait}, for new instructions @code{monitor} and
-@code{mwait}.
+This is the default choice for the x86-64 compiler.
@item sse,387
Attempt to utilize both instruction sets at once. This effectively double the
amount of available registers and on chips with separate execution units for
387 and SSE the execution resources too. Use this option with care, as it is
-still experimental, because gcc register allocator does not model separate
+still experimental, because the gcc register allocator does not model separate
functional units well resulting in instable performance.
@end table
standard of 80 bits for a @code{long double}.
@strong{Warning:} if you override the default value for your target ABI, the
-structures and arrays containing @code{long double} will change their size as
-well as function calling convention for function taking @code{long double}
-will be modified. Hence they will not be binary compatible with arrays or
-structures in code compiled without that switch.
+structures and arrays containing @code{long double} variables will change
+their size as well as function calling convention for function taking
+@code{long double} will be modified. Hence they will not be binary
+compatible with arrays or structures in code compiled without that switch.
@item -msvr3-shlib
@itemx -mno-sse
@item -msse2
@itemx -mno-sse2
-@item -mpni
-@itemx -mno-pni
+@item -msse3
+@itemx -mno-sse3
@item -m3dnow
@itemx -mno-3dnow
@opindex mmmx
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of built-in functions that allow
-direct access to the MMX, SSE and 3Dnow extensions of the instruction set.
+direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
+instruction set.
@xref{X86 Built-in Functions}, for details of the functions enabled
and disabled by these switches.
@env{PATH}. The linker used by GCC can be printed using @samp{which
`gcc -print-prog-name=ld`}.
+@item -mfdpic
+@opindex mfdpic
+
+Select the FDPIC ABI, that uses function descriptors to represent
+pointers to functions. Without any PIC/PIE-related options, it
+implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
+assumes GOT entries and small data are within a 12-bit range from the
+GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
+are computed with 32 bits.
+
+@item -minline-plt
+@opindex minline-plt
+
+Enable inlining of PLT entries in function calls to functions that are
+not known to bind locally. It has no effect without @option{-mfdpic}.
+It's enabled by default if optimizing for speed and compiling for
+shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
+optimization option such as @option{-O3} or above is present in the
+command line.
+
+@item -mgprel-ro
+@opindex mgprel-ro
+
+Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
+that is known to be in read-only sections. It's enabled by default,
+except for @option{-fpic} or @option{-fpie}: even though it may help
+make the global offset table smaller, it trades 1 instruction for 4.
+With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
+one of which may be shared by multiple symbols, and it avoids the need
+for a GOT entry for the referenced symbol, so it's more likely to be a
+win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
+
+@item -multilib-library-pic
+@opindex multilib-library-pic
+
+Link with the (library, not FD) pic libraries. It's implied by
+@option{-mlibrary-pic}, as well as by @option{-fPIC} and
+@option{-fpic} without @option{-mfdpic}. You should never have to use
+it explicitly.
+
+@item -mlinked-fp
+@opindex mlinked-fp
+
+Follow the EABI requirement of always creating a frame pointer whenever
+a stack frame is allocated. This option is enabled by default and can
+be disabled with @option{-mno-linked-fp}.
+
@item -mlong-calls
@opindex mno-long-calls
Generate code that uses long call sequences. This ensures that a call
linker.
@end table
-@node Intel 960 Options
-@subsection Intel 960 Options
-
-These @samp{-m} options are defined for the Intel 960 implementations:
-
-@table @gcctabopt
-@item -m@var{cpu-type}
-@opindex mka
-@opindex mkb
-@opindex mmc
-@opindex mca
-@opindex mcf
-@opindex msa
-@opindex msb
-Assume the defaults for the machine type @var{cpu-type} for some of
-the other options, including instruction scheduling, floating point
-support, and addressing modes. The choices for @var{cpu-type} are
-@samp{ka}, @samp{kb}, @samp{mc}, @samp{ca}, @samp{cf},
-@samp{sa}, and @samp{sb}.
-The default is
-@samp{kb}.
-
-@item -mnumerics
-@itemx -msoft-float
-@opindex mnumerics
-@opindex msoft-float
-The @option{-mnumerics} option indicates that the processor does support
-floating-point instructions. The @option{-msoft-float} option indicates
-that floating-point support should not be assumed.
-
-@item -mleaf-procedures
-@itemx -mno-leaf-procedures
-@opindex mleaf-procedures
-@opindex mno-leaf-procedures
-Do (or do not) attempt to alter leaf procedures to be callable with the
-@code{bal} instruction as well as @code{call}. This will result in more
-efficient code for explicit calls when the @code{bal} instruction can be
-substituted by the assembler or linker, but less efficient code in other
-cases, such as calls via function pointers, or using a linker that doesn't
-support this optimization.
-
-@item -mtail-call
-@itemx -mno-tail-call
-@opindex mtail-call
-@opindex mno-tail-call
-Do (or do not) make additional attempts (beyond those of the
-machine-independent portions of the compiler) to optimize tail-recursive
-calls into branches. You may not want to do this because the detection of
-cases where this is not valid is not totally complete. The default is
-@option{-mno-tail-call}.
-
-@item -mcomplex-addr
-@itemx -mno-complex-addr
-@opindex mcomplex-addr
-@opindex mno-complex-addr
-Assume (or do not assume) that the use of a complex addressing mode is a
-win on this implementation of the i960. Complex addressing modes may not
-be worthwhile on the K-series, but they definitely are on the C-series.
-The default is currently @option{-mcomplex-addr} for all processors except
-the CB and CC@.
-
-@item -mcode-align
-@itemx -mno-code-align
-@opindex mcode-align
-@opindex mno-code-align
-Align code to 8-byte boundaries for faster fetching (or don't bother).
-Currently turned on by default for C-series implementations only.
-
-@ignore
-@item -mclean-linkage
-@itemx -mno-clean-linkage
-@opindex mclean-linkage
-@opindex mno-clean-linkage
-These options are not fully implemented.
-@end ignore
-
-@item -mic-compat
-@itemx -mic2.0-compat
-@itemx -mic3.0-compat
-@opindex mic-compat
-@opindex mic2.0-compat
-@opindex mic3.0-compat
-Enable compatibility with iC960 v2.0 or v3.0.
-
-@item -masm-compat
-@itemx -mintel-asm
-@opindex masm-compat
-@opindex mintel-asm
-Enable compatibility with the iC960 assembler.
-
-@item -mstrict-align
-@itemx -mno-strict-align
-@opindex mstrict-align
-@opindex mno-strict-align
-Do not permit (do permit) unaligned accesses.
-
-@item -mold-align
-@opindex mold-align
-Enable structure-alignment compatibility with Intel's gcc release version
-1.3 (based on gcc 1.37). This option implies @option{-mstrict-align}.
-
-@item -mlong-double-64
-@opindex mlong-double-64
-Implement type @samp{long double} as 64-bit floating point numbers.
-Without the option @samp{long double} is implemented by 80-bit
-floating point numbers. The only reason we have it because there is
-no 128-bit @samp{long double} support in @samp{fp-bit.c} yet. So it
-is only useful for people using soft-float targets. Otherwise, we
-should recommend against use of it.
-
-@end table
-
@node DEC Alpha Options
@subsection DEC Alpha Options
scheduling, but does not always do so.
@end table
-@node D30V Options
-@subsection D30V Options
-@cindex D30V Options
-
-These @samp{-m} options are defined for D30V implementations:
-
-@table @gcctabopt
-@item -mextmem
-@opindex mextmem
-Link the @samp{.text}, @samp{.data}, @samp{.bss}, @samp{.strings},
-@samp{.rodata}, @samp{.rodata1}, @samp{.data1} sections into external
-memory, which starts at location @code{0x80000000}.
-
-@item -mextmemory
-@opindex mextmemory
-Same as the @option{-mextmem} switch.
-
-@item -monchip
-@opindex monchip
-Link the @samp{.text} section into onchip text memory, which starts at
-location @code{0x0}. Also link @samp{.data}, @samp{.bss},
-@samp{.strings}, @samp{.rodata}, @samp{.rodata1}, @samp{.data1} sections
-into onchip data memory, which starts at location @code{0x20000000}.
-
-@item -mno-asm-optimize
-@itemx -masm-optimize
-@opindex mno-asm-optimize
-@opindex masm-optimize
-Disable (enable) passing @option{-O} to the assembler when optimizing.
-The assembler uses the @option{-O} option to automatically parallelize
-adjacent short instructions where possible.
-
-@item -mbranch-cost=@var{n}
-@opindex mbranch-cost
-Increase the internal costs of branches to @var{n}. Higher costs means
-that the compiler will issue more instructions to avoid doing a branch.
-The default is 2.
-
-@item -mcond-exec=@var{n}
-@opindex mcond-exec
-Specify the maximum number of conditionally executed instructions that
-replace a branch. The default is 4.
-@end table
-
@node S/390 and zSeries Options
@subsection S/390 and zSeries Options
@cindex S/390 and zSeries Options
@item -mlibrary-pic
@opindex mlibrary-pic
-Enable PIC support for building libraries
+Generate position-independent EABI code.
@item -macc-4
@opindex macc-4
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