-mpoke-function-name @gol
-mthumb -marm @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
--mcaller-super-interworking -mcallee-super-interworking}
+-mcaller-super-interworking -mcallee-super-interworking @gol
+-mtp=@var{name}}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
assembler assembler-with-cpp
ada
f77 f77-cpp-input ratfor
-f95
+f95 f95-cpp-input
java
treelang
@end smallexample
value is ignored in the case where all instructions in the block being
crossjumped from are matched. The default value is 5.
+@item max-grow-copy-bb-insns
+The maximum code size expansion factor when copying basic blocks
+instead of jumping. The expansion is relative to a jump instruction.
+The default value is 8.
+
@item max-goto-duplication-insns
The maximum number of instructions to duplicate to a block that jumps
to a computed goto. To avoid @math{O(N^2)} behavior in a number of
Select fraction of the maximal frequency of executions of basic block in
function given basic block needs to have to be considered hot
+@item max-predicted-iterations
+The maximum number of loop iterations we predict statically. This is useful
+in cases where function contain single loop with known bound and other loop
+with unknown. We predict the known number of iterations correctly, while
+the unknown nummber of iterations average to roughly 10. This means that the
+loop without bounds would appear artifically cold relative to the other one.
+
@item tracer-dynamic-coverage
@itemx tracer-dynamic-coverage-feedback
Maximum number of basic blocks on path that cse considers. The default is 10.
+@item max-cse-insns
+The maximum instructions CSE process before flushing. The default is 1000.
+
@item global-var-threshold
Counts the number of function calls (@var{n}) and the number of
Increasing values mean more aggressive optimization, making the compile time
increase with probably slightly better performance. The default value is 500.
+@item max-flow-memory-location
+Similar as @option{max-cselib-memory-location} but for dataflow liveness.
+The default value is 100.
+
@item reorder-blocks-duplicate
@itemx reorder-blocks-duplicate-feedback
The minimum size of buffers (i.e. arrays) that will receive stack smashing
protection when @option{-fstack-protection} is used.
+@item max-jump-thread-duplication-stmts
+Maximum number of statements allowed in a block that needs to be
+duplicated when threading jumps.
@end table
@end table
@item -mabi=@var{name}
@opindex mabi
Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu},
-@samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
+@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}.
@item -mapcs-frame
@opindex mapcs-frame
compiled for interworking or not. There is a small overhead in the cost
of executing a function pointer if this option is enabled.
+@item -mtp=@var{name}
+@opindex mtp
+Specify the access model for the thread local storage pointer. The valid
+models are @option{soft}, which generates calls to @code{__aeabi_read_tp},
+@option{cp15}, which fetches the thread pointer from @code{cp15} directly
+(supported in the arm6k architecture), and @option{auto}, which uses the
+best available method for the selected processor. The default setting is
+@option{auto}.
+
@end table
@node AVR Options
@opindex mno-sse
@opindex m3dnow
@opindex mno-3dnow
-These switches enable or disable the use of built-in functions that allow
-direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
-instruction set.
-
-@xref{X86 Built-in Functions}, for details of the functions enabled
-and disabled by these switches.
+These switches enable or disable the use of instructions in the MMX,
+SSE, SSE2 or 3DNow! extended instruction sets. These extensions are
+also available as built-in functions: see @ref{X86 Built-in Functions},
+for details of the functions enabled and disabled by these switches.
To have SSE/SSE2 instructions generated automatically from floating-point
-code, see @option{-mfpmath=sse}.
+code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
+
+These options will enable GCC to use these extended instructions in
+generated code, even without @option{-mfpmath=sse}. Applications which
+perform runtime CPU detection must compile separate files for each
+supported architecture, using the appropriate flags. In particular,
+the file containing the CPU detection code should be compiled without
+these options.
@item -mpush-args
@itemx -mno-push-args
Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
64.
-@item -mtune-arch=@var{cpu-type}
-@opindex mtune-arch
+@item -mtune=@var{cpu-type}
+@opindex mtune
Tune the instruction scheduling for a particular CPU, Valid values are
itanium, itanium1, merced, itanium2, and mckinley.
if the stack size is @var{stack-guard} bytes above the @var{stack-size}
(remember that the stack on s390 grows downward). These options are intended to
be used to help debugging stack overflow problems. The additionally emitted code
-cause only little overhead and hence can also be used in production like systems
+causes only little overhead and hence can also be used in production like systems
without greater performance degradation. The given values have to be exact
-powers of 2 and @var{stack-size} has to be greater than @var{stack-guard}.
+powers of 2 and @var{stack-size} has to be greater than @var{stack-guard} without
+exceeding 64k.
In order to be efficient the extra code makes the assumption that the stack starts
at an address aligned to the value given by @var{stack-size}.
@end table
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