./:

[pf3gnuchains/gcc-fork.git] / gcc / cse.c

diff --git a/gcc/cse.c b/gcc/cse.c
index 9dc27c3..54edf7e 100644 (file)
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -761,8 +761,8 @@ notreg_cost (rtx x, enum rtx_code outer)
           && (GET_MODE_SIZE (GET_MODE (x))
               < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
           && subreg_lowpart_p (x)
-          && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (x)),
-                                    GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))))
+          && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
+                                            GET_MODE (SUBREG_REG (x))))
          ? 0
          : rtx_cost (x, outer, optimize_this_for_speed_p) * 2);
 }
@@ -1637,8 +1637,10 @@ insert_with_costs (rtx x, struct table_elt *classp, unsigned int hash,
          /* Put it after the last element cheaper than X.  */
          struct table_elt *p, *next;
 
-         for (p = classp; (next = p->next_same_value) && CHEAPER (next, elt);
-              p = next);
+         for (p = classp;
+              (next = p->next_same_value) && CHEAPER (next, elt);
+              p = next)
+           ;
 
          /* Put it after P and before NEXT.  */
          elt->next_same_value = next;
@@ -3650,7 +3652,7 @@ fold_rtx (rtx x, rtx insn)
              enum rtx_code associate_code;
 
              if (is_shift
-                 && (INTVAL (const_arg1) >= GET_MODE_BITSIZE (mode)
+                 && (INTVAL (const_arg1) >= GET_MODE_PRECISION (mode)
                      || INTVAL (const_arg1) < 0))
                {
                  if (SHIFT_COUNT_TRUNCATED)
@@ -3699,7 +3701,7 @@ fold_rtx (rtx x, rtx insn)
                 break;
 
              if (is_shift
-                 && (INTVAL (inner_const) >= GET_MODE_BITSIZE (mode)
+                 && (INTVAL (inner_const) >= GET_MODE_PRECISION (mode)
                      || INTVAL (inner_const) < 0))
                {
                  if (SHIFT_COUNT_TRUNCATED)
@@ -3729,7 +3731,7 @@ fold_rtx (rtx x, rtx insn)
 
              if (is_shift
                  && CONST_INT_P (new_const)
-                 && INTVAL (new_const) >= GET_MODE_BITSIZE (mode))
+                 && INTVAL (new_const) >= GET_MODE_PRECISION (mode))
                {
                  /* As an exception, we can turn an ASHIFTRT of this
                     form into a shift of the number of bits - 1.  */
@@ -3959,9 +3961,7 @@ record_jump_cond (enum rtx_code code, enum machine_mode mode, rtx op0,
      is not worth testing for with no SUBREG).  */
 
   /* Note that GET_MODE (op0) may not equal MODE.  */
-  if (code == EQ && GET_CODE (op0) == SUBREG
-      && (GET_MODE_SIZE (GET_MODE (op0))
-         > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0)))))
+  if (code == EQ && paradoxical_subreg_p (op0))
     {
       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
       rtx tem = record_jump_cond_subreg (inner_mode, op1);
@@ -3970,9 +3970,7 @@ record_jump_cond (enum rtx_code code, enum machine_mode mode, rtx op0,
                          reversed_nonequality);
     }
 
-  if (code == EQ && GET_CODE (op1) == SUBREG
-      && (GET_MODE_SIZE (GET_MODE (op1))
-         > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1)))))
+  if (code == EQ && paradoxical_subreg_p (op1))
     {
       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op1));
       rtx tem = record_jump_cond_subreg (inner_mode, op0);
@@ -4556,9 +4554,7 @@ cse_insn (rtx insn)
         treat it as volatile.  It may do the work of an SI in one context
         where the extra bits are not being used, but cannot replace an SI
         in general.  */
-      if (GET_CODE (src) == SUBREG
-         && (GET_MODE_SIZE (GET_MODE (src))
-             > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
+      if (paradoxical_subreg_p (src))
        sets[i].src_volatile = 1;
 #endif
 
@@ -4678,13 +4674,13 @@ cse_insn (rtx insn)
 
       if (src_const && src_related == 0 && CONST_INT_P (src_const)
          && GET_MODE_CLASS (mode) == MODE_INT
-         && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
+         && GET_MODE_PRECISION (mode) < BITS_PER_WORD)
        {
          enum machine_mode wider_mode;
 
          for (wider_mode = GET_MODE_WIDER_MODE (mode);
               wider_mode != VOIDmode
-              && GET_MODE_BITSIZE (wider_mode) <= BITS_PER_WORD
+              && GET_MODE_PRECISION (wider_mode) <= BITS_PER_WORD
               && src_related == 0;
               wider_mode = GET_MODE_WIDER_MODE (wider_mode))
            {
@@ -4836,9 +4832,7 @@ cse_insn (rtx insn)
 
          /* Also skip paradoxical subregs, unless that's what we're
             looking for.  */
-         if (code == SUBREG
-             && (GET_MODE_SIZE (GET_MODE (p->exp))
-                 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (p->exp))))
+         if (paradoxical_subreg_p (p->exp)
              && ! (src != 0
                    && GET_CODE (src) == SUBREG
                    && GET_MODE (src) == GET_MODE (p->exp)
@@ -4947,9 +4941,7 @@ cse_insn (rtx insn)
             size, but later may be adjusted so that the upper bits aren't
             what we want.  So reject it.  */
          if (elt != 0
-             && GET_CODE (elt->exp) == SUBREG
-             && (GET_MODE_SIZE (GET_MODE (elt->exp))
-                 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (elt->exp))))
+             && paradoxical_subreg_p (elt->exp)
              /* It is okay, though, if the rtx we're trying to match
                 will ignore any of the bits we can't predict.  */
              && ! (src != 0
@@ -5041,7 +5033,7 @@ cse_insn (rtx insn)
              && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 1))
              && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 2))
              && REG_P (XEXP (SET_DEST (sets[i].rtl), 0))
-             && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (sets[i].rtl)))
+             && (GET_MODE_PRECISION (GET_MODE (SET_DEST (sets[i].rtl)))
                  >= INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)))
              && ((unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 1))
                  + (unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 2))
@@ -5068,7 +5060,7 @@ cse_insn (rtx insn)
                  HOST_WIDE_INT mask;
                  unsigned int shift;
                  if (BITS_BIG_ENDIAN)
-                   shift = GET_MODE_BITSIZE (GET_MODE (dest_reg))
+                   shift = GET_MODE_PRECISION (GET_MODE (dest_reg))
                            - INTVAL (pos) - INTVAL (width);
                  else
                    shift = INTVAL (pos);
@@ -5710,9 +5702,7 @@ cse_insn (rtx insn)
               some tracking to be wrong.
 
               ??? Think about this more later.  */
-           || (GET_CODE (dest) == SUBREG
-               && (GET_MODE_SIZE (GET_MODE (dest))
-                   > GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))))
+           || (paradoxical_subreg_p (dest)
                && (GET_CODE (sets[i].src) == SIGN_EXTEND
                    || GET_CODE (sets[i].src) == ZERO_EXTEND)))
          continue;