Support scheduling for ColdFire V1 and V3 microarchitecture.

[pf3gnuchains/gcc-fork.git] / gcc / config / spu / predicates.md

diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 8b31e65..7e5c6a9 100644 (file)
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -1,9 +1,9 @@
 ;; Predicate definitions for CELL SPU
-;; Copyright (C) 2006 Free Software Foundation, Inc.
+;; Copyright (C) 2006, 2007 Free Software Foundation, Inc.
 ;;
 ;; This file is free software; you can redistribute it and/or modify it under
 ;; the terms of the GNU General Public License as published by the Free
-;; Software Foundation; either version 2 of the License, or (at your option) 
+;; Software Foundation; either version 3 of the License, or (at your option) 
 ;; any later version.
 
 ;; This file is distributed in the hope that it will be useful, but WITHOUT
@@ -12,9 +12,17 @@
 ;; for more details.
 
 ;; You should have received a copy of the GNU General Public License
-;; along with this file; see the file COPYING.  If not, write to the Free
-;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
-;; 02110-1301, USA.
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; Return 1 if operand is constant zero of its mode
+(define_predicate "const_zero_operand"
+  (and (match_code "const_int,const,const_double,const_vector")
+       (match_test "op == CONST0_RTX (mode)")))
+
+(define_predicate "const_one_operand"
+  (and (match_code "const_int,const,const_double,const_vector")
+       (match_test "op == CONST1_RTX (mode)")))
 
 (define_predicate "spu_reg_operand"
   (and (match_operand 0 "register_operand")