/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
+the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "config/vxworks-dummy.h"
/* Note that some other tm.h files include this one and then override
whatever definitions are necessary. */
CM_EMBMEDANY
};
-/* Value of -mcmodel specified by user. */
-extern const char *sparc_cmodel_string;
/* One of CM_FOO. */
extern enum cmodel sparc_cmodel;
which requires the following macro to be true if enabled. Prior to V9,
there are no instructions to even talk about memory synchronization.
Note that the UltraSPARC III processors don't implement RMO, unlike the
- UltraSPARC II processors.
+ UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
+ either.
Default to false; for example, Solaris never enables RMO, only ever uses
total memory ordering (TMO). */
#define TARGET_CPU_sparc64 7 /* alias */
#define TARGET_CPU_ultrasparc 8
#define TARGET_CPU_ultrasparc3 9
+#define TARGET_CPU_niagara 10
+#define TARGET_CPU_niagara2 11
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
#define CPP_CPU32_DEFAULT_SPEC ""
#define ASM_CPU32_DEFAULT_SPEC ""
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
#else
%{mcpu=v9:-D__sparc_v9__} \
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
+%{mcpu=niagara:-D__sparc_v9__} \
+%{mcpu=niagara2:-D__sparc_v9__} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
#define CPP_ARCH32_SPEC ""
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
"
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
to get high 32 bits. False in V8+ or V9 because multiply stores
- a 64 bit result in a register. */
+ a 64-bit result in a register. */
#define TARGET_HARD_MUL32 \
((TARGET_V8 || TARGET_SPARCLITE \
PROCESSOR_TSC701,
PROCESSOR_V9,
PROCESSOR_ULTRASPARC,
- PROCESSOR_ULTRASPARC3
+ PROCESSOR_ULTRASPARC3,
+ PROCESSOR_NIAGARA,
+ PROCESSOR_NIAGARA2
};
/* This is set from -m{cpu,tune}=xxx. */
#define MIN_UNITS_PER_WORD 4
#endif
-#define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
+#define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD)
/* Now define the sizes of the C data types. */
/* Boundary (in *bits*) on which stack pointer should be aligned. */
/* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
- then sp+2047 is 128-bit aligned so sp is really only byte-aligned. */
+ then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
-/* Temporary hack until the FIXME above is fixed. This macro is used
- only in pad_to_arg_alignment in function.c; see the comment there
- for details about what it does. */
+/* Temporary hack until the FIXME above is fixed. */
#define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
/* ALIGN FRAMES on double word boundaries */
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+/* Make local arrays of chars word-aligned for the same reasons. */
+#define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
+
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
even those that are not normally considered general registers.
SPARC has 32 integer registers and 32 floating point registers.
- 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
+ 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
accessible. We still account for them to simplify register computations
(e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
32+32+32+4 == 100.
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
+/* Value is 1 if it is OK to rename a hard register FROM to another hard
+ register TO. We cannot rename %g1 as it may be used before the save
+ register window instruction in the prologue. */
+#define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
+
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
-/* SPARC pc isn't overloaded on a register that the compiler knows about. */
-/* #define PC_REGNUM */
-
/* Register to use for pushing function arguments. */
#define STACK_POINTER_REGNUM 14
/* Given the stack bias, the stack pointer isn't actually aligned. */
#define INIT_EXPANDERS \
do { \
- if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
+ if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
{ \
REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
because FP_REGS > GENERAL_REGS.
- It is also important that one class contain all the general and all the
- fp regs. Otherwise when spilling a DFmode reg, it may be from EXTRA_FP_REGS
- but find_reloads() may use class GENERAL_OR_FP_REGS. This will cause
- allocate_reload_reg() to bypass it causing an abort because the compiler
- thinks it doesn't have a spill reg when in fact it does.
+ It is also important that one class contain all the general and all
+ the fp regs. Otherwise when spilling a DFmode reg, it may be from
+ EXTRA_FP_REGS but find_reloads() may use class
+ GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
+ because the compiler thinks it doesn't have a spill reg when in
+ fact it does.
v9 also has 4 floating point condition code registers. Since we don't
have a class that is the union of FPCC_REGS with either of the others,
: (C) == 'c' ? FPCC_REGS \
: NO_REGS))
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
+/* The letters I, J, K, L, M, N, O, P in a register constraint string
+ can be used to stand for particular ranges of CONST_INTs.
This macro defines what the ranges are.
C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C.
`L' is used for the range of constants supported by the movcc insns.
`M' is used for the range of constants supported by the movrcc insns.
`N' is like K, but for constants wider than 32 bits.
- `O' is used for the range which is just 4096. */
+ `O' is used for the range which is just 4096.
+ `P' is free. */
+/* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
#define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
-/* 10 and 11 bit immediates are only used for a few specific insns.
+
+/* 10- and 11-bit immediates are only used for a few specific insns.
SMALL_INT is used throughout the port so we continue to use it. */
#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
-/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
- (INTVAL (X), SImode)))
+
+/* Predicate for constants that can be loaded with a sethi instruction.
+ This is the general, 64-bit aware, bitwise version that ensures that
+ only constants whose representation fits in the mask
+
+ 0x00000000fffffc00
+
+ are accepted. It will reject, for example, negative SImode constants
+ on 64-bit hosts, so correct handling is to mask the value beforehand
+ according to the mode of the instruction. */
#define SPARC_SETHI_P(X) \
(((unsigned HOST_WIDE_INT) (X) \
& ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
+
+/* Version of the above predicate for SImode constants and below. */
#define SPARC_SETHI32_P(X) \
(SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
: (C) == 'O' ? (VALUE) == 4096 \
: 0)
-/* Similar, but for floating constants, and defining letters G and H.
+/* Similar, but for CONST_DOUBLEs, and defining letters G and H.
Here VALUE is the CONST_DOUBLE rtx itself. */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
+ ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
: (C) == 'H' ? arith_double_operand (VALUE, DImode) \
- : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
: 0)
/* Given an rtx X being reloaded into a reg required to be
|| (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
&& ! TARGET_FPU) \
|| (GET_MODE (X) == TFmode \
- && ! fp_zero_operand (X, TFmode))) \
+ && ! const_zero_operand (X, TFmode))) \
? NO_REGS \
: (!FP_REG_CLASS_P (CLASS) \
&& GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
-/* Define this if the nominal address of the stack frame
+/* Define this to nonzero if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
+#define FRAME_GROWS_DOWNWARD 1
/* Offset within stack frame to start allocating local variables at.
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
first local allocated. Otherwise, it is the offset to the BEGINNING
of the first local allocated. */
-/* This allows space for one TFmode floating point value. */
+/* This allows space for one TFmode floating point value, which is used
+ by SECONDARY_MEMORY_NEEDED_RTX. */
#define STARTING_FRAME_OFFSET \
(TARGET_ARCH64 ? -16 \
: (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
-/* If we generate an insn to push BYTES bytes,
- this says how many the stack pointer really advances by.
- On SPARC, don't define this because there are no push insns. */
-/* #define PUSH_ROUNDING(BYTES) */
-
/* Offset of first parameter from the argument pointer register value.
!v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
even if this function isn't going to use it.
extern GTY(()) rtx sparc_compare_op0;
extern GTY(()) rtx sparc_compare_op1;
+extern GTY(()) rtx sparc_compare_emitted;
\f
/* Generate the special assembly code needed to tell the assembler whatever
#define EXIT_IGNORE_STACK \
(get_frame_size () != 0 \
- || current_function_calls_alloca || current_function_outgoing_args_size)
+ || cfun->calls_alloca || crtl->outgoing_args_size)
/* Define registers used by the epilogue and return instruction. */
#define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
- || (current_function_calls_eh_return && (REGNO) == 1))
+ || (crtl->calls_eh_return && (REGNO) == 1))
\f
/* Length in units of the trampoline for entering a nested function. */
else \
sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
\f
-/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
- sparc_va_start (valist, nextarg)
-
/* Generate RTL to flush the register windows so as to make arbitrary frames
available. */
#define SETUP_FRAME_ADDRESSES() \
#define DYNAMIC_CHAIN_ADDRESS(frame) \
plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
+/* Given an rtx for the frame pointer,
+ return an rtx for the address of the frame. */
+#define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS)
+
/* The return address isn't on the stack, it is in a register, so we can't
access it from the current frame pointer. We can access it from the
previous frame pointer though by reading a value from the register window
/* This is the offset of the return address to the true next instruction to be
executed for the current function. */
#define RETURN_ADDR_OFFSET \
- (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
+ (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
/* The current return address is in %i7. The return address of anything
farther back is in the register window save area at [%fp+60]. */
|| (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
|| (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
? ((sparc_cpu == PROCESSOR_ULTRASPARC \
- || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
+ || sparc_cpu == PROCESSOR_ULTRASPARC3 \
+ || sparc_cpu == PROCESSOR_NIAGARA \
+ || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
/* Provide the cost of a branch. For pre-v9 processors we use
a value of 3 to take into account the potential annulling of
On v9 and later, which have branch prediction facilities, we set
it to the depth of the pipeline as that is the cost of a
- mispredicted branch. */
+ mispredicted branch.
+
+ On Niagara, normal branches insert 3 bubbles into the pipe
+ and annulled branches insert 4 bubbles.
+
+ On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
+ branch costs 6 cycles. */
#define BRANCH_COST \
((sparc_cpu == PROCESSOR_V9 \
|| sparc_cpu == PROCESSOR_ULTRASPARC) \
? 7 \
: (sparc_cpu == PROCESSOR_ULTRASPARC3 \
- ? 9 : 3))
-
-#define PREFETCH_BLOCK \
- ((sparc_cpu == PROCESSOR_ULTRASPARC \
- || sparc_cpu == PROCESSOR_ULTRASPARC3) \
- ? 64 : 32)
-
-#define SIMULTANEOUS_PREFETCHES \
- ((sparc_cpu == PROCESSOR_ULTRASPARC) \
- ? 2 \
- : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
- ? 8 : 3))
+ ? 9 \
+ : (sparc_cpu == PROCESSOR_NIAGARA \
+ ? 4 \
+ : (sparc_cpu == PROCESSOR_NIAGARA2 \
+ ? 5 \
+ : 3))))
\f
/* Control the assembler format that we output. */
} \
} while (0)
-/* Emit a dtp-relative reference to a TLS variable. */
-
-#ifdef HAVE_AS_TLS
-#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
- sparc_output_dwarf_dtprel (FILE, SIZE, X)
-#endif
+#define SPARC_SYMBOL_REF_TLS_P(RTX) \
+ (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
else if (GET_CODE (index) == REG) \
fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
else if (GET_CODE (index) == SYMBOL_REF \
+ || GET_CODE (index) == LABEL_REF \
|| GET_CODE (index) == CONST) \
fputc ('+', FILE), output_addr_const (FILE, index); \
else gcc_unreachable (); \
} \
}
+/* TLS support defaulting to original Sun flavor. GNU extensions
+ must be activated in separate configuration files. */
#ifdef HAVE_AS_TLS
#define TARGET_TLS 1
#else
#define TARGET_TLS 0
#endif
+
#define TARGET_SUN_TLS TARGET_TLS
#define TARGET_GNU_TLS 0
-/* Define the codes that are matched by predicates in sparc.c. */
-
-#define PREDICATE_CODES \
-{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
-{"const1_operand", {CONST_INT}}, \
-{"fp_zero_operand", {CONST_DOUBLE}}, \
-{"fp_register_operand", {SUBREG, REG}}, \
-{"intreg_operand", {SUBREG, REG}}, \
-{"fcc_reg_operand", {REG}}, \
-{"fcc0_reg_operand", {REG}}, \
-{"icc_or_fcc_reg_operand", {REG}}, \
-{"call_operand", {MEM}}, \
-{"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST, CONST_DOUBLE, \
- SUBREG, REG, PLUS, LO_SUM, CONST_INT}}, \
-{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
-{"symbolic_memory_operand", {SUBREG, MEM}}, \
-{"label_ref_operand", {LABEL_REF}}, \
-{"sp64_medium_pic_operand", {CONST}}, \
-{"data_segment_operand", {SYMBOL_REF, PLUS, CONST}}, \
-{"text_segment_operand", {LABEL_REF, SYMBOL_REF, PLUS, CONST}}, \
-{"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
-{"splittable_symbolic_memory_operand", {MEM}}, \
-{"splittable_immediate_memory_operand", {MEM}}, \
-{"eq_or_neq", {EQ, NE}}, \
-{"normal_comp_operator", {GE, GT, LE, LT, GTU, LEU}}, \
-{"noov_compare_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
-{"noov_compare64_op", {NE, EQ, GE, GT, LE, LT, GEU, GTU, LEU, LTU}}, \
-{"v9_regcmp_op", {EQ, NE, GE, LT, LE, GT}}, \
-{"extend_op", {SIGN_EXTEND, ZERO_EXTEND}}, \
-{"cc_arithop", {AND, IOR, XOR}}, \
-{"cc_arithopn", {AND, IOR}}, \
-{"arith_operand", {SUBREG, REG, CONST_INT}}, \
-{"arith_add_operand", {SUBREG, REG, CONST_INT}}, \
-{"arith11_operand", {SUBREG, REG, CONST_INT}}, \
-{"arith10_operand", {SUBREG, REG, CONST_INT}}, \
-{"arith_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
-{"arith_double_add_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
-{"arith11_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
-{"arith10_double_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
-{"small_int", {CONST_INT}}, \
-{"small_int_or_double", {CONST_INT, CONST_DOUBLE}}, \
-{"uns_small_int", {CONST_INT}}, \
-{"uns_arith_operand", {SUBREG, REG, CONST_INT}}, \
-{"clobbered_register", {REG}}, \
-{"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}}, \
-{"compare_operand", {SUBREG, REG, ZERO_EXTRACT}}, \
-{"const64_operand", {CONST_INT, CONST_DOUBLE}}, \
-{"const64_high_operand", {CONST_INT, CONST_DOUBLE}}, \
-{"tgd_symbolic_operand", {SYMBOL_REF}}, \
-{"tld_symbolic_operand", {SYMBOL_REF}}, \
-{"tie_symbolic_operand", {SYMBOL_REF}}, \
-{"tle_symbolic_operand", {SYMBOL_REF}},
-
/* The number of Pmode words for the setjmp buffer. */
#define JMP_BUF_SIZE 12
+
+/* We use gcc _mcount for profiling. */
+#define NO_PROFILE_COUNTERS 0
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