/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
at Cygnus Support.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
+the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 51 Franklin Street, Fifth Floor,
-Boston, MA 02110-1301, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "config/vxworks-dummy.h"
/* Note that some other tm.h files include this one and then override
whatever definitions are necessary. */
which requires the following macro to be true if enabled. Prior to V9,
there are no instructions to even talk about memory synchronization.
Note that the UltraSPARC III processors don't implement RMO, unlike the
- UltraSPARC II processors. Niagara does not implement RMO either.
+ UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO
+ either.
Default to false; for example, Solaris never enables RMO, only ever uses
total memory ordering (TMO). */
#define TARGET_CPU_ultrasparc 8
#define TARGET_CPU_ultrasparc3 9
#define TARGET_CPU_niagara 10
+#define TARGET_CPU_niagara2 11
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
- || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
#define CPP_CPU32_DEFAULT_SPEC ""
#define ASM_CPU32_DEFAULT_SPEC ""
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
#else
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
%{mcpu=niagara:-D__sparc_v9__} \
+%{mcpu=niagara2:-D__sparc_v9__} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
"
#define CPP_ARCH32_SPEC ""
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
%{mcpu=niagara:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
"
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
to get high 32 bits. False in V8+ or V9 because multiply stores
- a 64 bit result in a register. */
+ a 64-bit result in a register. */
#define TARGET_HARD_MUL32 \
((TARGET_V8 || TARGET_SPARCLITE \
PROCESSOR_V9,
PROCESSOR_ULTRASPARC,
PROCESSOR_ULTRASPARC3,
- PROCESSOR_NIAGARA
+ PROCESSOR_NIAGARA,
+ PROCESSOR_NIAGARA2
};
/* This is set from -m{cpu,tune}=xxx. */
#define MIN_UNITS_PER_WORD 4
#endif
-#define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD)
+#define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD)
/* Now define the sizes of the C data types. */
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+/* Make local arrays of chars word-aligned for the same reasons. */
+#define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
+
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
even those that are not normally considered general registers.
SPARC has 32 integer registers and 32 floating point registers.
- 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
+ 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
accessible. We still account for them to simplify register computations
(e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
32+32+32+4 == 100.
/* Given the stack bias, the stack pointer isn't actually aligned. */
#define INIT_EXPANDERS \
do { \
- if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
+ if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
{ \
REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
#define EXIT_IGNORE_STACK \
(get_frame_size () != 0 \
- || current_function_calls_alloca || current_function_outgoing_args_size)
+ || cfun->calls_alloca || crtl->outgoing_args_size)
/* Define registers used by the epilogue and return instruction. */
#define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
- || (current_function_calls_eh_return && (REGNO) == 1))
+ || (crtl->calls_eh_return && (REGNO) == 1))
\f
/* Length in units of the trampoline for entering a nested function. */
else \
sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
\f
-/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
- sparc_va_start (valist, nextarg)
-
/* Generate RTL to flush the register windows so as to make arbitrary frames
available. */
#define SETUP_FRAME_ADDRESSES() \
/* This is the offset of the return address to the true next instruction to be
executed for the current function. */
#define RETURN_ADDR_OFFSET \
- (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
+ (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
/* The current return address is in %i7. The return address of anything
farther back is in the register window save area at [%fp+60]. */
|| (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
? ((sparc_cpu == PROCESSOR_ULTRASPARC \
|| sparc_cpu == PROCESSOR_ULTRASPARC3 \
- || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
+ || sparc_cpu == PROCESSOR_NIAGARA \
+ || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
/* Provide the cost of a branch. For pre-v9 processors we use
a value of 3 to take into account the potential annulling of
mispredicted branch.
On Niagara, normal branches insert 3 bubbles into the pipe
- and annulled branches insert 4 bubbles. */
+ and annulled branches insert 4 bubbles.
+
+ On Niagara-2, a not-taken branch costs 1 cycle whereas a taken
+ branch costs 6 cycles. */
#define BRANCH_COST \
((sparc_cpu == PROCESSOR_V9 \
? 9 \
: (sparc_cpu == PROCESSOR_NIAGARA \
? 4 \
- : 3)))
+ : (sparc_cpu == PROCESSOR_NIAGARA2 \
+ ? 5 \
+ : 3))))
\f
/* Control the assembler format that we output. */
else if (GET_CODE (index) == REG) \
fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
else if (GET_CODE (index) == SYMBOL_REF \
+ || GET_CODE (index) == LABEL_REF \
|| GET_CODE (index) == CONST) \
fputc ('+', FILE), output_addr_const (FILE, index); \
else gcc_unreachable (); \
/* The number of Pmode words for the setjmp buffer. */
#define JMP_BUF_SIZE 12
+
+/* We use gcc _mcount for profiling. */
+#define NO_PROFILE_COUNTERS 0
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