/* Definitions of target machine for GNU compiler, for Sun SPARC.
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
- 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.
Contributed by Michael Tiemann (tiemann@cygnus.com).
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
capable cpu's. */
#define TARGET_CPU_sparc 0
-#define TARGET_CPU_v7 0 /* alias for previous */
-#define TARGET_CPU_sparclet 1
-#define TARGET_CPU_sparclite 2
-#define TARGET_CPU_v8 3 /* generic v8 implementation */
-#define TARGET_CPU_supersparc 4
-#define TARGET_CPU_hypersparc 5
-#define TARGET_CPU_sparc86x 6
+#define TARGET_CPU_v7 0 /* alias */
+#define TARGET_CPU_cypress 0 /* alias */
+#define TARGET_CPU_v8 1 /* generic v8 implementation */
+#define TARGET_CPU_supersparc 2
+#define TARGET_CPU_hypersparc 3
+#define TARGET_CPU_leon 4
+#define TARGET_CPU_sparclite 5
+#define TARGET_CPU_f930 5 /* alias */
+#define TARGET_CPU_f934 5 /* alias */
#define TARGET_CPU_sparclite86x 6
-#define TARGET_CPU_v9 7 /* generic v9 implementation */
-#define TARGET_CPU_sparcv9 7 /* alias */
-#define TARGET_CPU_sparc64 7 /* alias */
-#define TARGET_CPU_ultrasparc 8
-#define TARGET_CPU_ultrasparc3 9
-#define TARGET_CPU_niagara 10
-#define TARGET_CPU_niagara2 11
+#define TARGET_CPU_sparclet 7
+#define TARGET_CPU_tsc701 7 /* alias */
+#define TARGET_CPU_v9 8 /* generic v9 implementation */
+#define TARGET_CPU_sparcv9 8 /* alias */
+#define TARGET_CPU_sparc64 8 /* alias */
+#define TARGET_CPU_ultrasparc 9
+#define TARGET_CPU_ultrasparc3 10
+#define TARGET_CPU_niagara 11
+#define TARGET_CPU_niagara2 12
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
#endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
+#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
+#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
+#endif
+
#if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
#define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
#define ASM_CPU32_DEFAULT_SPEC ""
#define ASM_CPU32_DEFAULT_SPEC ""
#endif
-#if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
-#define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
-#define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
+#if TARGET_CPU_DEFAULT == TARGET_CPU_leon
+#define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
+#define ASM_CPU32_DEFAULT_SPEC ""
#endif
#endif
for handling -mcpu=xxx switches. */
#define CPP_CPU_SPEC "\
%{msoft-float:-D_SOFT_FLOAT} \
-%{mcypress:} \
-%{msparclite:-D__sparclite__} \
-%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
-%{mv8:-D__sparc_v8__} \
-%{msupersparc:-D__supersparc__ -D__sparc_v8__} \
%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
%{mcpu=sparclite:-D__sparclite__} \
%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
+%{mcpu=sparclite86x:-D__sparclite86x__} \
%{mcpu=v8:-D__sparc_v8__} \
%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
-%{mcpu=sparclite86x:-D__sparclite86x__} \
+%{mcpu=leon:-D__leon__ -D__sparc_v8__} \
%{mcpu=v9:-D__sparc_v9__} \
%{mcpu=ultrasparc:-D__sparc_v9__} \
%{mcpu=ultrasparc3:-D__sparc_v9__} \
%{mcpu=niagara:-D__sparc_v9__} \
%{mcpu=niagara2:-D__sparc_v9__} \
-%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
+%{!mcpu*:%(cpp_cpu_default)} \
"
#define CPP_ARCH32_SPEC ""
#define CPP_ARCH64_SPEC "-D__arch64__"
%{!m32:%{!m64:%(cpp_arch_default)}} \
"
-/* Macros to distinguish endianness. */
+/* Macro to distinguish endianness. */
#define CPP_ENDIAN_SPEC "\
-%{mlittle-endian:-D__LITTLE_ENDIAN__} \
-%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
+%{mlittle-endian:-D__LITTLE_ENDIAN__}"
/* Macros to distinguish the particular subtarget. */
#define CPP_SUBTARGET_SPEC ""
#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
-/* Prevent error on `-sun4' and `-target sun4' options. */
/* This used to translate -dalign to -malign, but that is no good
because it can't turn off the usual meaning of making debugging dumps. */
-/* Translate old style -m<cpu> into new style -mcpu=<cpu>.
- ??? Delete support for -m<cpu> for 2.9. */
-
-#define CC1_SPEC "\
-%{sun4:} %{target:} \
-%{mcypress:-mcpu=cypress} \
-%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
-%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
-"
+
+#define CC1_SPEC ""
/* Override in target specific files. */
#define ASM_CPU_SPEC "\
%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
-%{msparclite:-Asparclite} \
-%{mf930:-Asparclite} %{mf934:-Asparclite} \
%{mcpu=sparclite:-Asparclite} \
%{mcpu=sparclite86x:-Asparclite} \
%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
%{mcpu=niagara:%{!mv8plus:-Av9b}} \
%{mcpu=niagara2:%{!mv8plus:-Av9b}} \
-%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
+%{!mcpu*:%(asm_cpu_default)} \
"
/* Word size selection, among other things.
%{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
%(asm_cpu) %(asm_relax)"
-#define AS_NEEDS_DASH_FOR_PIPED_INPUT
-
/* This macro defines names of additional specifications to put in the specs
that can be used in various specifications like CC1_SPEC. Its definition
is an initializer with a subgrouping for each command option.
-mno-app-regs). */
#define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
-/* Processor type.
- These must match the values for the cpu attribute in sparc.md. */
-enum processor_type {
- PROCESSOR_V7,
- PROCESSOR_CYPRESS,
- PROCESSOR_V8,
- PROCESSOR_SUPERSPARC,
- PROCESSOR_SPARCLITE,
- PROCESSOR_F930,
- PROCESSOR_F934,
- PROCESSOR_HYPERSPARC,
- PROCESSOR_SPARCLITE86X,
- PROCESSOR_SPARCLET,
- PROCESSOR_TSC701,
- PROCESSOR_V9,
- PROCESSOR_ULTRASPARC,
- PROCESSOR_ULTRASPARC3,
- PROCESSOR_NIAGARA,
- PROCESSOR_NIAGARA2
-};
-
-/* This is set from -m{cpu,tune}=xxx. */
-extern enum processor_type sparc_cpu;
-
/* Recast the cpu class to be the cpu attribute.
Every file includes us, but not every file includes insn-attr.h. */
#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
#define OPTION_DEFAULT_SPECS \
{"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
- {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
-
-/* sparc_select[0] is reserved for the default cpu. */
-struct sparc_cpu_select
-{
- const char *string;
- const char *const name;
- const int set_tune_p;
- const int set_arch_p;
-};
-
-extern struct sparc_cpu_select sparc_select[];
+ {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" }
\f
/* target machine storage layout */
not be a register used by the prologue. */
#define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
+/* Register which holds the global offset table, if any. */
+
+#define GLOBAL_OFFSET_TABLE_REGNUM 23
+
/* Register which holds offset table for position-independent
data references. */
-#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
+#define PIC_OFFSET_TABLE_REGNUM \
+ (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
/* Pick a default value we can notice from override_options:
!v9: Default is on.
#define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
-/* The following macro defines cover classes for Integrated Register
- Allocator. Cover classes is a set of non-intersected register
- classes covering all hard registers used for register allocation
- purpose. Any move between two registers of a cover class should be
- cheaper than load or store of the registers. The macro value is
- array of register classes with LIM_REG_CLASSES used as the end
- marker. */
-
-#define IRA_COVER_CLASSES \
-{ \
- GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \
-}
-
/* Defines invalid mode changes. Borrowed from pa64-regs.h.
SImode loads to floating-point registers are not zero-extended.
#define SPARC_SETHI32_P(X) \
(SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
-/* Given an rtx X being reloaded into a reg required to be
- in class CLASS, return the class of reg to actually use.
- In general this is just CLASS; but on some machines
- in some cases it is preferable to use a more restrictive class. */
-/* - We can't load constants into FP registers.
- - We can't load FP constants into integer registers when soft-float,
- because there is no soft-float pattern with a r/F constraint.
- - We can't load FP constants into integer registers for TFmode unless
- it is 0.0L, because there is no movtf pattern with a r/F constraint.
- - Try and reload integer constants (symbolic or otherwise) back into
- registers directly, rather than having them dumped to memory. */
-
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- (CONSTANT_P (X) \
- ? ((FP_REG_CLASS_P (CLASS) \
- || (CLASS) == GENERAL_OR_FP_REGS \
- || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
- || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
- && ! TARGET_FPU) \
- || (GET_MODE (X) == TFmode \
- && ! const_zero_operand (X, TFmode))) \
- ? NO_REGS \
- : (!FP_REG_CLASS_P (CLASS) \
- && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
- ? GENERAL_REGS \
- : (CLASS)) \
- : (CLASS))
-
/* Return the register class of a scratch register needed to load IN into
a register of class CLASS in MODE.
addresses which require two reload registers. */
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
-
-/* Nonzero if the constant value X is a legitimate general operand.
- Anything can be made to work except floating point constants.
- If TARGET_VIS, 0.0 can be made to work as well. */
-
-#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
-
-/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
- and check its validity for a certain class.
- We have two alternate definitions for each of them.
- The usual definition accepts all pseudo regs; the other rejects
- them unless they have been allocated suitable hard regs.
- The symbol REG_OK_STRICT causes the latter definition to be used.
-
- Most source files want to accept pseudo regs in the hope that
- they will get allocated to the class that the insn wants them to be in.
- Source files for reload pass need to be strict.
- After reload, it makes no difference, since pseudo regs have
- been eliminated by then. */
-
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) \
- (REGNO (X) < 32 \
- || REGNO (X) == FRAME_POINTER_REGNUM \
- || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
-
-#else
-
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
\f
/* Should gcc use [%reg+%lo(xx)+offset] addresses? */
#define USE_AS_OFFSETABLE_LO10 0
#endif
\f
-/* On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
- ordinarily. This changes a bit when generating PIC. The details are
- in sparc.c's implementation of TARGET_LEGITIMATE_ADDRESS_P. */
-
-#define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
-
-#define RTX_OK_FOR_BASE_P(X) \
- ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
- || (GET_CODE (X) == SUBREG \
- && GET_CODE (SUBREG_REG (X)) == REG \
- && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define RTX_OK_FOR_INDEX_P(X) \
- ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
- || (GET_CODE (X) == SUBREG \
- && GET_CODE (SUBREG_REG (X)) == REG \
- && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
-
-#define RTX_OK_FOR_OFFSET_P(X) \
- (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
-
-#define RTX_OK_FOR_OLO10_P(X) \
- (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
-
-\f
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
macro is used in only one place: `find_reloads_address' in reload.c. */
#define DITF_CONVERSION_LIBFUNCS 0
#define SUN_INTEGER_MULTIPLY_64 0
-/* Compute extra cost of moving data between one register class
- and another. */
-#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
- || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
- || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
- ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
- || sparc_cpu == PROCESSOR_ULTRASPARC3 \
- || sparc_cpu == PROCESSOR_NIAGARA \
- || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2)
-
/* Provide the cost of a branch. For pre-v9 processors we use
a value of 3 to take into account the potential annulling of
the delay slot (which ends up being a bubble in the pipeline slot)
} \
} while (0)
-#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
- ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
- || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
-
-/* Print operand X (an rtx) in assembler syntax to file FILE.
- CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null. */
-
-#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
-
-/* Print a memory address as an operand to reference that memory location. */
-
-#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx base, index = 0; \
- int offset = 0; \
- register rtx addr = ADDR; \
- if (GET_CODE (addr) == REG) \
- fputs (reg_names[REGNO (addr)], FILE); \
- else if (GET_CODE (addr) == PLUS) \
- { \
- if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
- offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
- else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
- offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
- else \
- base = XEXP (addr, 0), index = XEXP (addr, 1); \
- if (GET_CODE (base) == LO_SUM) \
- { \
- gcc_assert (USE_AS_OFFSETABLE_LO10 \
- && TARGET_ARCH64 \
- && ! TARGET_CM_MEDMID); \
- output_operand (XEXP (base, 0), 0); \
- fputs ("+%lo(", FILE); \
- output_address (XEXP (base, 1)); \
- fprintf (FILE, ")+%d", offset); \
- } \
- else \
- { \
- fputs (reg_names[REGNO (base)], FILE); \
- if (index == 0) \
- fprintf (FILE, "%+d", offset); \
- else if (GET_CODE (index) == REG) \
- fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
- else if (GET_CODE (index) == SYMBOL_REF \
- || GET_CODE (index) == LABEL_REF \
- || GET_CODE (index) == CONST) \
- fputc ('+', FILE), output_addr_const (FILE, index); \
- else gcc_unreachable (); \
- } \
- } \
- else if (GET_CODE (addr) == MINUS \
- && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
- { \
- output_addr_const (FILE, XEXP (addr, 0)); \
- fputs ("-(", FILE); \
- output_addr_const (FILE, XEXP (addr, 1)); \
- fputs ("-.)", FILE); \
- } \
- else if (GET_CODE (addr) == LO_SUM) \
- { \
- output_operand (XEXP (addr, 0), 0); \
- if (TARGET_CM_MEDMID) \
- fputs ("+%l44(", FILE); \
- else \
- fputs ("+%lo(", FILE); \
- output_address (XEXP (addr, 1)); \
- fputc (')', FILE); \
- } \
- else if (flag_pic && GET_CODE (addr) == CONST \
- && GET_CODE (XEXP (addr, 0)) == MINUS \
- && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
- && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
- && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
- { \
- addr = XEXP (addr, 0); \
- output_addr_const (FILE, XEXP (addr, 0)); \
- /* Group the args of the second CONST in parenthesis. */ \
- fputs ("-(", FILE); \
- /* Skip past the second CONST--it does nothing for us. */\
- output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
- /* Close the parenthesis. */ \
- fputc (')', FILE); \
- } \
- else \
- { \
- output_addr_const (FILE, addr); \
- } \
-}
-
/* TLS support defaulting to original Sun flavor. GNU extensions
must be activated in separate configuration files. */
#ifdef HAVE_AS_TLS
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