sparc64 in 32 bit environments, so for now we only use `sparc64' in
64 bit environments. */
-#ifdef SPARC_BI_ARCH
-
-#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \
--D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
-#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \
--D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
-
-#else
-
#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
-#endif
-
#define CPP_ARCH_DEFAULT_SPEC \
(DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
#define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
\f
-#ifdef SPARC_BI_ARCH
-#define NO_BUILTIN_PTRDIFF_TYPE
-#define NO_BUILTIN_SIZE_TYPE
-#endif
#define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
#define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
#ifndef SUNOS4_SHARED_LIBRARIES
#define SUNOS4_SHARED_LIBRARIES 0
#endif
-
-
-/* Use text section for a constant
- unless we need more alignment than that offers. */
-/* This is defined differently for v9 in a cover file. */
-#define SELECT_RTX_SECTION(MODE, X, ALIGN) \
-{ \
- if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
- && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \
- text_section (); \
- else \
- data_section (); \
-}
\f
/* Standard register usage. */
stored from the compare operation. Note that we can't use "rtx" here
since it hasn't been defined! */
-extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1;
+extern GTY(()) rtx sparc_compare_op0;
+extern GTY(()) rtx sparc_compare_op1;
\f
/* Generate the special assembly code needed to tell the assembler whatever
On the SPARC this is never true. */
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
-
-/* If we are referencing a function make the SYMBOL_REF special.
- In the Embedded Medium/Anywhere code model, %g4 points to the data segment
- so we must not add it to function addresses. */
-
-#define ENCODE_SECTION_INFO(DECL, FIRST) \
- do { \
- if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
- SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
- } while (0)
\f
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define LTTF2_LIBCALL "_Q_flt"
#define LETF2_LIBCALL "_Q_fle"
+/* Assume by default that the _Qp_* 64-bit libcalls are implemented such
+ that the inputs are fully consumed before the output memory is clobbered. */
+
+#define TARGET_BUGGY_QP_LIB 0
+
/* We can define the TFmode sqrt optab only if TARGET_FPU. This is because
with soft-float, the SFmode and DFmode sqrt instructions will be absent,
and the compiler will notice and try to use the TFmode sqrt instruction
of the libgcc2 functions is used. */
#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
-/* Compute the cost of computing a constant rtl expression RTX
- whose rtx-code is CODE. The body of this macro is a portion
- of a switch statement. If the code is computed here,
- return it with a return statement. Otherwise, break from the switch. */
-
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- case CONST_INT: \
- if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
- return 0; \
- case HIGH: \
- return 2; \
- case CONST: \
- case LABEL_REF: \
- case SYMBOL_REF: \
- return 4; \
- case CONST_DOUBLE: \
- if (GET_MODE (RTX) == DImode) \
- if ((XINT (RTX, 3) == 0 \
- && (unsigned) XINT (RTX, 2) < 0x1000) \
- || (XINT (RTX, 3) == -1 \
- && XINT (RTX, 2) < 0 \
- && XINT (RTX, 2) >= -0x1000)) \
- return 0; \
- return 8;
-
-#define ADDRESS_COST(RTX) 1
-
/* Compute extra cost of moving data between one register class
and another. */
#define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
: (sparc_cpu == PROCESSOR_ULTRASPARC3 \
? 9 : 3))
-/* Provide the costs of a rtl expression. This is in the body of a
- switch on CODE. The purpose for the cost of MULT is to encourage
- `synth_mult' to find a synthetic multiply when reasonable.
+/* The cases that RTX_COSTS handles. */
- If we need more than 12 insns to do a multiply, then go out-of-line,
- since the call overhead will be < 10% of the cost of the multiply. */
+#define RTX_COSTS_CASES \
+case PLUS: case MINUS: case ABS: case NEG: \
+case FLOAT: case UNSIGNED_FLOAT: \
+case FIX: case UNSIGNED_FIX: \
+case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
+case SQRT: \
+case COMPARE: case IF_THEN_ELSE: \
+case MEM: \
+case MULT: case DIV: case UDIV: case MOD: case UMOD: \
+case CONST_INT: case HIGH: case CONST: \
+case LABEL_REF: case SYMBOL_REF: case CONST_DOUBLE:
+
+/* Provide the costs of a rtl expression. This is in the body of a
+ switch on CODE. */
#define RTX_COSTS(X,CODE,OUTER_CODE) \
- case MULT: \
- if (sparc_cpu == PROCESSOR_ULTRASPARC) \
- return (GET_MODE (X) == DImode ? \
- COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \
- if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
- return COSTS_N_INSNS (6); \
- return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
- case DIV: \
- case UDIV: \
- case MOD: \
- case UMOD: \
- if (sparc_cpu == PROCESSOR_ULTRASPARC) \
- return (GET_MODE (X) == DImode ? \
- COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \
- if (sparc_cpu == PROCESSOR_ULTRASPARC3) \
- return (GET_MODE (X) == DImode ? \
- COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); \
- return COSTS_N_INSNS (25); \
- /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
- so that cse will favor the latter. */ \
- case FLOAT: \
- case FIX: \
- return 19;
+ RTX_COSTS_CASES \
+ return sparc_rtx_costs(X,CODE,OUTER_CODE);
+
+#define ADDRESS_COST(RTX) 1
#define PREFETCH_BLOCK \
((sparc_cpu == PROCESSOR_ULTRASPARC \
/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
Used for C++ multiple inheritance. */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
-do { \
- int reg = 0; \
- \
- if (TARGET_ARCH64 \
- && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION)))) \
- reg = 1; \
- if ((DELTA) >= 4096 || (DELTA) < -4096) \
- fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n", \
- (int)(DELTA), reg, reg); \
- else \
- fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
- fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n"); \
- fprintf (FILE, "\tcall\t"); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, ", 0\n"); \
- fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n"); \
-} while (0)
+#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
+ sparc_output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION)
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
#define PREDICATE_CODES \
{"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
+{"const1_operand", {CONST_INT}}, \
{"fp_zero_operand", {CONST_DOUBLE}}, \
{"fp_register_operand", {SUBREG, REG}}, \
{"intreg_operand", {SUBREG, REG}}, \