gcc:

[pf3gnuchains/gcc-fork.git] / gcc / config / sh / sh.opt

diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
index 8aa0c9f..dbe077c 100644 (file)
--- a/gcc/config/sh/sh.opt
+++ b/gcc/config/sh/sh.opt
@@ -49,7 +49,7 @@ Generate SH2 code
 
 m2a
 Target RejectNegative Condition(SUPPORT_SH2A)
-Generate SH2a code
+Generate default double-precision SH2a-FPU code
 
 m2a-nofpu
 Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
@@ -57,11 +57,11 @@ Generate SH2a FPU-less code
 
 m2a-single
 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
-Generate default single-precision SH2a code
+Generate default single-precision SH2a-FPU code
 
 m2a-single-only
 Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
-Generate only single-precision SH2a code
+Generate only single-precision SH2a-FPU code
 
 m2e
 Target RejectNegative Condition(SUPPORT_SH2E)
@@ -244,13 +244,14 @@ mdivsi3_libfunc=
 Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
 Specify name for 32 bit signed division function
 
+mfmovd
+Target RejectNegative Mask(FMOVD)
+Enable the use of 64-bit floating point registers in fmov instructions.  See -mdalign if 64-bit alignment is required.
+
 mfixed-range=
 Target RejectNegative Joined Var(sh_fixed_range_str)
 Specify range of registers to make fixed
 
-mfmovd
-Target RejectNegative Mask(FMOVD) Undocumented
-
 mfused-madd
 Target Var(TARGET_FMAC)
 Enable the use of the fused floating point multiply-accumulate operation
@@ -315,7 +316,7 @@ Follow Renesas (formerly Hitachi) / SuperH calling conventions
 
 mspace
 Target Report RejectNegative Mask(SMALLCODE)
-Deprecated. Use -Os instead
+Deprecated.  Use -Os instead
 
 multcost=
 Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)