;;- Machine description for Hitachi / SuperH SH.
-;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+;; Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
;; Free Software Foundation, Inc.
;; Contributed by Steve Chamberlain (sac@cygnus.com).
;; Improved by Jim Wilson (wilson@cygnus.com).
(UNSPEC_FSINA 16)
(UNSPEC_NSB 17)
(UNSPEC_ALLOCO 18)
+ (UNSPEC_EH_RETURN 19)
+ (UNSPEC_TLSGD 20)
+ (UNSPEC_TLSLDM 21)
+ (UNSPEC_TLSIE 22)
+ (UNSPEC_DTPOFF 23)
+ (UNSPEC_GOTTPOFF 24)
+ (UNSPEC_TPOFF 25)
;; These are used with unspec_volatile.
(UNSPECV_BLOCKAGE 0)
;; Target CPU.
(define_attr "cpu"
- "sh1,sh2,sh3,sh3e,sh4,sh5"
+ "sh1,sh2,sh2e,sh3,sh3e,sh4,sh5"
(const (symbol_ref "sh_cpu_attr")))
(define_attr "endian" "big,little"
;; ftrc_s fix_truncsfsi2_i4
;; dfdiv double precision floating point divide (or square root)
;; cwb ic_invalidate_line_i
+;; tls_load load TLS related address
;; arith_media SHmedia arithmetic, logical, and shift instructions
;; cbranch_media SHmedia conditional branch instructions
;; cmp_media SHmedia compare instructions
;; fpconv_media SHmedia single precision floating point conversions
;; fstore_media SHmedia floating point register store instructions
;; gettr_media SHmedia gettr instruction
-;; invalidate_line_media SHmedia invaldiate_line sequence
+;; invalidate_line_media SHmedia invalidate_line sequence
;; jump_media SHmedia unconditional branch instructions
;; load_media SHmedia general register load instructions
;; pt_media SHmedia pt instruction (expanded by assembler)
;; mcmp_media SHmedia multimedia compare, absolute, saturating ops
;; mac_media SHmedia mac-style fixed point operations
;; d2mpy_media SHmedia: two 32 bit integer multiplies
-;; atrans SHmedia approximate transcendential functions
+;; atrans SHmedia approximate transcendental functions
;; ustore_media SHmedia unaligned stores
;; nil no-op move, will be deleted.
(define_attr "type"
- "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
+ "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,fload,store,move,fmove,smpy,dmpy,return,pload,prset,pstore,prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fdiv,ftrc_s,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,mem_fpscr,gp_fpscr,cwb,tls_load,arith_media,cbranch_media,cmp_media,dfdiv_media,dfmul_media,dfparith_media,dfpconv_media,dmpy_media,fcmp_media,fdiv_media,fload_media,fmove_media,fparith_media,fpconv_media,fstore_media,gettr_media,invalidate_line_media,jump_media,load_media,pt_media,ptabs_media,store_media,mcmp_media,mac_media,d2mpy_media,atrans_media,ustore_media,nil,other"
(const_string "other"))
;; We define a new attribute namely "insn_class".We use
(eq_attr "type" "jump")
(cond [(eq_attr "med_branch_p" "yes")
(const_int 2)
- (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
+ (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
(symbol_ref "INSN"))
- (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
+ (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
(symbol_ref "code_for_indirect_jump_scratch")))
(if_then_else (eq_attr "braf_branch_p" "yes")
(const_int 6)
(define_delay
(and (eq_attr "type" "cbranch")
(ne (symbol_ref "TARGET_SH2") (const_int 0)))
- [(eq_attr "in_delay_slot" "yes") (eq_attr "cond_delay_slot" "yes") (nil)])
+ ;; SH2e has a hardware bug that pretty much prohibits the use of
+ ;; annuled delay slots.
+ [(eq_attr "in_delay_slot" "yes") (and (eq_attr "cond_delay_slot" "yes")
+ (not (eq_attr "cpu" "sh2e"))) (nil)])
\f
;; -------------------------------------------------------------------------
;; SImode signed integer comparisons
; the udivsi3 libcall has the same name, we must consider all registers
; clobbered that are in the union of the registers clobbered by the
; shmedia and the shcompact implementation. Note, if the shcompact
-; implemenation actually used shcompact code, we'd need to clobber
+; implementation actually used shcompact code, we'd need to clobber
; also r23 and fr23.
(define_insn "udivsi3_i1_media"
[(set (match_operand:SI 0 "register_operand" "=z")
""
"
{
- rtx first = 0, last;
+ rtx first, last;
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH2E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
{
operands[1] = force_reg (SImode, operands[1]);
operands[2] = force_reg (SImode, operands[2]);
- last = gen_udivsi3_i4_media (operands[0], operands[1], operands[2]);
- first = last;
+ emit_insn (gen_udivsi3_i4_media (operands[0], operands[1], operands[2]));
+ DONE;
}
else if (TARGET_SH5)
{
gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
last = gen_udivsi3_i1 (operands[0], operands[3]);
}
- if (! first)
- {
- first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
- }
+ first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
last = emit_insn (last);
/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
invariant code motion can move it. */
; the sdivsi3 libcall has the same name, we must consider all registers
; clobbered that are in the union of the registers clobbered by the
; shmedia and the shcompact implementation. Note, if the shcompact
-; implemenation actually used shcompact code, we'd need to clobber
+; implementation actually used shcompact code, we'd need to clobber
; also r22, r23 and fr23.
(define_insn "divsi3_i1_media"
[(set (match_operand:SI 0 "register_operand" "=z")
""
"
{
- rtx first = 0, last;
+ rtx first, last;
operands[3] = gen_reg_rtx (Pmode);
/* Emit the move of the address to a pseudo outside of the libcall. */
- if (TARGET_HARD_SH4 && TARGET_SH3E)
+ if (TARGET_HARD_SH4 && TARGET_SH2E)
{
emit_move_insn (operands[3],
gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
{
operands[1] = force_reg (SImode, operands[1]);
operands[2] = force_reg (SImode, operands[2]);
- last = gen_divsi3_i4_media (operands[0], operands[1], operands[2]);
- first = last;
+ emit_insn (gen_divsi3_i4_media (operands[0], operands[1], operands[2]));
+ DONE;
}
else if (TARGET_SH5)
{
emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
last = gen_divsi3_i1 (operands[0], operands[3]);
}
- if (! first)
- {
- first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
- emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
- }
+ first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
last = emit_insn (last);
/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
invariant code motion can move it. */
(define_insn_and_split "anddi3"
[(set (match_operand:DI 0 "arith_reg_operand" "=r,r,r")
(and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
- (match_operand:DI 2 "and_operand" "r,P,n")))]
+ (match_operand:DI 2 "and_operand" "r,P,Z")))]
"TARGET_SHMEDIA"
"@
and %1, %2, %0
xor %1, %2, %0
xori %1, %2, %0"
[(set_attr "type" "arith_media")])
+
+;; Combiner bridge pattern for 2 * sign extend -> logical op -> truncate.
+;; converts 2 * sign extend -> logical op into logical op -> sign extend
+(define_split
+ [(set (match_operand:DI 0 "arith_reg_operand" "")
+ (sign_extend:DI (match_operator 4 "binary_logical_operator"
+ [(match_operand 1 "any_register_operand" "")
+ (match_operand 2 "any_register_operand" "")])))]
+ "TARGET_SHMEDIA"
+ [(set (match_dup 5) (match_dup 4))
+ (set (match_dup 0) (sign_extend:DI (match_dup 5)))]
+"
+{
+ enum machine_mode inmode = GET_MODE (operands[1]);
+ int regno, offset = 0;
+
+ if (GET_CODE (operands[0]) == SUBREG)
+ {
+ offset = SUBREG_BYTE (operands[0]);
+ operands[0] = SUBREG_REG (operands[0]);
+ }
+ if (GET_CODE (operands[0]) != REG)
+ abort ();
+ if (! TARGET_LITTLE_ENDIAN)
+ offset += 8 - GET_MODE_SIZE (inmode);
+ operands[5] = gen_rtx_SUBREG (inmode, operands[0], offset);
+}")
\f
;; -------------------------------------------------------------------------
;; Shifts and rotates
(and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "const_int_operand" ""))
(match_operand:SI 3 "const_int_operand" "")))]
- "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
+ "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
DONE;")
(match_operand:SI 2 "const_int_operand" ""))
(match_operand:SI 3 "const_int_operand" "")))
(clobber (reg:SI T_REG))]
- "TARGET_SH1 && (unsigned)INTVAL (operands[2]) < 32"
+ "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
[(use (reg:SI R0_REG))]
"if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
DONE;")
(define_insn "push_fpul"
[(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
- "TARGET_SH3E && ! TARGET_SH5"
+ "TARGET_SH2E && ! TARGET_SH5"
"sts.l fpul,@-r15"
[(set_attr "type" "store")
(set_attr "late_fp_use" "yes")
(define_insn "pop_fpul"
[(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
- "TARGET_SH3E && ! TARGET_SH5"
+ "TARGET_SH2E && ! TARGET_SH5"
"lds.l @r15+,fpul"
[(set_attr "type" "load")
(set_attr "hit_stack" "yes")])
"TARGET_SH1 && ! TARGET_SH5"
"")
+(define_expand "push_fpscr"
+ [(const_int 0)]
+ "TARGET_SH3E"
+ "
+{
+ rtx insn = emit_insn (gen_fpu_switch (gen_rtx (MEM, PSImode,
+ gen_rtx (PRE_DEC, Pmode,
+ stack_pointer_rtx)),
+ get_fpscr_rtx ()));
+ REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ DONE;
+}")
+
+(define_expand "pop_fpscr"
+ [(const_int 0)]
+ "TARGET_SH3E"
+ "
+{
+ rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
+ gen_rtx (MEM, PSImode,
+ gen_rtx (POST_INC, Pmode,
+ stack_pointer_rtx))));
+ REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
+ DONE;
+}")
+
;; These two patterns can happen as the result of optimization, when
;; comparisons get simplified to a move of zero or 1 into the T reg.
;; They don't disappear completely, because the T reg is a fixed hard reg.
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,r")
(match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,i"))]
"TARGET_SH1
- && ! TARGET_SH3E
+ && ! TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
;; ??? This allows moves from macl to fpul to be recognized, but these moves
;; will require a reload.
+;; ??? We can't include f/f because we need the proper FPSCR setting when
+;; TARGET_FMOVD is in effect, and mode switching is done before reload.
(define_insn "movsi_ie"
- [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,y")
- (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y"))]
- "TARGET_SH3E
+ [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+ (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+ "TARGET_SH2E
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
fake %1,%0
lds %1,%0
sts %1,%0
+ fsts fpul,%0
+ flds %1,fpul
+ fmov %1,%0
! move optimized away"
- [(set_attr "type" "pcload_si,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,nil")
- (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*")
- (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
+ [(set_attr "type" "pcload_si,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
+ (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
+ (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
(define_insn "movsi_i_lowpart"
[(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
(define_insn "*movsi_media"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,m,f,rU,f,f,r,*b,T"))]
+ (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,m,f,rU,f,f,r,*b,T"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
+ || sh_register_operand (operands[1], SImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1
+ st%M0.l %m0, %N1
fld%M1.s %m1, %0
fst%M0.s %m0, %1
fmov.ls %N1, %0
(define_insn "*movsi_media_nofpu"
[(set (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,m,*b,r,b")
- (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,r,r,*b,T"))]
+ (match_operand:SI 1 "general_movsrc_operand" "r,JS,ns,m,rU,r,*b,T"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
+ || sh_register_operand (operands[1], SImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1
+ st%M0.l %m0, %N1
ptabs %1, %0
gettr %1, %0
pt %1, %0"
{
rtx sfun, tramp;
+ tramp = force_reg (Pmode, operands[0]);
sfun = force_reg (Pmode, gen_rtx_SYMBOL_REF (Pmode, \"__init_trampoline\"));
- tramp = gen_rtx_REG (SImode, R0_REG);
- emit_move_insn (tramp, operands[0]);
emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
(define_insn "*movqi_media"
[(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:QI 1 "general_movsrc_operand" "r,JS,m,r"))]
+ (match_operand:QI 1 "general_movsrc_operand" "r,JS,m,rU"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], QImode)
- || arith_reg_operand (operands[1], QImode))"
+ || arith_reg_or_0_operand (operands[1], QImode))"
"@
add.l %1, r63, %0
movi %1, %0
ld%M1.ub %m1, %0
- st%M0.b %m0, %1"
+ st%M0.b %m0, %N1"
[(set_attr "type" "arith_media,arith_media,load_media,store_media")])
(define_expand "movqi"
(define_insn "*movhi_media"
[(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m")
- (match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,r"))]
+ (match_operand:HI 1 "general_movsrc_operand" "r,JS,n,m,rU"))]
"TARGET_SHMEDIA
&& (arith_reg_operand (operands[0], HImode)
- || arith_reg_operand (operands[1], HImode))"
+ || arith_reg_or_0_operand (operands[1], HImode))"
"@
add.l %1, r63, %0
movi %1, %0
#
ld%M1.w %m1, %0
- st%M0.w %m0, %1"
+ st%M0.w %m0, %N1"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")])
(define_split
operands[3] = gen_rtx_REG (DImode, REGNO (operands[2]));
}")
-;; ??? This should be a define expand.
-
;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
;; compiled with -m2 -ml -O3 -funroll-loops
-(define_insn ""
+(define_insn "*movdi_i"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
(match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
"TARGET_SH1
(define_insn "*movdi_media"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,f,m,f,r,f,*b,r,b")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,m,f,rU,f,f,r,*b,T"))]
+ (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,m,f,rU,f,f,r,*b,T"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
+ || sh_register_operand (operands[1], DImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1
+ st%M0.q %m0, %N1
fld%M1.d %m1, %0
fst%M0.d %m0, %1
fmov.qd %N1, %0
(define_insn "*movdi_media_nofpu"
[(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,rl,m,*b,r,b")
- (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rl,r,*b,T"))]
+ (match_operand:DI 1 "general_movsrc_operand" "r,JS,iF,m,rlU,r,*b,T"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DImode)
- || register_operand (operands[1], DImode))"
+ || sh_register_operand (operands[1], DImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1
+ st%M0.q %m0, %N1
ptabs %1, %0
gettr %1, %0
pt %1, %0"
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
"
{
- if (GET_CODE (operands[1]) == LABEL_REF
- && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
- LABEL_NUSES (XEXP (operands[1], 0)) += 4;
- else if (GOTOFF_P (operands[1])
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
- && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
- == CODE_LABEL))
- LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 4;
+ sh_mark_label (operands[1], 4);
}")
(define_expand "movdi_const_32bit"
&& MOVI_SHORI_BASE_OPERAND_P (operands[1])"
"
{
- if (GET_CODE (operands[1]) == LABEL_REF
- && GET_CODE (XEXP (operands[1], 0)) == CODE_LABEL)
- LABEL_NUSES (XEXP (operands[1], 0)) += 2;
- else if (GOTOFF_P (operands[1])
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == LABEL_REF
- && (GET_CODE (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0))
- == CODE_LABEL))
- LABEL_NUSES (XEXP (XVECEXP (XEXP (operands[1], 0), 0, 0), 0)) += 2;
+ sh_mark_label (operands[1], 2);
}")
(define_expand "movdi_const_16bit"
(define_insn "movdf_media"
[(set (match_operand:DF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,r"))]
+ (match_operand:DF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
+ || sh_register_operand (operands[1], DFmode))"
"@
fmov.d %1, %0
fmov.qd %N1, %0
fld%M1.d %m1, %0
fst%M0.d %m0, %1
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
+ st%M0.q %m0, %N1"
[(set_attr "type" "fmove_media,fload_media,dfpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
(define_insn "movdf_media_nofpu"
[(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:DF 1 "general_movsrc_operand" "r,F,m,r"))]
+ (match_operand:DF 1 "general_movsrc_operand" "r,F,m,rU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
+ || sh_register_operand (operands[1], DFmode))"
"@
add %1, r63, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
+ st%M0.q %m0, %N1"
[(set_attr "type" "arith_media,*,load_media,store_media")])
(define_split
(match_operand:SF 1 "register_operand" ""))
(use (match_operand:PSI 2 "fpscr_operand" ""))
(clobber (match_scratch:SI 3 "X"))]
- "TARGET_SH3E && reload_completed
+ "TARGET_SH2E && reload_completed
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 0) (match_dup 0))]
"")
(define_insn_and_split "*movv4sf_i"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=f,f,m")
- (match_operand:V4SF 1 "general_operand" "fU,m,f"))]
+ (match_operand:V4SF 1 "general_operand" "fU,m,fU"))]
"TARGET_SHMEDIA_FPU"
"#"
"&& reload_completed"
(define_insn "movsf_media"
[(set (match_operand:SF 0 "general_movdst_operand" "=f,f,r,r,r,f,m,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,r"))]
+ (match_operand:SF 1 "general_movsrc_operand" "f,rU,f,r,F,m,f,m,rU"))]
"TARGET_SHMEDIA_FPU
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
+ || sh_register_operand (operands[1], SFmode))"
"@
fmov.s %1, %0
fmov.ls %N1, %0
fld%M1.s %m1, %0
fst%M0.s %m0, %1
ld%M1.l %m1, %0
- st%M0.l %m0, %1"
+ st%M0.l %m0, %N1"
[(set_attr "type" "fmove_media,fload_media,fpconv_media,arith_media,*,fload_media,fstore_media,load_media,store_media")])
(define_insn "movsf_media_nofpu"
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,m")
- (match_operand:SF 1 "general_movsrc_operand" "r,F,m,r"))]
+ (match_operand:SF 1 "general_movsrc_operand" "r,F,m,rU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode))"
+ || sh_register_operand (operands[1], SFmode))"
"@
add.l %1, r63, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1"
+ st%M0.l %m0, %N1"
[(set_attr "type" "arith_media,*,load_media,store_media")])
(define_split
[(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
(match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
"TARGET_SH1
- && (! TARGET_SH3E
+ && (! TARGET_SH2E
/* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
|| (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3)
|| (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3))
(use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
(clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))]
- "TARGET_SH3E
+ "TARGET_SH2E
&& (arith_reg_operand (operands[0], SFmode)
|| arith_reg_operand (operands[1], SFmode)
|| arith_reg_operand (operands[3], SImode)
emit_insn (gen_movsf_media_nofpu (operands[0], operands[1]));
DONE;
}
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
DONE;
(define_insn "mov_nop"
[(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
""
[(set_attr "length" "0")
(set_attr "type" "nil")])
[(set (match_operand:SI 0 "register_operand" "=y,y")
(match_operand:SI 1 "immediate_operand" "Qi,I"))
(clobber (match_scratch:SI 2 "=&z,r"))]
- "TARGET_SH3E
+ "TARGET_SH2E
&& (reload_in_progress || reload_completed)"
"#"
[(set_attr "length" "4")
;; This one has the additional purpose to record a possible scratch register
;; for the following branch.
+;; ??? Unfortunately, just setting the scratch register is not good enough,
+;; because the insn then might be deemed dead and deleted. And we can't
+;; make the use in the jump insn explicit because that would disable
+;; delay slot scheduling from the target.
(define_insn "indirect_jump_scratch"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))]
+ (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
+ (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
"TARGET_SH1"
""
[(set_attr "length" "0")])
DONE;
}
- if (TARGET_SH3E
+ if (TARGET_SH2E
&& TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
DONE;
}
- if (TARGET_SH3E
+ if (TARGET_SH2E
&& ! TARGET_IEEE
&& GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
{
[(set_attr "type" "jump")
(set_attr "needs_delay_slot" "yes")])
+;; ??? It would be much saner to explicitly use the scratch register
+;; in the jump insn, and have indirect_jump_scratch only set it,
+;; but fill_simple_delay_slots would refuse to do delay slot filling
+;; from the target then, as it uses simplejump_p.
+;;(define_insn "jump_compact_far"
+;; [(set (pc)
+;; (label_ref (match_operand 0 "" "")))
+;; (use (match_operand 1 "register_operand" "r")]
+;; "TARGET_SH1"
+;; "* return output_far_jump(insn, operands[0], operands[1]);"
+;; [(set_attr "type" "jump")
+;; (set_attr "needs_delay_slot" "yes")])
+
(define_insn "jump_media"
[(set (pc)
(match_operand:DI 0 "target_operand" "b"))]
(const_int 0))
(match_operand 1 "" "")
(match_operand 2 "" "")])]
- "TARGET_SH3E || TARGET_SHMEDIA"
+ "TARGET_SH2E || TARGET_SHMEDIA"
"
{
int i;
""
"")
+;; TLS code generation.
+;; ??? this should be a define_insn_and_split
+;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
+;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
+;; for details.
+
+(define_insn "tls_global_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSGD))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSGD\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_insn "tls_local_dynamic"
+ [(set (match_operand:SI 0 "register_operand" "=&z")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSLDM))
+ (use (reg:PSI FPSCR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (scratch:SI))]
+ "TARGET_SH1"
+ "*
+{
+ return \"\\
+mov.l\\t1f,r4\\n\\
+\\tmova\\t2f,r0\\n\\
+\\tmov.l\\t2f,r1\\n\\
+\\tadd\\tr0,r1\\n\\
+\\tjsr\\t@r1\\n\\
+\\tadd\\tr12,r4\\n\\
+\\tbra\\t3f\\n\\
+\\tnop\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1@TLSLDM\\n\\
+2:\\t.long\\t__tls_get_addr@PLT\\n\\
+3:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "26")])
+
+(define_expand "sym2DTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
+ ""
+ "")
+
+(define_expand "symDTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
+ ""
+ "
+{
+ rtx dtpoffsym, insn;
+ rtx t = no_new_pseudos ? operands[0] : gen_reg_rtx (GET_MODE (operands[0]));
+
+ dtpoffsym = gen_sym2DTPOFF (operands[1]);
+ PUT_MODE (dtpoffsym, Pmode);
+ emit_move_insn (t, dtpoffsym);
+ insn = emit_move_insn (operands[0],
+ gen_rtx_PLUS (Pmode, t, operands[2]));
+ DONE;
+}")
+
+(define_expand "sym2GOTTPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
+ ""
+ "")
+
+(define_insn "tls_initial_exec"
+ [(set (match_operand:SI 0 "register_operand" "=&r")
+ (unspec:SI [(match_operand:SI 1 "" "")]
+ UNSPEC_TLSIE))
+ (use (reg:SI GBR_REG))
+ (use (reg:SI PIC_REG))
+ (clobber (reg:SI R0_REG))]
+ ""
+ "*
+{
+ return \"\\
+mov.l\\t1f,r0\\n\\
+\\tstc\\tgbr,%0\\n\\
+\\tmov.l\\t@(r0,r12),r0\\n\\
+\\tbra\\t2f\\n\\
+\\tadd\\tr0,%0\\n\\
+\\t.align\\t2\\n\\
+1:\\t.long\\t%a1\\n\\
+2:\";
+}"
+ [(set_attr "type" "tls_load")
+ (set_attr "length" "16")])
+
+(define_expand "sym2TPOFF"
+ [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
+ ""
+ "")
+
+(define_expand "symTPOFF2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "")]
+ ""
+ "
+{
+ rtx tpoffsym, insn;
+
+ tpoffsym = gen_sym2TPOFF (operands[1]);
+ PUT_MODE (tpoffsym, Pmode);
+ insn = emit_move_insn (operands[0], tpoffsym);
+ DONE;
+}")
+
+(define_insn "load_gbr"
+ [(set (match_operand:SI 0 "register_operand" "") (reg:SI GBR_REG))
+ (use (reg:SI GBR_REG))]
+ ""
+ "stc gbr,%0"
+ [(set_attr "type" "tls_load")])
+
;; case instruction for switch statements.
;; Operand 0 is index
DONE;
}")
+(define_expand "eh_return"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand 1 "register_operand" ""))]
+ ""
+{
+ rtx tmp, sa = operands[0], ra = operands[1];
+
+ if (TARGET_SHMEDIA64)
+ emit_insn (gen_eh_set_ra_di (ra));
+ else
+ emit_insn (gen_eh_set_ra_si (ra));
+
+ emit_move_insn (EH_RETURN_STACKADJ_RTX, sa);
+ DONE;
+})
+
+;; Clobber the return address on the stack. We can't expand this
+;; until we know where it will be put in the stack frame.
+
+(define_insn "eh_set_ra_si"
+ [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:SI 1 "=&r"))]
+ "! TARGET_SHMEDIA64"
+ "#")
+
+(define_insn "eh_set_ra_di"
+ [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch:DI 1 "=&r"))]
+ "TARGET_SHMEDIA64"
+ "#")
+
+(define_split
+ [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch 1 ""))]
+ "reload_completed"
+ [(const_int 0)]
+ "
+{
+ sh_set_return_address (operands[0], operands[1]);
+ DONE;
+}")
+
(define_insn "blockage"
[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
;; The mac_gp type for r/!c might look a bit odd, but it actually schedules
;; like a mac -> gpr move.
(define_insn "fpu_switch"
- [(set (match_operand:PSI 0 "register_operand" "=c,c,r,c,c,r,m,r")
- (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
- "TARGET_SH4
+ [(set (match_operand:PSI 0 "general_movdst_operand" "=c,c,r,c,c,r,m,r,<")
+ (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c,c"))]
+ "TARGET_SH3E
&& (! reload_completed
|| true_regnum (operands[0]) != FPSCR_REG
|| GET_CODE (operands[1]) != MEM
lds %1,fpscr
mov %1,%0
mov.l %1,%0
- sts fpscr,%0"
- [(set_attr "length" "0,2,2,4,2,2,2,2")
- (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp")])
+ sts fpscr,%0
+ sts.l fpscr,%0"
+ [(set_attr "length" "0,2,2,4,2,2,2,2,2")
+ (set_attr "type" "nil,mem_fpscr,load,mem_fpscr,gp_fpscr,move,store,mac_gp,store")])
(define_split
[(set (reg:PSI FPSCR_REG)
[(set (match_operand:SF 0 "arith_reg_operand" "")
(plus:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_addsf3_i, operands);
DONE;
(vec_concat:V2SF
(vec_select:SF
(match_dup 0)
- (parallel [(not:BI (match_operand 4 "const_int_operand" "n"))]))
+ (parallel [(match_operand 7 "const_int_operand" "n")]))
(match_operator:SF 3 "binary_float_operator"
[(vec_select:SF (match_operand:V2SF 1 "fp_arith_reg_operand" "f")
(parallel [(match_operand 5
(vec_select:SF (match_operand:V2SF 2 "fp_arith_reg_operand" "f")
(parallel [(match_operand 6
"const_int_operand" "n")]))]))
- (parallel [(not:BI (match_dup 4)) (match_dup 4)])))]
- "TARGET_SHMEDIA_FPU"
+ (parallel [(match_dup 7) (match_operand 4 "const_int_operand" "n")])))]
+ "TARGET_SHMEDIA_FPU && INTVAL (operands[4]) != INTVAL (operands[7])"
"#"
- "TARGET_SHMEDIA_FPU && reload_completed"
- [(set (match_dup 7) (match_dup 8))]
+ "&& reload_completed"
+ [(set (match_dup 8) (match_dup 9))]
"
{
int endian = TARGET_LITTLE_ENDIAN ? 0 : 1;
(true_regnum (operands[2])
+ (INTVAL (operands[6]) ^ endian)));
- operands[7] = gen_rtx_REG (SFmode,
+ operands[8] = gen_rtx_REG (SFmode,
(true_regnum (operands[0])
+ (INTVAL (operands[4]) ^ endian)));
- operands[8] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
+ operands[9] = gen_rtx (GET_CODE (operands[3]), SFmode, op1, op2);
}"
[(set_attr "type" "fparith_media")])
(plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fadd %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_subsf3_i, operands);
DONE;
(minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fsub %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
(match_operand:SF 2 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
expand_sf_binop (&gen_mulsf3_i4, operands);
- else if (TARGET_SH3E)
+ else if (TARGET_SH2E)
emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
if (! TARGET_SHMEDIA)
DONE;
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fmul %2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
(match_operand:SF 2 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fmul %2,%0"
[(set_attr "type" "fp")])
(match_operand:SF 2 "fp_arith_reg_operand" "f"))
(match_operand:SF 3 "arith_reg_operand" "0")))
(use (match_operand:PSI 4 "fpscr_operand" "c"))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fmac fr0,%2,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (match_operand:SF 0 "arith_reg_operand" "")
(div:SF (match_operand:SF 1 "arith_reg_operand" "")
(match_operand:SF 2 "arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_binop (&gen_divsf3_i, operands);
DONE;
(div:SF (match_operand:SF 1 "arith_reg_operand" "0")
(match_operand:SF 2 "arith_reg_operand" "f")))
(use (match_operand:PSI 3 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fdiv %2,%0"
[(set_attr "type" "fdiv")
(set_attr "fp_mode" "single")])
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(float:SF (match_operand:SI 1 "fpul_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
(define_insn "*floatsisf2_ie"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(float:SF (match_operand:SI 1 "fpul_operand" "y")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"float %1,%0"
[(set_attr "type" "fp")])
(define_expand "fix_truncsfsi2"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
if (TARGET_SH4)
(define_insn "*fixsfsi"
[(set (match_operand:SI 0 "fpul_operand" "=y")
(fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"ftrc %1,%0"
[(set_attr "type" "fp")])
[(set (reg:SI T_REG)
(gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fcmp/gt %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
[(set (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f")))]
- "TARGET_SH3E && ! TARGET_SH4"
+ "TARGET_SH2E && ! TARGET_SH4"
"fcmp/eq %1,%0"
[(set_attr "type" "fp")
(set_attr "fp_mode" "single")])
(ior:SI (reg:SI T_REG)
(eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
(match_operand:SF 1 "fp_arith_reg_operand" "f"))))]
- "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
+ "TARGET_SH2E && TARGET_IEEE && ! TARGET_SH4"
"* return output_ieee_ccmpeq (insn, operands);"
[(set_attr "length" "4")])
[(set (reg:SI T_REG)
(compare (match_operand:SF 0 "arith_operand" "")
(match_operand:SF 1 "arith_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
sh_compare_op0 = operands[0];
(define_expand "negsf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_unop (&gen_negsf2_i, operands);
DONE;
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fneg %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
(define_expand "abssf2"
[(set (match_operand:SF 0 "fp_arith_reg_operand" "")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
- "TARGET_SH3E || TARGET_SHMEDIA_FPU"
+ "TARGET_SH2E || TARGET_SHMEDIA_FPU"
"
{
- if (TARGET_SH3E)
+ if (TARGET_SH2E)
{
expand_sf_unop (&gen_abssf2_i, operands);
DONE;
[(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
(abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
(use (match_operand:PSI 2 "fpscr_operand" "c"))]
- "TARGET_SH3E"
+ "TARGET_SH2E"
"fabs %0"
[(set_attr "type" "fmove")
(set_attr "fp_mode" "single")])
(plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
(set (mem:SF (match_dup 0))
(match_operand:SF 2 "general_movsrc_operand" ""))]
- "TARGET_SH3E && REGNO (operands[0]) == 0
+ "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
(set (match_operand:SF 2 "general_movdst_operand" "")
(mem:SF (match_dup 0)))]
- "TARGET_SH3E && REGNO (operands[0]) == 0
+ "TARGET_SH2E && REGNO (operands[0]) == 0
&& ((GET_CODE (operands[2]) == REG
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
|| (GET_CODE (operands[2]) == SUBREG
(define_insn "movv8qi_i"
[(set (match_operand:V8QI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V8QI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
+ (match_operand:V8QI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V8QImode)
- || register_operand (operands[1], V8QImode))"
+ || sh_register_operand (operands[1], V8QImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
+ st%M0.q %m0, %N1"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
(set_attr "length" "4,4,16,4,4")])
&& VECTOR_MODE_SUPPORTED_P (GET_MODE (operands[0]))
&& GET_MODE_SIZE (GET_MODE (operands[0])) == 8
&& (XVECEXP (operands[1], 0, 0) != const0_rtx
- || XVECEXP (operands[1], 0, 1) != const0_rtx)"
+ || XVECEXP (operands[1], 0, 1) != const0_rtx)
+ && (XVECEXP (operands[1], 0, 0) != constm1_rtx
+ || XVECEXP (operands[1], 0, 1) != constm1_rtx)"
[(set (match_dup 0) (match_dup 1))
(match_dup 2)]
"
(define_insn "movv2hi_i"
[(set (match_operand:V2HI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V2HI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
+ (match_operand:V2HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V2HImode)
- || register_operand (operands[1], V2HImode))"
+ || sh_register_operand (operands[1], V2HImode))"
"@
addz.l %1, r63, %0
movi %1, %0
#
ld%M1.l %m1, %0
- st%M0.l %m0, %1"
+ st%M0.l %m0, %N1"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
(set_attr "length" "4,4,16,4,4")])
(define_insn "movv4hi_i"
[(set (match_operand:V4HI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V4HI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
+ (match_operand:V4HI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V4HImode)
- || register_operand (operands[1], V4HImode))"
+ || sh_register_operand (operands[1], V4HImode))"
"@
add %1, r63, %0
movi %1, %0
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
+ st%M0.q %m0, %N1"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
(set_attr "length" "4,4,16,4,4")])
(define_insn "movv2si_i"
[(set (match_operand:V2SI 0 "general_movdst_operand" "=r,r,r,rl,m")
- (match_operand:V2SI 1 "general_movsrc_operand" "r,JSU,nW,m,rl"))]
+ (match_operand:V2SI 1 "general_movsrc_operand" "r,JSU,nW,m,rlU"))]
"TARGET_SHMEDIA
&& (register_operand (operands[0], V2SImode)
- || register_operand (operands[1], V2SImode))"
+ || sh_register_operand (operands[1], V2SImode))"
"@
add %1, r63, %0
#
#
ld%M1.q %m1, %0
- st%M0.q %m0, %1"
+ st%M0.q %m0, %N1"
[(set_attr "type" "arith_media,arith_media,*,load_media,store_media")
(set_attr "length" "4,4,16,4,4")])
(vec_select:V4HI
(vec_concat:V4HI (match_operand:V2HI 1 "extend_reg_or_0_operand" "rU")
(match_operand:V2HI 2 "extend_reg_or_0_operand" "rU"))
- (parallel [(const_int 0) (const_int 2) (const_int 1) (const_int 3)])))]
+ (parallel [(const_int 2) (const_int 0) (const_int 3) (const_int 1)])))]
"TARGET_SHMEDIA"
"mshflo.w %N1, %N2, %0"
[(set_attr "type" "arith_media")])
"issue+load_store")
;; We don't model all pipeline stages; we model the issue ('D') stage
-;; inasmuch as we allow only two instructions to issue simultanously,
-;; and CO instructions prevent any simultanous issue of another instruction.
+;; inasmuch as we allow only two instructions to issue simultaneously,
+;; and CO instructions prevent any simultaneous issue of another instruction.
;; (This uses pipe_01 and pipe_02).
;; Double issue of EX insns is prevented by using the int unit in the EX stage.
;; Double issue of EX / BR insns is prevented by using the int unit /
;; (except in the cases outlined above), nor to describe the FS stage after
;; the F2 stage.
-;; Other MT group intructions(1 step operations)
+;; Other MT group instructions(1 step operations)
;; Group: MT
;; Latency: 1
;; Issue Rate: 1
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