#define TARGET_DEFAULT (0)
+#define PRESERVE_DEATH_INFO_REGNO_P(regno) (TARGET_RELAX || optimize)
+
#define OVERRIDE_OPTIONS \
do { \
sh_cpu = CPU_SH0; \
/* Allocation boundary (in *bits*) for the code of a function.
32 bit alignment is faster, because instructions are always fetched as a
pair from a longword boundary. */
-/* ??? Perhaps also define ASM_OUTPUT_ALIGN_CODE and/or ASM_OUTPUT_LOOP_ALIGN
- so as to align jump targets and/or loops to 4 byte boundaries when not
- optimizing for space? */
#define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
/* Alignment of field after `int : 0' in a structure. */
mach multiply/accumulate result, high part
macl multiply/accumulate result, low part.
fpul fp/int communication register
+ rap return address pointer register
fr0 fp arg return
fr1..fr3 scratch floating point registers
fr4..fr11 fp args in
#define MACL_REG 21
#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
#define FPUL_REG 22
-/* Number 23 is unused. Reserved for future expansion. */
+#define RAP_REG 23
#define FIRST_FP_REG 24
#define LAST_FP_REG 39
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 14
+/* Fake register that holds the address on the stack of the
+ current function's return address. */
+#define RETURN_ADDRESS_POINTER_REGNUM 23
+
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may be accessed
via the stack pointer) in functions that seem suitable. */
followed by "to". Eliminations of the same "from" register are listed
in order of preference. */
-#define ELIMINABLE_REGS \
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
+#define ELIMINABLE_REGS \
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
/* Given FROM and TO register numbers, say whether this elimination
is allowed. */
FPUL_REGS,
FP0_REGS,
FP_REGS,
+ GENERAL_FP_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
"FPUL_REGS", \
"FP0_REGS", \
"FP_REGS", \
+ "GENERAL_FP_REGS", \
"ALL_REGS", \
}
{ 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
{ 0x01000000, 0x00000000 }, /* FP0_REGS */ \
{ 0xFF000000, 0x000000FF }, /* FP_REGS */ \
+ { 0xFF01FFFF, 0x000000FF }, /* GENERAL_FP_REGS */ \
{ 0xFF7FFFFF, 0x000000FF }, /* ALL_REGS */ \
}
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? fp_zero_operand (VALUE) \
: (C) == 'H' ? fp_one_operand (VALUE) \
- : 0)
+ : (C) == 'F')
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
+/* ??? Should make FPUL register a nn-fixed register and make it's
+ use explicit in the rtl; then change this definition here to
+ ... ? FPUL_REGS : NO_REGS) . */
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
+ ((((CLASS == FP_REGS || CLASS == FP0_REGS) \
+ && GET_CODE (X) == REG && REGNO (X) <= AP_REG) \
+ || (CLASS == GENERAL_REGS && GET_CODE (X) == REG \
+ && REGNO (X) <= FIRST_FP_REG && REGNO (X) >= LAST_FP_REG)) \
+ ? /* FPUL_REGS */ NO_REGS : NO_REGS)
+
+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
+ (((CLASS == FP_REGS || CLASS == FP0_REGS) && immediate_operand (X, MODE)\
+ && ! (fp_one_operand (X) || fp_one_operand (X))) \
+ ? R0_REGS : SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X))
+
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
On SH, the offset always starts at 0: the first parm reg is always
the same reg. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
do { \
(CUM).arg_count[(int) SH_ARG_INT] = 0; \
(CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
(ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
&& ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
- && (TARGET_SH3E && (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) < NPARM_REGS (MODE))))
+ && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE))))
/* Define where to put the arguments to a function.
Value is zero to push the argument on the stack,
fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
}
+/* Define this macro if the code for function profiling should come
+ before the function prologue. Normally, the profiling code comes
+ after. */
+
+#define PROFILE_BEFORE_PROLOGUE
+
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
(FNADDR)); \
}
+
+/* A C expression whose value is RTL representing the value of the return
+ address for the frame COUNT steps up from the current frame.
+ FRAMEADDR is already the frame pointer of the COUNT frame, so we
+ can ignore COUNT. */
+
+#define RETURN_ADDR_RTX(COUNT, FRAME) \
+ ((COUNT == 0) \
+ ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
+ : (rtx) 0)
\f
/* Generate necessary RTL for __builtin_saveregs().
ARGLIST is the argument list; see expr.c. */
/* Nonzero if the constant value X is a legitimate general operand. */
-/* ??? Should modify this to accept CONST_DOUBLE, and then modify the
- constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
- work well, then we can at least handle simple CONST_DOUBLEs here
- such as 0.0. */
-
#define LEGITIMATE_CONSTANT_P(X) \
(GET_CODE (X) != CONST_DOUBLE \
+ || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
|| (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
GO_IF_LEGITIMATE_ADDRESS.
It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
+ opportunities to optimize the output.
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
+ For the SH, if X is almost suitable for indexing, but the offset is
+ out of range, convert it into a normal form so that cse has a chance
+ of reducing the number of address registers used. */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
+{ \
+ if (GET_CODE (X) == PLUS \
+ && (GET_MODE_SIZE (MODE) == 4 \
+ || GET_MODE_SIZE (MODE) == 8) \
+ && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
+ && ! (TARGET_SH3E && MODE == SFmode)) \
+ { \
+ rtx index_rtx = XEXP (X, 1); \
+ HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
+ rtx sum; \
+ \
+ GO_IF_LEGITIMATE_INDEX (MODE, index_rtx, WIN); \
+ /* On rare occasions, we might get an unaligned pointer \
+ that is indexed in a way to give an aligned address. \
+ Therefore, keep the lower two bits in offset_base. */ \
+ /* Instead of offset_base 128..131 use 124..127, so that \
+ simple add suffices. */ \
+ if (offset > 127) \
+ { \
+ offset_base = ((offset + 4) & ~60) - 4; \
+ } \
+ else \
+ offset_base = offset & ~60; \
+ /* Sometimes the normal form does not suit DImode. We \
+ could avoid that by using smaller ranges, but that \
+ would give less optimized code when SImode is \
+ prevalent. */ \
+ if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
+ { \
+ sum = expand_binop (Pmode, add_optab, XEXP (X, 0), \
+ GEN_INT (offset_base), NULL_RTX, 0, \
+ OPTAB_LIB_WIDEN); \
+ \
+ (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \
+ goto WIN; \
+ } \
+ } \
+}
/* Go to LABEL if ADDR (a legitimate address expression)
has an effect that depends on the machine mode it is used for. */
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
+/* Define if loading short immediate values into registers sign extends. */
+#define SHORT_IMMEDIATES_SIGN_EXTEND
+
/* Define this if zero-extension is slow (more than one real instruction).
On the SH, it's only one instruction. */
/* #define SLOW_ZERO_EXTEND */
\f
/* Assembler output control. */
+/* A C string constant describing how to begin a comment in the target
+ assembler language. The compiler assumes that the comment will end at
+ the end of the line. */
+#define ASM_COMMENT_START "!"
+
/* The text to go at the start of the assembler file. */
-#define ASM_FILE_START(STREAM) \
- output_file_start (STREAM, f_options, \
- sizeof f_options / sizeof f_options[0], \
- W_options, sizeof W_options / sizeof W_options[0]);
+#define ASM_FILE_START(STREAM) \
+ output_file_start (STREAM)
#define ASM_FILE_END(STREAM)
#define ASM_APP_OFF ""
#define FILE_ASM_OP "\t.file\n"
#define IDENT_ASM_OP "\t.ident\n"
+#define SET_ASM_OP ".set"
/* How to change between sections. */
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
- "ap", "pr", "t", "gbr", "mach","macl", "fpul", "X", \
+ "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \
"fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
"fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
}
assemble_name (STREAM, NAME), \
fputc ('\n',STREAM))
-/* Output a reference to a label. */
-#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
- fprintf (STREAM, "_%s", NAME)
+/* The prefix to add to user-visible assembler symbols. */
+
+#define USER_LABEL_PREFIX "_"
/* Make an internal label into a string. */
#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
+/* Align loops and labels after unconditional branches to get faster
+ code. */
+
+#define ASM_OUTPUT_LOOP_ALIGN(FILE) \
+ if (! TARGET_SMALLCODE) \
+ ASM_OUTPUT_ALIGN ((FILE), 2)
+
+#define ASM_OUTPUT_ALIGN_CODE(FILE) \
+ if (! TARGET_SMALLCODE) \
+ ASM_OUTPUT_ALIGN ((FILE), (TARGET_SH3 || TARGET_SH3E) ? 4 : 2)
+
/* This is how to output an assembler line
that says to advance the location counter by SIZE bytes. */
text can be read. CH is the first character after the #pragma. The
result of the expression is the terminating character found
(newline or EOF). */
-#define HANDLE_PRAGMA(FILE, CH) handle_pragma (FILE, CH)
+#define HANDLE_PRAGMA(FILE, NODE) handle_pragma (FILE, NODE)
/* Set when processing a function with pragma interrupt turned on. */
#define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
\f
/* Instructions with unfilled delay slots take up an extra two bytes for
- the nop in the delay slot. */
+ the nop in the delay slot. Instructions at the start of loops, or
+ after unconditional branches, may take up extra room when they are
+ aligned. ??? We would get more accurate results if we did instruction
+ alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
+ here is too conservative. */
#define ADJUST_INSN_LENGTH(X, LENGTH) \
if (((GET_CODE (X) == INSN \
&& GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
&& GET_CODE (PATTERN (X)) != ADDR_VEC)) \
&& get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
- LENGTH += 2;
+ LENGTH += 2; \
+ if (! TARGET_SMALLCODE) \
+ { \
+ rtx aip; \
+ for (aip = PREV_INSN (X); aip; aip = PREV_INSN (aip)) \
+ { \
+ if (GET_CODE (aip) == BARRIER) \
+ { \
+ if (TARGET_SH3 || TARGET_SH3E) \
+ LENGTH += 14; \
+ else \
+ LENGTH += 2; \
+ break; \
+ } \
+ else if ((GET_CODE (aip) == NOTE \
+ && NOTE_LINE_NUMBER (aip) == NOTE_INSN_LOOP_BEG)) \
+ { \
+ LENGTH += 2; \
+ break; \
+ } \
+ else if (GET_CODE (aip) != NOTE \
+ && GET_CODE (aip) != CODE_LABEL) \
+ break; \
+ } \
+ }
/* Enable a bug fix for the shorten_branches pass. */
#define SHORTEN_WITH_ADJUST_INSN_LENGTH
/* ??? Define ADJUST_COSTS? */
+/* Since the SH architecture lacks negative address offsets,
+ the givs should be sorted smallest to largest so combine_givs
+ has maximum opportunity to combine givs. */
+#define GIV_SORT_CRITERION(X, Y) \
+ if (GET_CODE ((X)->add_val) == CONST_INT \
+ && GET_CODE ((Y)->add_val) == CONST_INT) \
+ return INTVAL ((X)->add_val) - INTVAL ((Y)->add_val);
+
/* For the sake of libgcc2.c, indicate target supports atexit. */
#define HAVE_ATEXIT
OSDN Git Service
