/* Definitions of target machine for GNU compiler for Hitachi Super-H.
- Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
- Contributed by Steve Chamberlain (sac@cygnus.com)
+ Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
+ Contributed by Steve Chamberlain (sac@cygnus.com).
+ Improved by Jim Wilson (wilson@cygnus.com).
This file is part of GNU CC.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
-/* Run-time Target Specification. */
-#define TARGET_SH
-
-#define TARGET_VERSION \
+#define TARGET_VERSION \
fputs (" (Hitachi SH)", stderr);
/* Generate SDB debugging information. */
-#define SDB_DEBUGGING_INFO 1
+#define SDB_DEBUGGING_INFO
/* Output DBX (stabs) debugging information if doing -gstabs. */
-#define DBX_DEBUGGING_INFO
-
-/* Generate SDB debugging information by default. */
-
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
+#include "dbxcoff.h"
#define SDB_DELIM ";"
-#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
+#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__} \
+%{m1:-D__sh1__} \
+%{m2:-D__sh2__} \
+%{m3:-D__sh3__} \
+%{m3e:-D__SH3E__}"
#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
-#define ASM_SPEC "%{ml:-little}"
-
-#define LINK_SPEC "%{ml:-m shl}"
+#define ASM_SPEC "%{ml:-little} %{mrelax:-relax}"
-/* Show we can debug even without a frame pointer. */
-#define CAN_DEBUG_WITHOUT_FP
+#define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
+/* We can not debug without a frame pointer. */
+/* #define CAN_DEBUG_WITHOUT_FP */
#define CONDITIONAL_REGISTER_USAGE \
+ if (! TARGET_SH3E) \
+ { \
+ int regno; \
+ for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
+ fixed_regs[regno] = call_used_regs[regno] = 1; \
+ } \
/* Hitachi saves and restores mac registers on call. */ \
if (TARGET_HITACHI) \
- { \
- call_used_regs[MACH_REG] = 0; \
- call_used_regs[MACL_REG] = 0; \
- }
+ { \
+ call_used_regs[MACH_REG] = 0; \
+ call_used_regs[MACL_REG] = 0; \
+ }
\f
+/* ??? Need to write documentation for all SH options and add it to the
+ invoke.texi file. */
+
/* Run-time compilation parameters selecting different hardware subsets. */
extern int target_flags;
#define ISIZE_BIT (1<<1)
-#define FAST_BIT (1<<2)
-#define RTL_BIT (1<<4)
-#define DT_BIT (1<<5)
#define DALIGN_BIT (1<<6)
#define SH0_BIT (1<<7)
#define SH1_BIT (1<<8)
#define SH2_BIT (1<<9)
#define SH3_BIT (1<<10)
-#define C_BIT (1<<11)
-#define R_BIT (1<<12)
+#define SH3E_BIT (1<<11)
#define SPACE_BIT (1<<13)
#define BIGTABLE_BIT (1<<14)
-#define CONSTLEN_2_BIT (1<<20)
-#define CONSTLEN_3_BIT (1<<21)
+#define RELAX_BIT (1<<15)
#define HITACHI_BIT (1<<22)
-#define CONSTLEN_0_BIT (1<<25)
-#define PACKSTRUCT_BIT (1<<28)
+#define PADSTRUCT_BIT (1<<28)
#define LITTLE_ENDIAN_BIT (1<<29)
+/* Nonzero if we should dump out instruction size info. */
+#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
+
+/* Nonzero to align doubles on 64 bit boundaries. */
+#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
+
/* Nonzero if we should generate code using type 0 insns. */
+/* ??? Is there such a thing as SH0? If not, we should delete all
+ references to it. */
#define TARGET_SH0 (target_flags & SH0_BIT)
/* Nonzero if we should generate code using type 1 insns. */
/* Nonzero if we should generate code using type 3 insns. */
#define TARGET_SH3 (target_flags & SH3_BIT)
-/* Nonzero if we should generate faster code rather than smaller code. */
-#define TARGET_FASTCODE (target_flags & FAST_BIT)
+/* Nonzero if we should generate code using type 3E insns. */
+#define TARGET_SH3E (target_flags & SH3E_BIT)
/* Nonzero if we should generate smaller code rather than faster code. */
#define TARGET_SMALLCODE (target_flags & SPACE_BIT)
-/* Nonzero if we should dump out instruction size info. */
-#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
-
-/* Nonzero if we should dump the rtl in the assembly file. */
-#define TARGET_DUMP_RTL (target_flags & RTL_BIT)
-
-/* Nonzero if we should dump the rtl somewher else. */
-#define TARGET_DUMP_R (target_flags & R_BIT)
-
-/* Nonzero to align doubles on 64 bit boundaries. */
-#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
-
/* Nonzero to use long jump tables. */
#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
-/* Nonzero if combine dumping wanted. */
-#define TARGET_CDUMP (target_flags & C_BIT)
-
-/* Select max size of computed constant code sequences to be 3 insns. */
-#define TARGET_CLEN3 (target_flags & CONSTLEN_3_BIT)
-
-/* Select max size of computed constant code sequences to be 0 insns -
- i.e. don't do it. */
-#define TARGET_CLEN0 (target_flags & CONSTLEN_0_BIT)
+/* Nonzero to generate pseudo-ops needed by the assembler and linker
+ to do function call relaxing. */
+#define TARGET_RELAX (target_flags & RELAX_BIT)
/* Nonzero if using Hitachi's calling convention. */
#define TARGET_HITACHI (target_flags & HITACHI_BIT)
-/* Nonzero if packing structures as small as they'll go (incompatible
- with Hitachi's compiler). */
-#define TARGET_PACKSTRUCT (target_flags & PACKSTRUCT_BIT)
-
+/* Nonzero if padding structures to a multiple of 4 bytes. This is
+ incompatible with Hitachi's compiler, and gives unusual structure layouts
+ which confuse programmers.
+ ??? This option is not useful, but is retained in case there are people
+ who are still relying on it. It may be deleted in the future. */
+#define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
+/* Nonzero if generating code for a little endian SH. */
#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
#define TARGET_SWITCHES \
-{ {"0", (SH0_BIT) }, \
- {"1", (SH1_BIT) }, \
- {"2", (SH2_BIT) }, \
- {"3", (SH3_BIT) }, \
- {"3l", (SH3_BIT|LITTLE_ENDIAN_BIT)}, \
- {"R", (R_BIT) }, \
- {"b", (-LITTLE_ENDIAN_BIT) }, \
- {"bigtable", (BIGTABLE_BIT)}, \
- {"c", (C_BIT) }, \
- {"clen0", (CONSTLEN_0_BIT) }, \
- {"clen3", (CONSTLEN_3_BIT) }, \
- {"dalign", (DALIGN_BIT) }, \
- {"hitachi", (HITACHI_BIT) }, \
- {"isize", (ISIZE_BIT) }, \
- {"l", (LITTLE_ENDIAN_BIT) }, \
- {"packstruct",(PACKSTRUCT_BIT) }, \
- {"r", (RTL_BIT) }, \
- {"space", (SPACE_BIT) }, \
+{ {"0", SH0_BIT}, \
+ {"1", SH1_BIT}, \
+ {"2", SH2_BIT}, \
+ {"3", SH3_BIT|SH2_BIT}, \
+ {"3e", SH3E_BIT|SH3_BIT|SH2_BIT}, \
+ {"b", -LITTLE_ENDIAN_BIT}, \
+ {"bigtable", BIGTABLE_BIT}, \
+ {"dalign", DALIGN_BIT}, \
+ {"hitachi", HITACHI_BIT}, \
+ {"isize", ISIZE_BIT}, \
+ {"l", LITTLE_ENDIAN_BIT}, \
+ {"padstruct", PADSTRUCT_BIT}, \
+ {"relax", RELAX_BIT}, \
+ {"space", SPACE_BIT}, \
{"", TARGET_DEFAULT} \
}
+#define TARGET_DEFAULT (0)
-#define TARGET_DEFAULT (FAST_BIT)
-
-
-/* Macro to define table for command options with values. */
-#define TARGET_OPTIONS \
- { { "maxsi-", &max_si}, \
- { "maxhi-", &max_hi} }
-
+#define PRESERVE_DEATH_INFO_REGNO_P(regno) (TARGET_RELAX || optimize)
#define OVERRIDE_OPTIONS \
do { \
sh_cpu = CPU_SH1; \
if (TARGET_SH2) \
sh_cpu = CPU_SH2; \
- if (TARGET_SH3) \
- sh_cpu = CPU_SH3|CPU_SH2; \
+ if (TARGET_SH3) \
+ sh_cpu = CPU_SH3; \
+ if (TARGET_SH3E) \
+ sh_cpu = CPU_SH3E; \
\
- /* We *MUST* always define optimize since we *HAVE* to run \
- shorten branches to get correct code. */ \
- \
- optimize = 1; \
- flag_delayed_branch = 1; \
- /* But never run scheduling before reload, since than can \
- break global alloc, and generates slower code anyway due \
- to the pressure on R0. */ \
- flag_schedule_insns = 0; \
- if (max_si) \
- max_count_si = atoi (max_si); \
- else \
- max_count_si = 1010; \
- if (max_hi) \
- max_count_hi = atoi (max_hi); \
- else \
- max_count_hi = 500; \
+ /* Never run scheduling before reload, since that can \
+ break global alloc, and generates slower code anyway due \
+ to the pressure on R0. */ \
+ flag_schedule_insns = 0; \
} while (0)
\f
-/* Target machine storage Layout. */
+/* Target machine storage layout. */
/* Define to use software floating point emulator for REAL_ARITHMETIC and
decimal <-> binary conversion. */
#define BITS_BIG_ENDIAN 0
-
/* Define this if most significant byte of a word is the lowest numbered. */
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
numbered. */
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
-
/* Define this to set the endianness to use in libgcc2.c, which can
not depend on target_flags. */
#if defined(__LITTLE_ENDIAN__)
#define FASTEST_ALIGNMENT 32
/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < FASTEST_ALIGNMENT) \
? FASTEST_ALIGNMENT : (ALIGN))
/* Number of bits which any structure or union's size must be a
multiple of. Each structure or union's size is rounded up to a
multiple of this. */
-#define STRUCTURE_SIZE_BOUNDARY (TARGET_PACKSTRUCT ? 8 : 32)
+#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
r0 arg return
r1..r3 scratch
- r4-r7 args in
+ r4..r7 args in
r8..r13 call saved
r14 frame pointer/call saved
r15 stack pointer
pr subroutine return address
t t bit
mach multiply/accumulate result, high part
- macl multiply/accumulate result, low part. */
+ macl multiply/accumulate result, low part.
+ fpul fp/int communication register
+ rap return address pointer register
+ fr0 fp arg return
+ fr1..fr3 scratch floating point registers
+ fr4..fr11 fp args in
+ fr12..fr15 call saved floating point registers */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
#define GBR_REG 19
#define MACH_REG 20
#define MACL_REG 21
+#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
+#define FPUL_REG 22
+#define RAP_REG 23
+#define FIRST_FP_REG 24
+#define LAST_FP_REG 39
-#define FIRST_PSEUDO_REGISTER 22
+#define FIRST_PSEUDO_REGISTER 40
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
Mach register is fixed 'cause it's only 10 bits wide for SH1.
It is 32 bits wide for SH2. */
- /* r0 r1 r2 r3
- r4 r5 r6 r7
- r8 r9 r10 r11
- r12 r13 r14 r15
- ap pr t gbr
- mh ml */
-
#define FIXED_REGISTERS \
{ 0, 0, 0, 0, \
0, 0, 0, 0, \
0, 0, 0, 0, \
0, 0, 0, 1, \
1, 1, 1, 1, \
- 1, 1}
-
+ 1, 1, 1, 1, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 0 \
+}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
- /* r0 r1 r2 r3
- r4 r5 r6 r7
- r8 r9 r10 r11
- r12 r13 r14 r15
- ap pr t gbr
- mh ml */
-
#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, \
- 1, 1, 1, 1, \
- 0, 0, 0, 0, \
- 0, 0, 0, 1, \
- 1, 0, 1, 1, \
- 1, 1}
+ { 1, 1, 1, 1, \
+ 1, 1, 1, 1, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 1, \
+ 1, 0, 1, 1, \
+ 1, 1, 1, 1, \
+ 1, 1, 1, 1, \
+ 1, 1, 1, 1, \
+ 1, 1, 1, 1, \
+ 0, 0, 0, 0 \
+}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
On the SH regs are UNITS_PER_WORD bits wide. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
+#define HARD_REGNO_NREGS(REGNO, MODE) \
(((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- We may keep double values in even registers. */
+ We can allow any mode in any general register. The special registers
+ only allow SImode. Don't allow any mode in the PR. */
-extern int hard_regno_mode_ok[];
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (hard_regno_mode_ok[REGNO] & (1<<(int)MODE))
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ (SPECIAL_REG (REGNO) ? (MODE) == SImode \
+ : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
+ : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG ? (MODE) == SFmode \
+ : (REGNO) == PR_REG ? 0 \
+ : 1)
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
/* Base register for access to local variables of the function. */
#define FRAME_POINTER_REGNUM 14
+/* Fake register that holds the address on the stack of the
+ current function's return address. */
+#define RETURN_ADDRESS_POINTER_REGNUM 23
+
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may be accessed
via the stack pointer) in functions that seem suitable. */
followed by "to". Eliminations of the same "from" register are listed
in order of preference. */
-#define ELIMINABLE_REGS \
-{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
- { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
-
+#define ELIMINABLE_REGS \
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
/* Given FROM and TO register numbers, say whether this elimination
is allowed. */
/*#define STRUCT_VALUE ((rtx)0)*/
-
/* Don't default to pcc-struct-return, because we have already specified
exactly how to return structures in the RETURN_IN_MEMORY macro. */
/* The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the
- Procedure Return Register and the Multipy Accumulate Registers. */
+ Procedure Return Register and the Multiply Accumulate Registers. */
enum reg_class
{
T_REGS,
MAC_REGS,
GENERAL_REGS,
+ FPUL_REGS,
+ FP0_REGS,
+ FP_REGS,
+ GENERAL_FP_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
-#define REG_CLASS_NAMES \
+#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"R0_REGS", \
"T_REGS", \
"MAC_REGS", \
"GENERAL_REGS", \
+ "FPUL_REGS", \
+ "FP0_REGS", \
+ "FP_REGS", \
+ "GENERAL_FP_REGS", \
"ALL_REGS", \
}
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
-{ \
- 0x000000, /* NO_REGS */ \
- 0x000001, /* R0_REGS */ \
- 0x020000, /* PR_REGS */ \
- 0x040000, /* T_REGS */ \
- 0x300000, /* MAC_REGS */ \
- 0x01FFFF, /* GENERAL_REGS */ \
- 0x37FFFF /* ALL_REGS */ \
+#define REG_CLASS_CONTENTS \
+{ \
+ { 0x00000000, 0x00000000 }, /* NO_REGS */ \
+ { 0x00000001, 0x00000000 }, /* R0_REGS */ \
+ { 0x00020000, 0x00000000 }, /* PR_REGS */ \
+ { 0x00040000, 0x00000000 }, /* T_REGS */ \
+ { 0x00300000, 0x00000000 }, /* MAC_REGS */ \
+ { 0x0001FFFF, 0x00000000 }, /* GENERAL_REGS */ \
+ { 0x00400000, 0x00000000 }, /* FPUL_REGS */ \
+ { 0x01000000, 0x00000000 }, /* FP0_REGS */ \
+ { 0xFF000000, 0x000000FF }, /* FP_REGS */ \
+ { 0xFF01FFFF, 0x000000FF }, /* GENERAL_FP_REGS */ \
+ { 0xFF7FFFFF, 0x000000FF }, /* ALL_REGS */ \
}
/* The same information, inverted:
#define SMALL_REGISTER_CLASSES
/* The order in which register should be allocated. */
-#define REG_ALLOC_ORDER \
- { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
+#define REG_ALLOC_ORDER \
+ { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
+ 24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, \
+ 22,15,16,17,18,19,20,21,23 }
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS R0_REGS
#define REG_CLASS_FROM_LETTER(C) \
( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
-
-
+\f
/* The letters I, J, K, L and M in a register constraint string
can be used to stand for particular ranges of immediate operands.
This macro defines what the ranges are.
M: constant 1
N: constant 0 */
-
#define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
#define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
- : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
- : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
- : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
- : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
+ ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
+ : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
+ : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
+ : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
+ : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: 0)
/* Similar, but for floating constants, and defining letters G and H.
Here VALUE is the CONST_DOUBLE rtx itself. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
- && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
- : 0)
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
+((C) == 'G' ? fp_zero_operand (VALUE) \
+ : (C) == 'H' ? fp_one_operand (VALUE) \
+ : (C) == 'F')
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
+/* ??? Should make FPUL register a nn-fixed register and make it's
+ use explicit in the rtl; then change this definition here to
+ ... ? FPUL_REGS : NO_REGS) . */
+#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
+ ((((CLASS == FP_REGS || CLASS == FP0_REGS) \
+ && GET_CODE (X) == REG && REGNO (X) <= AP_REG) \
+ || (CLASS == GENERAL_REGS && GET_CODE (X) == REG \
+ && REGNO (X) <= FIRST_FP_REG && REGNO (X) >= LAST_FP_REG)) \
+ ? /* FPUL_REGS */ NO_REGS : NO_REGS)
+
+#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
+ (((CLASS == FP_REGS || CLASS == FP0_REGS) && immediate_operand (X, MODE)\
+ && ! (fp_one_operand (X) || fp_one_operand (X))) \
+ ? R0_REGS : SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X))
+
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS.
On SH this is the size of MODE in words. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
+#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
\f
/* Stack layout; function entry, exit and calling. */
-/* Define the number of register that can hold parameters.
- These two macros are used only in other macro definitions below. */
-#define NPARM_REGS 4
+/* Define the number of registers that can hold parameters.
+ These macros are used only in other macro definitions below. */
+
+#define NPARM_REGS(MODE) \
+ ((TARGET_SH3E && ((MODE) == SFmode)) ? 8 : 4)
+
#define FIRST_PARM_REG 4
#define FIRST_RET_REG 0
+#define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
+#define FIRST_FP_RET_REG FIRST_FP_REG
+
/* Define this if pushing a word on the stack
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
on the stack. */
#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
+/* Some subroutine macros specific to this machine. */
+
+#define BASE_RETURN_VALUE_REG(MODE) \
+ ((TARGET_SH3E && ((MODE) == SFmode)) \
+ ? FIRST_FP_RET_REG \
+ : FIRST_RET_REG)
+
+#define BASE_ARG_REG(MODE) \
+ ((TARGET_SH3E && ((MODE) == SFmode)) \
+ ? FIRST_FP_PARM_REG \
+ : FIRST_PARM_REG)
+
/* Define how to find the value returned by a function.
VALTYPE is the data type of the value (as a tree).
If the precise function being called is known, FUNC is its FUNCTION_DECL;
otherwise, FUNC is 0. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx (REG, \
- TYPE_MODE (VALTYPE) == BLKmode ? SImode : TYPE_MODE (VALTYPE), \
- FIRST_RET_REG)
-
+ LIBCALL_VALUE (TYPE_MODE (VALTYPE))
+
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
-#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, MODE, FIRST_RET_REG)
+#define LIBCALL_VALUE(MODE) \
+ gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE));
-/* 1 if N is a possible register number for a function value.
- On the SH, only r0 can return results. */
-#define FUNCTION_VALUE_REGNO_P(REGNO) \
- ((REGNO) == FIRST_RET_REG)
+/* 1 if N is a possible register number for a function value. */
+#define FUNCTION_VALUE_REGNO_P(REGNO) \
+ ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
/* 1 if N is a possible register number for function argument passing. */
-
-#define FUNCTION_ARG_REGNO_P(REGNO) \
- ((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
+#define FUNCTION_ARG_REGNO_P(REGNO) \
+ (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
+ || (TARGET_SH3E \
+ && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
if any, which holds the structure-value-address).
Thus NARGREGS or more means all following args should go on the stack. */
-#define CUMULATIVE_ARGS int
+enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
+struct sh_args {
+ int arg_count[2];
+};
+
+#define CUMULATIVE_ARGS struct sh_args
+
+#define GET_SH_ARG_CLASS(MODE) \
+ ((TARGET_SH3E && ((MODE) == SFmode)) ? SH_ARG_FLOAT : SH_ARG_INT)
-#define ROUND_ADVANCE(SIZE) \
+#define ROUND_ADVANCE(SIZE) \
((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Round a register number up to a proper boundary for an arg of mode
The SH doesn't care about double alignment, so we only
round doubles to even regs when asked to explicitly. */
-#define ROUND_REG(X, MODE) \
- ((TARGET_ALIGN_DOUBLE \
- && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
- ? ((X) + ((X) & 1)) : (X))
-
+#define ROUND_REG(CUM, MODE) \
+ ((TARGET_ALIGN_DOUBLE \
+ && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
+ ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
+ + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
+ : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
On SH, the offset always starts at 0: the first parm reg is always
the same reg. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
- ((CUM) = 0)
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
+ do { \
+ (CUM).arg_count[(int) SH_ARG_INT] = 0; \
+ (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
+ } while (0)
/* Update the data in CUM to advance over an argument
of mode MODE and data type TYPE.
available.) */
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM) = (ROUND_REG ((CUM), (MODE)) \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] = \
+ (ROUND_REG ((CUM), (MODE)) \
+ ((MODE) != BLKmode \
? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
: ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
+/* Return boolean indicating arg of mode MODE will be passed in a reg.
+ This macro is only used in this file. */
+
+#define PASS_IN_REG_P(CUM, MODE, TYPE) \
+ (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
+ && ((TYPE) == 0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
+ && (! TARGET_SH3E || (ROUND_REG((CUM), (MODE)) + (GET_MODE_SIZE(MODE)/4) <= NPARM_REGS (MODE))))
+
/* Define where to put the arguments to a function.
Value is zero to push the argument on the stack,
or a hard register in which to store the argument.
its data type forbids. */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- sh_function_arg (CUM, MODE, TYPE, NAMED)
-
-extern struct rtx_def *sh_function_arg();
+ ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
+ && (NAMED || TARGET_SH3E)) \
+ ? gen_rtx (REG, (MODE), \
+ (BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
+ : 0)
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
We sometimes split args. */
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
- sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
+ ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
+ && (NAMED || TARGET_SH3E) \
+ && (ROUND_REG ((CUM), (MODE)) \
+ + (MODE != BLKmode \
+ ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
+ : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
+ - NPARM_REGS (MODE) > 0)) \
+ ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
+ : 0)
extern int current_function_anonymous_args;
#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
current_function_anonymous_args = 1;
-/* Call the function profiler with a given profile label. */
+/* Call the function profiler with a given profile label.
+ We use two .aligns, so as to make sure that both the .long is aligned
+ on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
+ from the trapa instruction. */
#define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
- fprintf(STREAM, " trapa #5\n"); \
+ fprintf(STREAM, " .align 2\n"); \
+ fprintf(STREAM, " trapa #33\n"); \
fprintf(STREAM, " .align 2\n"); \
fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
}
+/* Define this macro if the code for function profiling should come
+ before the function prologue. Normally, the profiling code comes
+ after. */
+
+#define PROFILE_BEFORE_PROLOGUE
+
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
- On the SH, the trapoline looks like
+ On the SH, the trampoline looks like
1 0000 D301 mov.l l1,r3
2 0002 DD02 mov.l l2,r13
3 0004 4D2B jmp @r13
{ \
fprintf ((FILE), " .word 0xd301\n"); \
fprintf ((FILE), " .word 0xdd02\n"); \
- fprintf ((FILE), " .word 0x4d2b\n"); \
+ fprintf ((FILE), " .word 0x4d2b\n"); \
fprintf ((FILE), " .word 0x200b\n"); \
fprintf ((FILE), " .long 0\n"); \
fprintf ((FILE), " .long 0\n"); \
FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
(CXT)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
(FNADDR)); \
}
+
+/* A C expression whose value is RTL representing the value of the return
+ address for the frame COUNT steps up from the current frame.
+ FRAMEADDR is already the frame pointer of the COUNT frame, so we
+ can ignore COUNT. */
+
+#define RETURN_ADDR_RTX(COUNT, FRAME) \
+ ((COUNT == 0) \
+ ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
+ : (rtx) 0)
+\f
+/* Generate necessary RTL for __builtin_saveregs().
+ ARGLIST is the argument list; see expr.c. */
+extern struct rtx_def *sh_builtin_saveregs ();
+#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sh_builtin_saveregs (ARGLIST)
\f
/* Addressing modes, and classification of registers for them. */
#define HAVE_POST_INCREMENT 1
Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in local-alloc.c. */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
+#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
/* Maximum number of registers that can appear in a valid memory
/* Recognize any constant value that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF)
+#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
/* Nonzero if the constant value X is a legitimate general operand. */
#define LEGITIMATE_CONSTANT_P(X) \
- (GET_CODE(X) != CONST_DOUBLE /*&& GET_CODE(X) != LABEL_REF*/)
+ (GET_CODE (X) != CONST_DOUBLE \
+ || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
+ || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
them unless they have been allocated suitable hard regs.
The symbol REG_OK_STRICT causes the latter definition to be used. */
-#define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
-#define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
-
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
- (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
+ (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
-
#define REG_OK_FOR_INDEX_P(X) \
- (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
+ (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-#define REG_OK_FOR_PRE_POST_P(X) \
- (REG_OK_FOR_BASE_P (X))
+/* Nonzero if X/OFFSET is a hard reg that can be used as an index
+ or if X is a pseudo reg. */
+#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
+ ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
#else
+
/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) \
- REGNO_OK_FOR_BASE_P (REGNO (X))
+#define REG_OK_FOR_BASE_P(X) \
+ REGNO_OK_FOR_BASE_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) \
- REGNO_OK_FOR_INDEX_P (REGNO (X))
+#define REG_OK_FOR_INDEX_P(X) \
+ REGNO_OK_FOR_INDEX_P (REGNO (X))
+
+/* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
+#define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
+ (REGNO_OK_FOR_INDEX_P (REGNO (X)) && OFFSET == 0)
-#define REG_OK_FOR_PRE_POST_P(X) \
- (REGNO_OK_FOR_BASE_P (REGNO (X)))
#endif
-/* The Q is a pc relative load operand. */
+/* The 'Q' constraint is a pc relative load operand. */
#define EXTRA_CONSTRAINT_Q(OP) \
(GET_CODE (OP) == MEM && \
((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
&& GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
&& GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
-#define IS_INDEX(OP) \
- ((GET_CODE (OP) == PLUS && \
- (INDEX_REGISTER_RTX_P (XEXP (OP, 0)) && BASE_REGISTER_RTX_P (XEXP (OP, 1))) || \
- (INDEX_REGISTER_RTX_P (XEXP (OP, 1)) && BASE_REGISTER_RTX_P (XEXP (OP, 0)))))
-
-
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
- : 0)
+#define EXTRA_CONSTRAINT(OP, C) \
+ ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
+ : 0)
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
-#define BASE_REGISTER_RTX_P(X) \
- (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-#define INDEX_REGISTER_RTX_P(X) \
- (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
+#define MODE_DISP_OK_4(X,MODE) \
+(GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
+ && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && MODE == SFmode))
+#define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
+#define BASE_REGISTER_RTX_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+
+/* Since this must be r0, which is a single register class, we must check
+ SUBREGs more carefully, to be sure that we don't accept one that extends
+ outside the class. */
+#define INDEX_REGISTER_RTX_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
/* Jump to LABEL if X is a valid address RTX. This must also take
REG_OK_STRICT into account when deciding about valid registers, but it uses
REG++
--REG */
+/* ??? The SH3e does not have the REG+disp addressing mode when loading values
+ into the FRx registers. We implement this by setting the maximum offset
+ to zero when the value is SFmode. This also restricts loading of SFmode
+ values into the integer registers, but that can't be helped. */
+
/* The SH allows a displacement in a QI or HI amode, but only when the
other operand is R0. GCC doesn't handle this very well, so we forgo
all of that.
- A legitimate index for a QI or HI is 0, SI and above can be any
- number 0..63. */
+ A legitimate index for a QI or HI is 0, SI can be any number 0..63,
+ DI can be any number 0..60. */
-#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
+#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
do { \
if (GET_CODE (OP) == CONST_INT) \
{ \
} \
} while(0)
-
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
-{ \
- if (BASE_REGISTER_RTX_P (X)) \
- goto LABEL; \
- else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
- goto LABEL; \
- else if (GET_CODE (X) == PLUS) \
- { \
- rtx xop0 = XEXP(X,0); \
- rtx xop1 = XEXP(X,1); \
- if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
- GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
- if (GET_MODE_SIZE(MODE) <= 8 && BASE_REGISTER_RTX_P (xop1)) \
- GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
- if (GET_MODE_SIZE(MODE)<= 4) { \
- if(BASE_REGISTER_RTX_P(xop1) && \
- INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \
- if(INDEX_REGISTER_RTX_P(xop1) && \
- BASE_REGISTER_RTX_P(xop0)) goto LABEL; \
- } \
- } \
- else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
- goto LABEL; \
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+{ \
+ if (BASE_REGISTER_RTX_P (X)) \
+ goto LABEL; \
+ else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
+ && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
+ goto LABEL; \
+ else if (GET_CODE (X) == PLUS) \
+ { \
+ rtx xop0 = XEXP (X, 0); \
+ rtx xop1 = XEXP (X, 1); \
+ if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
+ GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
+ if (GET_MODE_SIZE (MODE) <= 4) \
+ { \
+ if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
+ goto LABEL; \
+ if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
+ goto LABEL; \
+ } \
+ } \
}
\f
/* Try machine-dependent ways of modifying an illegitimate address
GO_IF_LEGITIMATE_ADDRESS.
It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output. */
+ opportunities to optimize the output.
-#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
+ For the SH, if X is almost suitable for indexing, but the offset is
+ out of range, convert it into a normal form so that cse has a chance
+ of reducing the number of address registers used. */
+
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
+{ \
+ if (GET_CODE (X) == PLUS \
+ && (GET_MODE_SIZE (MODE) == 4 \
+ || GET_MODE_SIZE (MODE) == 8) \
+ && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
+ && ! (TARGET_SH3E && MODE == SFmode)) \
+ { \
+ rtx index_rtx = XEXP (X, 1); \
+ HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
+ rtx sum; \
+ \
+ GO_IF_LEGITIMATE_INDEX (MODE, index_rtx, WIN); \
+ /* On rare occasions, we might get an unaligned pointer \
+ that is indexed in a way to give an aligned address. \
+ Therefore, keep the lower two bits in offset_base. */ \
+ /* Instead of offset_base 128..131 use 124..127, so that \
+ simple add suffices. */ \
+ if (offset > 127) \
+ { \
+ offset_base = ((offset + 4) & ~60) - 4; \
+ } \
+ else \
+ offset_base = offset & ~60; \
+ /* Sometimes the normal form does not suit DImode. We \
+ could avoid that by using smaller ranges, but that \
+ would give less optimized code when SImode is \
+ prevalent. */ \
+ if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
+ { \
+ sum = expand_binop (Pmode, add_optab, XEXP (X, 0), \
+ GEN_INT (offset_base), NULL_RTX, 0, \
+ OPTAB_LIB_WIDEN); \
+ \
+ (X) = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base)); \
+ goto WIN; \
+ } \
+ } \
+}
/* Go to LABEL if ADDR (a legitimate address expression)
has an effect that depends on the machine mode it is used for. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
{ \
- if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
- || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
+ if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
goto LABEL; \
}
\f
/* This is the kind of divide that is easiest to do in the general case. */
#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+/* Since the SH3e has only `float' support, it is desirable to make all
+ floating point types equivalent to `float'. */
+#define DOUBLE_TYPE_SIZE (TARGET_SH3E ? 32 : 64)
+
/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
done, NIL if none. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
+/* Define if loading short immediate values into registers sign extends. */
+#define SHORT_IMMEDIATES_SIGN_EXTEND
+
/* Define this if zero-extension is slow (more than one real instruction).
On the SH, it's only one instruction. */
/* #define SLOW_ZERO_EXTEND */
that the native compiler puts too large (> 32) immediate shift counts
into a register and shifts by the register, letting the SH decide what
to do instead of doing that itself. */
+/* ??? This is defined, but the library routines in lib1funcs.asm do not
+ truncate the shift count. This may result in incorrect results for
+ unusual cases. Truncating the shift counts in the library routines would
+ make them faster. However, the SH3 has hardware shifts that do not
+ truncate, so it appears that we need to leave this undefined for correct
+ SH3 code. We can still using truncation in the library routines though to
+ make them faster. */
#define SHIFT_COUNT_TRUNCATED 1
/* All integers have the same format so truncation is easy. */
/* The relative costs of various types of constants. Note that cse.c defines
REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
-#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
+#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
case CONST_INT: \
if (INTVAL (RTX) == 0) \
return 0; \
#define RTX_COSTS(X, CODE, OUTER_CODE) \
case AND: \
- return COSTS_N_INSNS (andcosts (X)); \
+ return COSTS_N_INSNS (andcosts (X)); \
case MULT: \
return COSTS_N_INSNS (multcosts (X)); \
case ASHIFT: \
case FIX: \
return 100;
-
/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
are actually function calls with some special constraints on arguments
and register usage.
&& GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_type (X) == TYPE_SFUNC))
+/* Compute the cost of an address. For the SH, all valid addresses are
+ the same cost. */
+/* ??? Perhaps we should make reg+reg addresses have higher cost because
+ they add to register pressure on r0. */
+
+#define ADDRESS_COST(RTX) 1
+
/* Compute extra cost of moving data between one register class
and another.
On the SH it is hard to move into the T reg, but simple to load
from it. */
-#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
- (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
+#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
+ (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 \
+ : ((DSTCLASS == FP_REGS && SRCCLASS == GENERAL_REGS) \
+ || (DSTCLASS == GENERAL_REGS && SRCCLASS == FP_REGS)) ? 4 \
+ : 1)
+
+/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
+ would be so that people would slow memory systems could generate
+ different code that does fewer memory accesses. */
\f
/* Assembler output control. */
+/* A C string constant describing how to begin a comment in the target
+ assembler language. The compiler assumes that the comment will end at
+ the end of the line. */
+#define ASM_COMMENT_START "!"
+
/* The text to go at the start of the assembler file. */
-#define ASM_FILE_START(STREAM) \
- output_file_start (STREAM, f_options, \
- sizeof f_options / sizeof f_options[0], \
- W_options, sizeof W_options / sizeof W_options[0]);
+#define ASM_FILE_START(STREAM) \
+ output_file_start (STREAM)
#define ASM_FILE_END(STREAM)
#define ASM_APP_OFF ""
#define FILE_ASM_OP "\t.file\n"
#define IDENT_ASM_OP "\t.ident\n"
+#define SET_ASM_OP ".set"
/* How to change between sections. */
#define DATA_SECTION_ASM_OP "\t.data"
#define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
#define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
-#define INIT_SECTION_ASM_OP "\t.section\t.init\n"
#define EXTRA_SECTIONS in_ctors, in_dtors
-#define EXTRA_SECTION_FUNCTIONS \
-void \
-ctors_section() \
-{ \
- if (in_section != in_ctors) \
- { \
- fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
- in_section = in_ctors; \
- } \
-} \
-void \
-dtors_section() \
-{ \
- if (in_section != in_dtors) \
- { \
- fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
- in_section = in_dtors; \
- } \
+#define EXTRA_SECTION_FUNCTIONS \
+void \
+ctors_section() \
+{ \
+ if (in_section != in_ctors) \
+ { \
+ fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
+ in_section = in_ctors; \
+ } \
+} \
+void \
+dtors_section() \
+{ \
+ if (in_section != in_dtors) \
+ { \
+ fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
+ in_section = in_dtors; \
+ } \
}
+/* Define this so that jump tables go in same section as the current function,
+ which could be text or it could be a user defined section. */
+#define JUMP_TABLES_IN_TEXT_SECTION
+
/* A C statement to output something to the assembler file to switch to section
NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
NULL_TREE. Some target formats do not support arbitrary sections. Do not
#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
#undef DO_GLOBAL_CTORS_BODY
}
#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY \
+#define DO_GLOBAL_DTORS_BODY \
{ \
typedef (*pfunc)(); \
extern pfunc __dtors[]; \
} \
}
-
#define ASM_OUTPUT_REG_PUSH(file, v) \
fprintf (file, "\tmov.l r%s,-@r15\n", v);
#define ASM_OUTPUT_REG_POP(file, v) \
fprintf (file, "\tmov.l @r15+,r%s\n", v);
-
/* The assembler's names for the registers. RFP need not always be used as
the Real framepointer; it can also be used as a normal general register.
Note that the name `fp' is horribly misleading since `fp' is in fact only
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
- "ap", "pr", "t", "gbr", "mach","macl" \
+ "ap", "pr", "t", "gbr", "mach","macl", "fpul","rap", \
+ "fr0","fr1","fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
+ "fr8","fr9","fr10","fr11","fr12","fr13","fr14","fr15",\
}
/* DBX register number for a given compiler register number. */
-#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+/* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
+ to match gdb. */
+#define DBX_REGISTER_NUMBER(REGNO) \
+ (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
/* Output a label definition. */
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
+#define ASM_OUTPUT_LABEL(FILE,NAME) \
do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
/* This is how to output an assembler line
that says to advance the location counter
to a multiple of 2**LOG bytes. */
ASM_OUTPUT_LABEL(STREAM, NAME)
/* Output a globalising directive for a label. */
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
- (fprintf (STREAM, "\t.global\t"), \
- assemble_name (STREAM, NAME), \
- fputc ('\n',STREAM)) \
+#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
+ (fprintf (STREAM, "\t.global\t"), \
+ assemble_name (STREAM, NAME), \
+ fputc ('\n',STREAM))
-/* Output a reference to a label. */
-#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
- fprintf (STREAM, "_%s", NAME)
+/* The prefix to add to user-visible assembler symbols. */
+
+#define USER_LABEL_PREFIX "_"
/* Make an internal label into a string. */
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
sprintf (STRING, "*%s%d", PREFIX, NUM)
/* Output an internal label definition. */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
fprintf (FILE, "%s%d:\n", PREFIX, NUM)
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* Construct a private name. */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
- ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
+#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
+ ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
/* Jump tables must be 32 bit aligned, no matter the size of the element. */
#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
- fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
+ fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
/* Output a relative address table. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
if (TARGET_BIGTABLE) \
- fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
+ fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
else \
- fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
/* Output an absolute table element. */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (TARGET_BIGTABLE) \
- fprintf (STREAM, "\t.long L%d\n", VALUE); \
+ fprintf (STREAM, "\t.long L%d\n", VALUE); \
else \
- fprintf (STREAM, "\t.word L%d\n", VALUE); \
+ fprintf (STREAM, "\t.word L%d\n", VALUE); \
/* Output various types of constants. */
-
/* This is how to output an assembler line defining a `double'. */
#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
fprintf (FILE, "\t.double %s\n", dstr); \
} while (0)
-
/* This is how to output an assembler line defining a `float' constant. */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
+#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
do { char dstr[30]; \
REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
fprintf (FILE, "\t.float %s\n", dstr); \
output_addr_const (STREAM, (EXP)), \
fputc ('\n', STREAM))
-#define ASM_OUTPUT_SHORT(STREAM, EXP) \
- (fprintf (STREAM, "\t.short\t"), \
- output_addr_const (STREAM, (EXP)), \
+#define ASM_OUTPUT_SHORT(STREAM, EXP) \
+ (fprintf (STREAM, "\t.short\t"), \
+ output_addr_const (STREAM, (EXP)), \
fputc ('\n', STREAM))
#define ASM_OUTPUT_CHAR(STREAM, EXP) \
#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
fprintf (STREAM, "\t.byte\t%d\n", VALUE) \
+/* Align loops and labels after unconditional branches to get faster
+ code. */
+
+#define ASM_OUTPUT_LOOP_ALIGN(FILE) \
+ if (! TARGET_SMALLCODE) \
+ ASM_OUTPUT_ALIGN ((FILE), 2)
+
+#define ASM_OUTPUT_ALIGN_CODE(FILE) \
+ if (! TARGET_SMALLCODE) \
+ ASM_OUTPUT_ALIGN ((FILE), (TARGET_SH3 || TARGET_SH3E) ? 4 : 2)
+
/* This is how to output an assembler line
that says to advance the location counter by SIZE bytes. */
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
+#define ASM_OUTPUT_SKIP(FILE,SIZE) \
fprintf (FILE, "\t.space %d\n", (SIZE))
/* This says how to output an assembler line
to define a global common symbol. */
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
( fputs ("\t.comm ", (FILE)), \
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (SIZE)))
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (SIZE)))
-
/* The assembler's parentheses characters. */
#define ASM_OPEN_PAREN "("
#define ASM_CLOSE_PAREN ")"
#define TARGET_CR 015
\f
/* Only perform branch elimination (by making instructions conditional) if
- we're optimising. Otherwise it's of no use anyway. */
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
- final_prescan_insn (INSN, OPVEC, NOPERANDS)
+ we're optimizing. Otherwise it's of no use anyway. */
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
+ final_prescan_insn (INSN, OPVEC, NOPERANDS)
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
extern struct rtx_def *sh_compare_op1;
extern struct rtx_def *prepare_scc_operands();
-
/* Which processor to schedule for. The elements of the enumeration must
match exactly the cpu attribute in the sh.md file. */
PROCESSOR_SH0,
PROCESSOR_SH1,
PROCESSOR_SH2,
- PROCESSOR_SH3
+ PROCESSOR_SH3,
+ PROCESSOR_SH3E
};
#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
#define TARGET_MEM_FUNCTIONS
-#define HANDLE_PRAGMA(finput) return handle_pragma (finput)
+/* Define this macro if you want to implement any pragmas. If defined, it
+ is a C expression to be executed when #pragma is seen. The
+ argument FILE is the stdio input stream from which the source
+ text can be read. CH is the first character after the #pragma. The
+ result of the expression is the terminating character found
+ (newline or EOF). */
+#define HANDLE_PRAGMA(FILE, NODE) handle_pragma (FILE, NODE)
/* Set when processing a function with pragma interrupt turned on. */
extern int pragma_interrupt;
-#define MOVE_RATIO (TARGET_SMALLCODE ? 4 : 16)
-extern char *max_si;
-extern char *max_hi;
-extern int max_count_si;
-extern int max_count_hi;
+#define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
\f
/* Instructions with unfilled delay slots take up an extra two bytes for
- the nop in the delay slot. */
+ the nop in the delay slot. Instructions at the start of loops, or
+ after unconditional branches, may take up extra room when they are
+ aligned. ??? We would get more accurate results if we did instruction
+ alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
+ here is too conservative. */
#define ADJUST_INSN_LENGTH(X, LENGTH) \
if (((GET_CODE (X) == INSN \
&& GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
&& GET_CODE (PATTERN (X)) != ADDR_VEC)) \
&& get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
- LENGTH += 2;
+ LENGTH += 2; \
+ if (! TARGET_SMALLCODE) \
+ { \
+ rtx aip; \
+ for (aip = PREV_INSN (X); aip; aip = PREV_INSN (aip)) \
+ { \
+ if (GET_CODE (aip) == BARRIER) \
+ { \
+ if (TARGET_SH3 || TARGET_SH3E) \
+ LENGTH += 14; \
+ else \
+ LENGTH += 2; \
+ break; \
+ } \
+ else if ((GET_CODE (aip) == NOTE \
+ && NOTE_LINE_NUMBER (aip) == NOTE_INSN_LOOP_BEG)) \
+ { \
+ LENGTH += 2; \
+ break; \
+ } \
+ else if (GET_CODE (aip) != NOTE \
+ && GET_CODE (aip) != CODE_LABEL) \
+ break; \
+ } \
+ }
/* Enable a bug fix for the shorten_branches pass. */
#define SHORTEN_WITH_ADJUST_INSN_LENGTH
+\f
+/* Define the codes that are matched by predicates in sh.c. */
+#define PREDICATE_CODES \
+ {"arith_reg_operand", {SUBREG, REG}}, \
+ {"arith_operand", {SUBREG, REG, CONST_INT}}, \
+ {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
+ {"logical_operand", {SUBREG, REG, CONST_INT}}, \
+ {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
+ {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
+
+/* Define this macro if it is advisable to hold scalars in registers
+ in a wider mode than that declared by the program. In such cases,
+ the value is constrained to be within the bounds of the declared
+ type, but kept valid in the wider mode. The signedness of the
+ extension may differ from that of the type.
+
+ Leaving the unsignedp unchanged gives better code than always setting it
+ to 0. This is despite the fact that we have only signed char and short
+ load instructions. */
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+ if (GET_MODE_CLASS (MODE) == MODE_INT \
+ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
+ MODE = SImode;
+
+/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
+ extensions applied to char/short functions arguments. Defining
+ PROMOTE_FUNCTION_RETURN does the same for function returns. */
+
+#define PROMOTE_FUNCTION_ARGS
+#define PROMOTE_FUNCTION_RETURN
+
+/* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
+ and poping arguments. However, we do have push/pop instructions, and
+ rather limited offsets (4 bits) in load/store instructions, so it isn't
+ clear if this would give better code. If implemented, should check for
+ compatibility problems. */
+
+/* ??? Define ADJUST_COSTS? */
+
+/* Since the SH architecture lacks negative address offsets,
+ the givs should be sorted smallest to largest so combine_givs
+ has maximum opportunity to combine givs. */
+#define GIV_SORT_CRITERION(X, Y) \
+ if (GET_CODE ((X)->add_val) == CONST_INT \
+ && GET_CODE ((Y)->add_val) == CONST_INT) \
+ return INTVAL ((X)->add_val) - INTVAL ((Y)->add_val);
+
+/* For the sake of libgcc2.c, indicate target supports atexit. */
+#define HAVE_ATEXIT
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