-/* Definitions of target machine for GNU compiler, for Hitachi Super-H.
- Copyright (C) 1993 Free Software Foundation, Inc.
-
- Contributed by Steve Chamberlain (sac@cygnus.com)
+/* Definitions of target machine for GNU compiler for Hitachi Super-H.
+ Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
+ Contributed by Steve Chamberlain (sac@cygnus.com).
+ Improved by Jim Wilson (wilson@cygnus.com).
This file is part of GNU CC.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
-\f
-/* Run-time Target Specification. */
-#define TARGET_SH
-#define TARGET_VERSION \
+#define TARGET_VERSION \
fputs (" (Hitachi SH)", stderr);
/* Generate SDB debugging information. */
-#define SDB_DEBUGGING_INFO 1
+#define SDB_DEBUGGING_INFO
-#define SDB_DELIM ";"
+/* Output DBX (stabs) debugging information if doing -gstabs. */
-#define CPP_PREDEFINES "-D__sh__"
+#define DBX_DEBUGGING_INFO
+/* Generate SDB debugging information by default. */
-/* Omitting the frame pointer is a very good idea on the SH */
+#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-#define OPTIMIZATION_OPTIONS(OPTIMIZE) \
-{ \
- if (OPTIMIZE) \
- flag_omit_frame_pointer = 1; \
- if (OPTIMIZE==0)OPTIMIZE=1; \
-}
-\f
-/* Run-time compilation parameters selecting different hardware subsets. */
+#define SDB_DELIM ";"
-extern int target_flags;
-#define ISIZE_BIT 1
-#define FAST_BIT 2
-
-#define MAC_BIT 8
-#define RTL_BIT 16
-#define DT_BIT 32
-#define DALIGN_BIT 64
-#define SH0_BIT 128
-#define SH1_BIT 256
-#define SH2_BIT 512
-#define SH3_BIT 1024
-#define C_BIT 2048
-#define R_BIT (1<<12)
-#define SPACE_BIT (1<<13)
-
-/* Nonzero if we should generate code using type 0 insns */
-#define TARGET_SH0 (target_flags & SH0_BIT)
+#define CPP_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
-/* Nonzero if we should generate code using type 1 insns */
-#define TARGET_SH1 (target_flags & SH1_BIT)
+#define CPP_PREDEFINES "-D__sh__ -Acpu(sh) -Amachine(sh)"
-/* Nonzero if we should generate code using type 2 insns */
-#define TARGET_SH2 (target_flags & SH2_BIT)
+#define ASM_SPEC "%{ml:-little}"
-/* Nonzero if we should generate code using type 3 insns */
-#define TARGET_SH3 (target_flags & SH3_BIT)
+#define LINK_SPEC "%{ml:-m shl}"
-/* Nonzero if we should generate faster code rather than smaller code */
-#define TARGET_FASTCODE (target_flags & FAST_BIT)
+/* Show we can debug even without a frame pointer. */
+#define CAN_DEBUG_WITHOUT_FP
-/* Nonzero if we should generate faster code rather than smaller code */
-#define TARGET_SMALLCODE (target_flags & SPACE_BIT)
+#define CONDITIONAL_REGISTER_USAGE \
+ /* Hitachi saves and restores mac registers on call. */ \
+ if (TARGET_HITACHI) \
+ { \
+ call_used_regs[MACH_REG] = 0; \
+ call_used_regs[MACL_REG] = 0; \
+ }
+\f
+/* ??? Need to write documentation for all SH options and add it to the
+ invoke.texi file. */
-/* Nonzero if we should dump out instruction size info */
-#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
+/* Run-time compilation parameters selecting different hardware subsets. */
-/* Nonzero if we should try to generate mac instructions */
-#define TARGET_MAC (target_flags & MAC_BIT)
+extern int target_flags;
+#define ISIZE_BIT (1<<1)
+#define DALIGN_BIT (1<<6)
+#define SH0_BIT (1<<7)
+#define SH1_BIT (1<<8)
+#define SH2_BIT (1<<9)
+#define SH3_BIT (1<<10)
+#define SPACE_BIT (1<<13)
+#define BIGTABLE_BIT (1<<14)
+#define HITACHI_BIT (1<<22)
+#define PADSTRUCT_BIT (1<<28)
+#define LITTLE_ENDIAN_BIT (1<<29)
+
+/* Nonzero if we should dump out instruction size info. */
+#define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
-/* Nonzero if we should dump the rtl in the assembly file. */
-#define TARGET_DUMP_RTL (target_flags & RTL_BIT)
+/* Nonzero to align doubles on 64 bit boundaries. */
+#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
-/* Nonzero if we should dump the rtl somewher else. */
-#define TARGET_DUMP_R (target_flags & R_BIT)
+/* Nonzero if we should generate code using type 0 insns. */
+/* ??? Is there such a thing as SH0? If not, we should delete all
+ references to it. */
+#define TARGET_SH0 (target_flags & SH0_BIT)
-/* Nonzero to align doubles on 64 bit boundaries */
-#define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
+/* Nonzero if we should generate code using type 1 insns. */
+#define TARGET_SH1 (target_flags & SH1_BIT)
+/* Nonzero if we should generate code using type 2 insns. */
+#define TARGET_SH2 (target_flags & SH2_BIT)
-/* Nonzero if Combine dumping wanted */
-#define TARGET_CDUMP (target_flags & C_BIT)
-
-#define TARGET_SWITCHES \
-{ {"isize", ( ISIZE_BIT) },\
- {"space", ( SPACE_BIT) },\
- {"0", ( SH0_BIT) },\
- {"1", ( SH1_BIT) },\
- {"2", ( SH2_BIT) },\
- {"3", ( SH3_BIT) },\
- {"ac", ( MAC_BIT) },\
- {"dalign", ( DALIGN_BIT) },\
- {"c", ( C_BIT) },\
- {"r", ( RTL_BIT) },\
- {"R", ( R_BIT) },\
- {"", TARGET_DEFAULT} \
-}
+/* Nonzero if we should generate code using type 3 insns. */
+#define TARGET_SH3 (target_flags & SH3_BIT)
-#define TARGET_DEFAULT FAST_BIT
+/* Nonzero if we should generate smaller code rather than faster code. */
+#define TARGET_SMALLCODE (target_flags & SPACE_BIT)
-#define OVERRIDE_OPTIONS override_options();
+/* Nonzero to use long jump tables. */
+#define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
+
+/* Nonzero if using Hitachi's calling convention. */
+#define TARGET_HITACHI (target_flags & HITACHI_BIT)
+
+/* Nonzero if padding structures to a multiple of 4 bytes. This is
+ incompatible with Hitachi's compiler, and gives unusual structure layouts
+ which confuse programmers.
+ ??? This option is not useful, but is retained in case there are people
+ who are still relying on it. It may be deleted in the future. */
+#define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
+
+/* Nonzero if generating code for a little endian SH. */
+#define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
+
+#define TARGET_SWITCHES \
+{ {"0", SH0_BIT}, \
+ {"1", SH1_BIT}, \
+ {"2", SH2_BIT}, \
+ {"3", SH3_BIT|SH2_BIT}, \
+ {"3l", SH3_BIT|SH2_BIT|LITTLE_ENDIAN_BIT}, \
+ {"b", -LITTLE_ENDIAN_BIT}, \
+ {"bigtable", BIGTABLE_BIT}, \
+ {"dalign", DALIGN_BIT}, \
+ {"hitachi", HITACHI_BIT}, \
+ {"isize", ISIZE_BIT}, \
+ {"l", LITTLE_ENDIAN_BIT}, \
+ {"padstruct", PADSTRUCT_BIT}, \
+ {"space", SPACE_BIT}, \
+ {"", TARGET_DEFAULT} \
+}
+#define TARGET_DEFAULT (0)
+
+#define OVERRIDE_OPTIONS \
+do { \
+ sh_cpu = CPU_SH0; \
+ if (TARGET_SH1) \
+ sh_cpu = CPU_SH1; \
+ if (TARGET_SH2) \
+ sh_cpu = CPU_SH2; \
+ if (TARGET_SH3) \
+ sh_cpu = CPU_SH3; \
+ \
+ /* We *MUST* always define optimize since we *HAVE* to run \
+ shorten branches to get correct code. */ \
+ /* ??? This is obsolete, since now shorten branches is no \
+ longer required by the SH, and is always run once even \
+ when not optimizing. Changing this now might be \
+ confusing though. */ \
+ optimize = 1; \
+ flag_delayed_branch = 1; \
+ \
+ /* But never run scheduling before reload, since that can \
+ break global alloc, and generates slower code anyway due \
+ to the pressure on R0. */ \
+ flag_schedule_insns = 0; \
+} while (0)
\f
-/* Target machine storage Layout. */
+/* Target machine storage layout. */
/* Define to use software floating point emulator for REAL_ARITHMETIC and
- decimal <-> binary conversion. */
+ decimal <-> binary conversion. */
#define REAL_ARITHMETIC
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
+
#define BITS_BIG_ENDIAN 0
/* Define this if most significant byte of a word is the lowest numbered. */
-#define BYTES_BIG_ENDIAN 1
+#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
/* Define this if most significant word of a multiword number is the lowest
numbered. */
-#define WORDS_BIG_ENDIAN 1
+#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+
+/* Define this to set the endianness to use in libgcc2.c, which can
+ not depend on target_flags. */
+#if defined(__LITTLE_ENDIAN__)
+#define LIBGCC2_WORDS_BIG_ENDIAN 0
+#else
+#define LIBGCC2_WORDS_BIG_ENDIAN 1
+#endif
-/* Number of bits in an addressable storage unit */
+/* Number of bits in an addressable storage unit. */
#define BITS_PER_UNIT 8
/* Width in bits of a "word", which is the contents of a machine register.
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY 32
-/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 16
+/* Allocation boundary (in *bits*) for the code of a function.
+ 32 bit alignment is faster, because instructions are always fetched as a
+ pair from a longword boundary. */
+/* ??? Perhaps also define ASM_OUTPUT_ALIGN_CODE and/or ASM_OUTPUT_LOOP_ALIGN
+ so as to align jump targets and/or loops to 4 byte boundaries when not
+ optimizing for space? */
+#define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : 32)
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 32
/* The best alignment to use in cases where we have a choice. */
#define FASTEST_ALIGNMENT 32
-/* Every structures size must be a multiple of 32 bits. */
-#define STRUCTURE_SIZE_BOUNDARY 32
-
/* Make strings word-aligned so strcpy from constants will be faster. */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
((TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < FASTEST_ALIGNMENT) \
- ? FASTEST_ALIGNMENT : (ALIGN))
+ ? FASTEST_ALIGNMENT : (ALIGN))
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
&& (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+/* Number of bits which any structure or union's size must be a
+ multiple of. Each structure or union's size is rounded up to a
+ multiple of this. */
+#define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
+
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
#define STRICT_ALIGNMENT 1
-
\f
/* Standard register usage. */
-/* Register allocation for our first guess
+/* Register allocation for the Hitachi calling convention:
- r0-r3 scratch
- r4-r7 args in and out
- r8-r12 call saved
- r13 assembler temp
- r14 frame pointer
+ r0 arg return
+ r1..r3 scratch
+ r4..r7 args in
+ r8..r13 call saved
+ r14 frame pointer/call saved
r15 stack pointer
ap arg pointer (doesn't really exist, always eliminated)
pr subroutine return address
t t bit
- mach multiply/accumulate result
- macl
-*/
+ mach multiply/accumulate result, high part
+ macl multiply/accumulate result, low part. */
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
from 0 to just below FIRST_PSEUDO_REGISTER.
All registers that the compiler knows about must be given numbers,
- even those that are not normally considered general registers.
-
- SH has 16 integer registers and 4 control registers + the arg
- pointer */
-
-#define FIRST_PSEUDO_REGISTER 22
+ even those that are not normally considered general registers. */
+#define AP_REG 16
#define PR_REG 17
#define T_REG 18
#define GBR_REG 19
#define MACH_REG 20
#define MACL_REG 21
+#define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
+#define FIRST_PSEUDO_REGISTER 22
/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator. */
- /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap pr t gbr mh ml */
-#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1}
+ and are not available for the register allocator.
+
+ Mach register is fixed 'cause it's only 10 bits wide for SH1.
+ It is 32 bits wide for SH2. */
+
+#define FIXED_REGISTERS \
+ { 0, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 1, \
+ 1, 1, 1, 1, \
+ 1, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
- /* r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ap pr t gbr mh ml */
-#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1}
+#define CALL_USED_REGISTERS \
+ { 1, 1, 1, 1, \
+ 1, 1, 1, 1, \
+ 0, 0, 0, 0, \
+ 0, 0, 0, 1, \
+ 1, 0, 1, 1, \
+ 1, 1}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the SH regs are UNITS_PER_WORD bits wide; */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
+ On the SH regs are UNITS_PER_WORD bits wide. */
+
+#define HARD_REGNO_NREGS(REGNO, MODE) \
(((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
- We may keep double values in even registers */
+ We can allow any mode in any general register. The special registers
+ only allow SImode. Don't allow any mode in the PR. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- ((TARGET_ALIGN_DOUBLE && GET_MODE_SIZE(MODE) > 4) ? (((REGNO)&1)==0) : 1)
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ (SPECIAL_REG (REGNO) ? (MODE) == SImode \
+ : (REGNO) == PR_REG ? 0 \
+ : 1)
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
Zero means the frame pointer need not be set up (and parms may be accessed
via the stack pointer) in functions that seem suitable. */
-
-#define FRAME_POINTER_REQUIRED (get_frame_size() > 1000)
+#define FRAME_POINTER_REQUIRED 0
/* Definitions for register eliminations.
- We have two registers that can be eliminated on the m88k. First, the
+ We have two registers that can be eliminated on the SH. First, the
frame pointer register can often be eliminated in favor of the stack
pointer register. Secondly, the argument pointer register can always be
eliminated; it is replaced with either the stack or frame pointer. */
/* Register in which the static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 13
-/* The register in which a struct value address is passed */
+/* The register in which a struct value address is passed. */
+
+#define STRUCT_VALUE_REGNUM 2
+
+/* If the structure value address is not passed in a register, define
+ `STRUCT_VALUE' as an expression returning an RTX for the place
+ where the address is passed. If it returns 0, the address is
+ passed as an "invisible" first argument. */
-#define STRUCT_VALUE_REGNUM 3
+/*#define STRUCT_VALUE ((rtx)0)*/
+/* Don't default to pcc-struct-return, because we have already specified
+ exactly how to return structures in the RETURN_IN_MEMORY macro. */
+#define DEFAULT_PCC_STRUCT_RETURN 0
\f
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
For any two classes, it is very desirable that there be another
class that represents their union. */
-/* The SH has two sorts of general registers, R0 and the rest. R0 can
+/* The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the
- Procedure Return Register and the Multipy Accumulate Registers */
+ Procedure Return Register and the Multiply Accumulate Registers. */
enum reg_class
{
NO_REGS,
R0_REGS,
- GENERAL_REGS,
PR_REGS,
T_REGS,
MAC_REGS,
+ GENERAL_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
-/* Give names of register classes as strings for dump file. */
-#define REG_CLASS_NAMES \
+/* Give names of register classes as strings for dump file. */
+#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
"R0_REGS", \
- "GENERAL_REGS", \
"PR_REGS", \
"T_REGS", \
"MAC_REGS", \
+ "GENERAL_REGS", \
"ALL_REGS", \
}
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS \
+#define REG_CLASS_CONTENTS \
{ \
0x000000, /* NO_REGS */ \
0x000001, /* R0_REGS */ \
- 0x01FFFF, /* GENERAL_REGS */ \
0x020000, /* PR_REGS */ \
0x040000, /* T_REGS */ \
0x300000, /* MAC_REGS */ \
+ 0x01FFFF, /* GENERAL_REGS */ \
0x37FFFF /* ALL_REGS */ \
}
extern int regno_reg_class[];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[REGNO]
+/* When defined, the compiler allows registers explicitly used in the
+ rtl to be used as spill registers but prevents the compiler from
+ extending the lifetime of these registers. */
+
+#define SMALL_REGISTER_CLASSES
+
/* The order in which register should be allocated. */
-#define REG_ALLOC_ORDER \
- { 1,2,3,7,4,5,6,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21}
+#define REG_ALLOC_ORDER \
+ { 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14,15,16,17,18,19,20,21 }
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS R0_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Get reg_class from a letter such as appears in the machine
- description. */
+/* Get reg_class from a letter such as appears in the machine
+ description. */
extern enum reg_class reg_class_from_letter[];
#define REG_CLASS_FROM_LETTER(C) \
( (C) >= 'a' && (C) <= 'z' ? reg_class_from_letter[(C)-'a'] : NO_REGS )
-
-
+\f
/* The letters I, J, K, L and M in a register constraint string
can be used to stand for particular ranges of immediate operands.
This macro defines what the ranges are.
C is the letter, and VALUE is a constant value.
Return 1 if VALUE is in the range specified by C.
I: arithmetic operand -127..128, as used in add, sub, etc
+ K: shift operand 1,2,8 or 16
L: logical operand 0..255, as used in and, or, etc.
M: constant 1
- K: shift operand 1,2,8 or 16 */
-
+ N: constant 0 */
#define CONST_OK_FOR_I(VALUE) (((int)(VALUE))>= -128 && ((int)(VALUE)) <= 127)
+#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
#define CONST_OK_FOR_L(VALUE) (((int)(VALUE))>= 0 && ((int)(VALUE)) <= 255)
#define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
-#define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
- : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
- : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
- : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
+#define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
+ ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \
+ : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \
+ : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \
+ : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
+ : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
: 0)
/* Similar, but for floating constants, and defining letters G and H.
Here VALUE is the CONST_DOUBLE rtx itself. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? CONST_OK_FOR_I (CONST_DOUBLE_HIGH (VALUE)) \
- && CONST_OK_FOR_I (CONST_DOUBLE_LOW (VALUE)) \
- : 0)
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
in some cases it is preferable to use a more restrictive class. */
-#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
-
-/* Return the register class of a scratch register needed to copy IN into
- or out of a register in CLASS in MODE. If it can be done directly,
- NO_REGS is returned. */
-
-#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
+#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
/* Return the maximum number of consecutive registers
- needed to represent mode MODE in a register of class CLASS.
+ needed to represent mode MODE in a register of class CLASS.
- On SH this is the size of MODE in words */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
+ On SH this is the size of MODE in words. */
+#define CLASS_MAX_NREGS(CLASS, MODE) \
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-
\f
/* Stack layout; function entry, exit and calling. */
-/* Define the number of register that can hold parameters.
- These two macros are used only in other macro definitions below. */
+/* Define the number of registers that can hold parameters.
+ These three macros are used only in other macro definitions below. */
#define NPARM_REGS 4
#define FIRST_PARM_REG 4
-#define FIRST_RET_REG 4
+#define FIRST_RET_REG 0
/* Define this if pushing a word on the stack
makes the stack pointer a smaller address. */
-#define STACK_GROWS_DOWNWARD
-
-/* Define this if the nominal address of the stack frame
- is at the high-address end of the local variables;
- that is, each additional local variable allocated
- goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
-
-/* Offset within stack frame to start allocating local variables at.
- If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
- first local allocated. Otherwise, it is the offset to the BEGINNING
- of the first local allocated. */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this macro if the addresses of local variable slots are at
+ negative offsets from the frame pointer.
+
+ The SH only has positive indexes, so grow the frame up. */
+/* #define FRAME_GROWS_DOWNWARD */
+
+/* Offset from the frame pointer to the first local variable slot to
+ be allocated. */
#define STARTING_FRAME_OFFSET 0
/* If we generate an insn to push BYTES bytes,
/* Value is the number of byte of arguments automatically
popped when returning from a subroutine call.
+ FUNDECL is the declaration node of the function (as a tree),
FUNTYPE is the data type of the function (as a tree),
or for a library call it is an identifier node for the subroutine name.
SIZE is the number of bytes of arguments passed on the stack.
On the SH, the caller does not pop any of its arguments that were passed
on the stack. */
-#define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
/* Define how to find the value returned by a function.
VALTYPE is the data type of the value (as a tree).
If the precise function being called is known, FUNC is its FUNCTION_DECL;
otherwise, FUNC is 0. */
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
+
+#define FUNCTION_VALUE(VALTYPE, FUNC) \
+ gen_rtx (REG, TYPE_MODE (VALTYPE), FIRST_RET_REG)
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
-#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, MODE, FIRST_RET_REG)
+#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, FIRST_RET_REG)
/* 1 if N is a possible register number for a function value.
- On the SH, only r4 can return results. */
-#define FUNCTION_VALUE_REGNO_P(REGNO) \
- ((REGNO) == FIRST_RET_REG)
+ On the SH, only r0 can return results. */
+#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == FIRST_RET_REG)
-/* 1 if N is a possible register number for function argument passing.*/
+/* 1 if N is a possible register number for function argument passing. */
-#define FUNCTION_ARG_REGNO_P(REGNO) \
+#define FUNCTION_ARG_REGNO_P(REGNO) \
((REGNO) >= FIRST_PARM_REG && (REGNO) < (NPARM_REGS + FIRST_PARM_REG))
-
-
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
#define CUMULATIVE_ARGS int
-#define ROUND_ADVANCE(SIZE) \
+#define ROUND_ADVANCE(SIZE) \
((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* Round a register number up to a proper boundary for an arg of mode
- MODE.
-
- We round to an even reg for things larger than a word */
+/* Round a register number up to a proper boundary for an arg of mode
+ MODE.
+
+ The SH doesn't care about double alignment, so we only
+ round doubles to even regs when asked to explicitly. */
#define ROUND_REG(X, MODE) \
((TARGET_ALIGN_DOUBLE \
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
? ((X) + ((X) & 1)) : (X))
-
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0.
On SH, the offset always starts at 0: the first parm reg is always
the same reg. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME) \
((CUM) = 0)
/* Update the data in CUM to advance over an argument
NPARM_REGS words is at least partially passed in a register unless
its data type forbids. */
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
- (NAMED && ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
- && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
- && ((TYPE)==0 || (MODE) != BLKmode \
- || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
- ? gen_rtx (REG, (MODE), \
- (FIRST_PARM_REG + ROUND_REG ((CUM), (MODE)))) \
- : 0)
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+ sh_function_arg (CUM, MODE, TYPE, NAMED)
+
+extern struct rtx_def *sh_function_arg();
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
For args passed entirely in registers or entirely in memory, zero.
- Any arg that starts in the first NPARM_REGS regs but won't entirely
- fit in them needs partial registers on the SH. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
- ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
- && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
- && ((TYPE)==0 || (MODE) != BLKmode \
- || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
- && (ROUND_REG ((CUM), (MODE)) \
- + ((MODE) == BLKmode \
- ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
- : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
- ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
- : 0)
+
+ We sometimes split args. */
+
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+ sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
extern int current_function_anonymous_args;
/* Perform any needed actions needed for a function that is receiving a
- variable number of arguments. */
+ variable number of arguments. */
#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
current_function_anonymous_args = 1;
-
-/* Call the function profiler with a given profile label. */
+/* Call the function profiler with a given profile label. */
#define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
fprintf(STREAM, " .long LP%d\n", (LABELNO)); \
}
-
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
No definition is equivalent to always zero. */
-#define EXIT_IGNORE_STACK 0
+#define EXIT_IGNORE_STACK 1
-/* Generate the assembly code for function exit
- Just dump out any accumulated constant table.*/
+/* Generate the assembly code for function exit
+ Just dump out any accumulated constant table. */
-#define FUNCTION_EPILOGUE(STREAM, SIZE) \
- dump_constants(0);
+#define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue (STREAM, SIZE)
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
- On the SH, the trapoline looks like
+ On the SH, the trampoline looks like
1 0000 D301 mov.l l1,r3
2 0002 DD02 mov.l l2,r13
3 0004 4D2B jmp @r13
4 0006 200B or r0,r0
5 0008 00000000 l1: .long function
- 6 000c 00000000 l2: .long area
-*/
+ 6 000c 00000000 l2: .long area */
#define TRAMPOLINE_TEMPLATE(FILE) \
{ \
fprintf ((FILE), " .word 0xd301\n"); \
fprintf ((FILE), " .word 0xdd02\n"); \
- fprintf ((FILE), " .word 0x4d2b\n"); \
+ fprintf ((FILE), " .word 0x4d2b\n"); \
fprintf ((FILE), " .word 0x200b\n"); \
fprintf ((FILE), " .long 0\n"); \
fprintf ((FILE), " .long 0\n"); \
FNADDR is an RTX for the address of the function's pure code.
CXT is an RTX for the static chain value for the function. */
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 8)), \
(CXT)); \
emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 12)), \
(FNADDR)); \
}
-
\f
/* Addressing modes, and classification of registers for them. */
-
-/*#define HAVE_POST_INCREMENT 1*/
+#define HAVE_POST_INCREMENT 1
/*#define HAVE_PRE_INCREMENT 1*/
/*#define HAVE_POST_DECREMENT 1*/
-/*#define HAVE_PRE_DECREMENT 1*/
+#define HAVE_PRE_DECREMENT 1
/* Macros to check register numbers against specific register classes. */
They give nonzero only if REGNO is a hard reg of the suitable class
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
- has been allocated, which happens in local-alloc.c.
+ has been allocated, which happens in local-alloc.c. */
-*/
-#define REGNO_OK_FOR_BASE_P(REGNO) \
+#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+ ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
-#define REGNO_OK_FOR_INDEX_P(REGNO) ((REGNO)==0)
-
-/* Maximum number of registers that can appear in a valid memory
- address. */
+/* Maximum number of registers that can appear in a valid memory
+ address. */
-#define MAX_REGS_PER_ADDRESS 4
+#define MAX_REGS_PER_ADDRESS 2
/* Recognize any constant value that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF)
+#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
+/* Nonzero if the constant value X is a legitimate general operand. */
- On the SH, allow anything but a double */
-
-#define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
+/* ??? Should modify this to accept CONST_DOUBLE, and then modify the
+ constant pool table code to fix loads of CONST_DOUBLEs. If that doesn't
+ work well, then we can at least handle simple CONST_DOUBLEs here
+ such as 0.0. */
+#define LEGITIMATE_CONSTANT_P(X) (GET_CODE(X) != CONST_DOUBLE)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
them unless they have been allocated suitable hard regs.
The symbol REG_OK_STRICT causes the latter definition to be used. */
+#define MODE_DISP_OK_4(X,MODE) ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<64) && (!(INTVAL(X) &3)))
+#define MODE_DISP_OK_8(X,MODE) ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) && (!(INTVAL(X) &3)))
+
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
- (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+ (REGNO (X) <= 16 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_INDEX_P(X) \
- (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
-
-#define REG_OK_FOR_PRE_POST_P(X) \
- (REGNO (X) <= 16)
+ (REGNO (X) == 0 || REGNO(X) >= FIRST_PSEUDO_REGISTER)
#else
/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) \
+#define REG_OK_FOR_BASE_P(X) \
REGNO_OK_FOR_BASE_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) \
+#define REG_OK_FOR_INDEX_P(X) \
REGNO_OK_FOR_INDEX_P (REGNO (X))
-#define REG_OK_FOR_PRE_POST_P(X) \
- (REGNO (X) <= 16 || (unsigned) reg_renumber[REGNO (X)] <=16)
#endif
+
+/* The 'Q' constraint is a pc relative load operand. */
+#define EXTRA_CONSTRAINT_Q(OP) \
+ (GET_CODE (OP) == MEM && \
+ ((GET_CODE (XEXP (OP, 0)) == LABEL_REF) \
+ || (GET_CODE (XEXP (OP, 0)) == CONST \
+ && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
+ && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == LABEL_REF \
+ && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT)))
+
+#define EXTRA_CONSTRAINT(OP, C) \
+ ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
+ : 0)
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
-#define BASE_REGISTER_RTX_P(X) \
- (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))
-
-#define INDEX_REGISTER_RTX_P(X) \
- (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))
+#define BASE_REGISTER_RTX_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+#define INDEX_REGISTER_RTX_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
/* Jump to LABEL if X is a valid address RTX. This must also take
REG_OK_STRICT into account when deciding about valid registers, but it uses
- the above macros so we are in luck.
-
+ the above macros so we are in luck.
+
Allow REG
REG+disp
REG+r0
REG++
- --REG
-*/
+ --REG */
-/* The SH allows a displacement in a QI or HI amode, but only when the
+/* The SH allows a displacement in a QI or HI amode, but only when the
other operand is R0. GCC doesn't handle this very well, so we forgo
all of that.
- A legitimate index for a QI or HI is 0, SI and above can be any
- number 0..63 */
-
-#define GO_IF_LEGITIMATE_INDEX(MODE, REGNO, OP, LABEL) \
- do { \
- if (GET_CODE (OP) == CONST_INT) \
- { \
- if (0&&GET_MODE_SIZE (MODE) == 2 && ((unsigned)INTVAL(OP)) <=30)\
- goto LABEL; \
- if (0&&GET_MODE_SIZE (MODE) == 1 && ((unsigned)INTVAL(OP)) <=15)\
- goto LABEL; \
- if (GET_MODE_SIZE (MODE) >=4 \
- && ((unsigned)INTVAL(OP)) < 64) \
- goto LABEL; \
- } \
- } while(0)
+ A legitimate index for a QI or HI is 0, SI can be any number 0..63,
+ DI can be any number 0..60. */
+#define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
+ do { \
+ if (GET_CODE (OP) == CONST_INT) \
+ { \
+ if (MODE_DISP_OK_4 (OP, MODE)) goto LABEL; \
+ if (MODE_DISP_OK_8 (OP, MODE)) goto LABEL; \
+ } \
+ } while(0)
-#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
-{ \
- if (BASE_REGISTER_RTX_P (X)) \
- goto LABEL; \
- else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
- goto LABEL; \
- else if (GET_CODE (X) == PLUS || GET_CODE(X) == LO_SUM) \
- { \
- rtx xop0 = XEXP(X,0); \
- rtx xop1 = XEXP(X,1); \
- if (GET_MODE_SIZE(MODE) >= 4 && BASE_REGISTER_RTX_P (xop0)) \
- GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
- if (GET_MODE_SIZE(MODE) >= 4 && BASE_REGISTER_RTX_P (xop1)) \
- GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
- if (GET_MODE_SIZE(MODE)<=4) { \
- if(BASE_REGISTER_RTX_P(xop1) && \
- INDEX_REGISTER_RTX_P(xop0)) goto LABEL; \
- if(INDEX_REGISTER_RTX_P(xop1) && \
- BASE_REGISTER_RTX_P(xop0)) goto LABEL; \
- } \
- } \
- else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_PRE_POST_P (XEXP (X, 0))) \
- goto LABEL; \
-}
-
-\f
-/* Try machine-dependent ways of modifying an illegitimate address
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
+{ \
+ if (BASE_REGISTER_RTX_P (X)) \
+ goto LABEL; \
+ else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
+ && BASE_REGISTER_RTX_P (XEXP (X, 0))) \
+ goto LABEL; \
+ else if (GET_CODE (X) == PLUS) \
+ { \
+ rtx xop0 = XEXP (X, 0); \
+ rtx xop1 = XEXP (X, 1); \
+ if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
+ GO_IF_LEGITIMATE_INDEX (MODE, xop1, LABEL); \
+ if (GET_MODE_SIZE (MODE) <= 4) \
+ { \
+ if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
+ goto LABEL; \
+ if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
+ goto LABEL; \
+ } \
+ } \
+}
+\f
+/* Try machine-dependent ways of modifying an illegitimate address
to be legitimate. If we find one, return the new, valid address.
This macro is used in only one place: `memory_address' in explow.c.
GO_IF_LEGITIMATE_ADDRESS.
It is always safe for this macro to do nothing. It exists to recognize
- opportunities to optimize the output.
+ opportunities to optimize the output. */
- On the SH we don't try anything */
-
-#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) ;
+#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) ;
/* Go to LABEL if ADDR (a legitimate address expression)
has an effect that depends on the machine mode it is used for. */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
{ \
- if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC \
- || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC) \
+ if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
goto LABEL; \
}
\f
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE SImode
+#define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
/* Define this if the tablejump instruction expects the table
to contain offsets from the address of the table.
Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE */
+#define CASE_VECTOR_PC_RELATIVE
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* This is the kind of divide that is easiest to do in the general case. */
#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-/* 'char' is signed by default */
+/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
/* The type of size_t unsigned int. */
#define SIZE_TYPE "unsigned int"
+#define WCHAR_TYPE "short unsigned int"
+#define WCHAR_TYPE_SIZE 16
+
/* Don't cse the address of the function being compiled. */
-#define NO_RECURSIVE_FUNCTION_CSE 1
+/*#define NO_RECURSIVE_FUNCTION_CSE 1*/
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Define this if zero-extension is slow (more than one real instruction).
- On the SH, it's only one instruction */
+ On the SH, it's only one instruction. */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define STORE_FLAG_VALUE 1
/* Immediate shift counts are truncated by the output routines (or was it
- the assembler?). Shift counts in a register are truncated by ARM. Note
+ the assembler?). Shift counts in a register are truncated by SH. Note
that the native compiler puts too large (> 32) immediate shift counts
- into a register and shifts by the register, letting the ARM decide what
+ into a register and shifts by the register, letting the SH decide what
to do instead of doing that itself. */
+/* ??? This is defined, but the library routines in lib1funcs.asm do not
+ truncate the shift count. This may result in incorrect results for
+ unusual cases. Truncating the shift counts in the library routines would
+ make them faster. However, the SH3 has hardware shifts that do not
+ truncate, so it appears that we need to leave this undefined for correct
+ SH3 code. We can still using truncation in the library routines though to
+ make them faster. */
#define SHIFT_COUNT_TRUNCATED 1
-/* We have the vprintf function. */
-#define HAVE_VPRINTF 1
-
/* All integers have the same format so truncation is easy. */
#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
/* Chars and shorts should be passed as ints. */
#define PROMOTE_PROTOTYPES 1
-/* The machine modes of pointers and functions */
+/* The machine modes of pointers and functions. */
#define Pmode SImode
#define FUNCTION_MODE Pmode
-/* The structure type of the machine dependent info field of insns
- No uses for this yet. */
-/* #define INSN_MACHINE_INFO struct machine_info */
-
/* The relative costs of various types of constants. Note that cse.c defines
REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
-#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
+#define CONST_COSTS(RTX, CODE, OUTER_CODE) \
case CONST_INT: \
- if (CONST_OK_FOR_I (INTVAL(RTX))) \
+ if (INTVAL (RTX) == 0) \
+ return 0; \
+ else if (CONST_OK_FOR_I (INTVAL (RTX))) \
+ return 1; \
+ else if ((OUTER_CODE == AND || OUTER_CODE == IOR || OUTER_CODE == XOR) \
+ && CONST_OK_FOR_L (INTVAL (RTX))) \
return 1; \
else \
return 8; \
return 10;
#define RTX_COSTS(X, CODE, OUTER_CODE) \
+ case AND: \
+ return COSTS_N_INSNS (andcosts (X)); \
case MULT: \
return COSTS_N_INSNS (multcosts (X)); \
case ASHIFT: \
case ASHIFTRT: \
- case LSHIFT: \
+ case LSHIFTRT: \
return COSTS_N_INSNS (shiftcosts (X)) ; \
case DIV: \
case UDIV: \
case MOD: \
case UMOD: \
- return COSTS_N_INSNS (100); \
+ return COSTS_N_INSNS (20); \
case FLOAT: \
case FIX: \
return 100;
+/* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
+ are actually function calls with some special constraints on arguments
+ and register usage.
+
+ These macros tell reorg that the references to arguments and
+ register clobbers for insns of type sfunc do not appear to happen
+ until after the millicode call. This allows reorg to put insns
+ which set the argument registers into the delay slot of the millicode
+ call -- thus they act more like traditional CALL_INSNs.
+
+ get_attr_type will try to recognize the given insn, so make sure to
+ filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
+ in particular. */
+
+#define INSN_SETS_ARE_DELAYED(X) \
+ ((GET_CODE (X) == INSN \
+ && GET_CODE (PATTERN (X)) != SEQUENCE \
+ && GET_CODE (PATTERN (X)) != USE \
+ && GET_CODE (PATTERN (X)) != CLOBBER \
+ && get_attr_type (X) == TYPE_SFUNC))
+
+#define INSN_REFERENCES_ARE_DELAYED(X) \
+ ((GET_CODE (X) == INSN \
+ && GET_CODE (PATTERN (X)) != SEQUENCE \
+ && GET_CODE (PATTERN (X)) != USE \
+ && GET_CODE (PATTERN (X)) != CLOBBER \
+ && get_attr_type (X) == TYPE_SFUNC))
+
/* Compute extra cost of moving data between one register class
- and another.
+ and another.
On the SH it is hard to move into the T reg, but simple to load
- from it.
-*/
+ from it. */
-#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
- ((DSTCLASS == T_REGS) ? 10 : 1)
+#define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
+ (((DSTCLASS == T_REGS) || (DSTCLASS == PR_REG)) ? 10 : 1)
+
+/* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
+ would be so that people would slow memory systems could generate
+ different code that does fewer memory accesses. */
\f
-/* Assembler output control */
-
-/* The text to go at the start of the assembler file */
-#define ASM_FILE_START(STREAM) \
- output_file_start (STREAM, f_options, sizeof f_options / sizeof f_options[0], \
- W_options, sizeof W_options / sizeof W_options[0]);
-
-
-#define ASM_FILE_END(STREAM) \
- dump_constants(0);
-
-#define ASM_APP_ON ""
-#define ASM_APP_OFF ""
-
-#define FILE_ASM_OP "\t.file\n"
-#define IDENT_ASM_OP "\t.ident\n"
-
-
-/* Switch to the text or data segment. */
-#define TEXT_SECTION_ASM_OP "\t.text"
-#define DATA_SECTION_ASM_OP "\t.data"
-#define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
-#define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
-
-#define EXTRA_SECTIONS in_ctors, in_dtors
-#define EXTRA_SECTION_FUNCTIONS \
-void \
-ctors_section() \
-{ \
- if (in_section != in_ctors) \
- { \
- fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
- in_section = in_ctors; \
- } \
-} \
-void \
-dtors_section() \
-{ \
- if (in_section != in_dtors) \
- { \
- fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
- in_section = in_dtors; \
- } \
-}
-
-#define ASM_OUTPUT_SECTION(file, nam) \
- do { fprintf (file, "\t.section\t%s\n", nam); } while(0)
-
-#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
+/* Assembler output control. */
+
+/* The text to go at the start of the assembler file. */
+#define ASM_FILE_START(STREAM) \
+ output_file_start (STREAM, f_options, \
+ sizeof f_options / sizeof f_options[0], \
+ W_options, sizeof W_options / sizeof W_options[0]);
+
+#define ASM_FILE_END(STREAM)
+
+#define ASM_APP_ON ""
+#define ASM_APP_OFF ""
+#define FILE_ASM_OP "\t.file\n"
+#define IDENT_ASM_OP "\t.ident\n"
+
+/* How to change between sections. */
+
+#define TEXT_SECTION_ASM_OP "\t.text"
+#define DATA_SECTION_ASM_OP "\t.data"
+#define CTORS_SECTION_ASM_OP "\t.section\t.ctors\n"
+#define DTORS_SECTION_ASM_OP "\t.section\t.dtors\n"
+#define INIT_SECTION_ASM_OP "\t.section\t.init\n"
+#define EXTRA_SECTIONS in_ctors, in_dtors
+#define EXTRA_SECTION_FUNCTIONS \
+void \
+ctors_section() \
+{ \
+ if (in_section != in_ctors) \
+ { \
+ fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \
+ in_section = in_ctors; \
+ } \
+} \
+void \
+dtors_section() \
+{ \
+ if (in_section != in_dtors) \
+ { \
+ fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \
+ in_section = in_dtors; \
+ } \
+}
+
+/* A C statement to output something to the assembler file to switch to section
+ NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
+ NULL_TREE. Some target formats do not support arbitrary sections. Do not
+ define this macro in such cases. */
+
+#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
+ do { fprintf (FILE, ".section\t%s\n", NAME); } while (0)
+
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
do { ctors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
-#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { dtors_section(); fprintf(FILE,"\t.long\t_%s\n", NAME); } while (0)
+#undef DO_GLOBAL_CTORS_BODY
-#undef DO_GLOBAL_CTORS_BODY
#define DO_GLOBAL_CTORS_BODY \
{ \
typedef (*pfunc)(); \
extern pfunc __ctors[]; \
extern pfunc __ctors_end[]; \
pfunc *p; \
- for (p = __ctors; p < __ctors_end; p++) \
+ for (p = __ctors_end; p > __ctors; ) \
{ \
- (*p)(); \
+ (*--p)(); \
} \
-}
+}
-#undef DO_GLOBAL_DTORS_BODY
-#define DO_GLOBAL_DTORS_BODY \
+#undef DO_GLOBAL_DTORS_BODY
+#define DO_GLOBAL_DTORS_BODY \
{ \
typedef (*pfunc)(); \
extern pfunc __dtors[]; \
{ \
(*p)(); \
} \
-}
-
-
+}
#define ASM_OUTPUT_REG_PUSH(file, v) \
fprintf (file, "\tmov.l r%s,-@r15\n", v);
#define ASM_OUTPUT_REG_POP(file, v) \
fprintf (file, "\tmov.l @r15+,r%s\n", v);
-
-
/* The assembler's names for the registers. RFP need not always be used as
the Real framepointer; it can also be used as a normal general register.
Note that the name `fp' is horribly misleading since `fp' is in fact only
"ap", "pr", "t", "gbr", "mach","macl" \
}
-/* DBX register number for a given compiler register number */
+/* DBX register number for a given compiler register number. */
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
/* Output a label definition. */
-#define ASM_OUTPUT_LABEL(FILE,NAME) \
+#define ASM_OUTPUT_LABEL(FILE,NAME) \
do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-
/* This is how to output an assembler line
that says to advance the location counter
to a multiple of 2**LOG bytes. */
ASM_OUTPUT_LABEL(STREAM, NAME)
/* Output a globalising directive for a label. */
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
- (fprintf (STREAM, "\t.global\t"), \
- assemble_name (STREAM, NAME), \
- fputc ('\n',STREAM)) \
+#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
+ (fprintf (STREAM, "\t.global\t"), \
+ assemble_name (STREAM, NAME), \
+ fputc ('\n',STREAM))
/* Output a reference to a label. */
-#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
+#define ASM_OUTPUT_LABELREF(STREAM,NAME) \
fprintf (STREAM, "_%s", NAME)
/* Make an internal label into a string. */
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
+#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
sprintf (STRING, "*%s%d", PREFIX, NUM)
/* Output an internal label definition. */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
fprintf (FILE, "%s%d:\n", PREFIX, NUM)
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* Construct a private name. */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
- ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
+#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
+ ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)))
-/* Jump tables must be 32 bit aligned. */
+/* Jump tables must be 32 bit aligned, no matter the size of the element. */
#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \
- fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
+ fprintf (STREAM, "\t.align 2\n%s%d:\n", PREFIX, NUM);
-/* Output a relative address. Not needed since jump tables are absolute
- but we must define it anyway. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
- fputs ("- - - ASM_OUTPUT_ADDR_DIFF_ELT called!\n", STREAM)
+/* Output a relative address table. */
-/* Output an element of a dispatch table. */
-#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
- fprintf (STREAM, "\t.long\tL%d\n", VALUE)
+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,VALUE,REL) \
+ if (TARGET_BIGTABLE) \
+ fprintf (STREAM, "\t.long L%d-L%d\n", VALUE,REL); \
+ else \
+ fprintf (STREAM, "\t.word L%d-L%d\n", VALUE,REL); \
-/* Output various types of constants. */
+/* Output an absolute table element. */
+
+#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
+ if (TARGET_BIGTABLE) \
+ fprintf (STREAM, "\t.long L%d\n", VALUE); \
+ else \
+ fprintf (STREAM, "\t.word L%d\n", VALUE); \
+/* Output various types of constants. */
-/* This is how to output an assembler line defining a `double' */
+/* This is how to output an assembler line defining a `double'. */
#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
do { char dstr[30]; \
fprintf (FILE, "\t.double %s\n", dstr); \
} while (0)
-
/* This is how to output an assembler line defining a `float' constant. */
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
+#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
do { char dstr[30]; \
REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", dstr); \
fprintf (FILE, "\t.float %s\n", dstr); \
} while (0)
-
#define ASM_OUTPUT_INT(STREAM, EXP) \
(fprintf (STREAM, "\t.long\t"), \
output_addr_const (STREAM, (EXP)), \
- fputc ('\n', STREAM))
+ fputc ('\n', STREAM))
-#define ASM_OUTPUT_SHORT(STREAM, EXP) \
- (fprintf (STREAM, "\t.short\t"), \
- output_addr_const (STREAM, (EXP)), \
- fputc ('\n', STREAM))
+#define ASM_OUTPUT_SHORT(STREAM, EXP) \
+ (fprintf (STREAM, "\t.short\t"), \
+ output_addr_const (STREAM, (EXP)), \
+ fputc ('\n', STREAM))
#define ASM_OUTPUT_CHAR(STREAM, EXP) \
(fprintf (STREAM, "\t.byte\t"), \
/* This is how to output an assembler line
that says to advance the location counter by SIZE bytes. */
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
+#define ASM_OUTPUT_SKIP(FILE,SIZE) \
fprintf (FILE, "\t.space %d\n", (SIZE))
/* This says how to output an assembler line
to define a global common symbol. */
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
( fputs ("\t.comm ", (FILE)), \
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (SIZE)))
assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (SIZE)))
-
/* The assembler's parentheses characters. */
#define ASM_OPEN_PAREN "("
#define ASM_CLOSE_PAREN ")"
#define TARGET_FF 014
#define TARGET_CR 015
\f
-
/* Only perform branch elimination (by making instructions conditional) if
- we're optimising. Otherwise it's of no use anyway. */
-#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
- final_prescan_insn (INSN, OPVEC, NOPERANDS)
+ we're optimizing. Otherwise it's of no use anyway. */
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
+ final_prescan_insn (INSN, OPVEC, NOPERANDS)
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
#define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address (STREAM, X)
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
- ((CHAR)=='.' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '!')
-
+ ((CHAR)=='.' || (CHAR) == '#' || (CHAR)=='@')
\f
-/* Define the information needed to generate branch insns. This is stored
- from the compare operation. Note that we can't use "rtx" here since it
- hasn't been defined! */
-
extern struct rtx_def *sh_compare_op0;
extern struct rtx_def *sh_compare_op1;
extern struct rtx_def *prepare_scc_operands();
-extern enum attr_cpu sh_cpu; /* target cpu */
+/* Which processor to schedule for. The elements of the enumeration must
+ match exactly the cpu attribute in the sh.md file. */
+
+enum processor_type {
+ PROCESSOR_SH0,
+ PROCESSOR_SH1,
+ PROCESSOR_SH2,
+ PROCESSOR_SH3
+};
+
+#define sh_cpu_attr ((enum attr_cpu)sh_cpu)
+extern enum processor_type sh_cpu;
-/* Declare functions defined in sh.c and used in templates. */
+/* Declare functions defined in sh.c and used in templates. */
extern char *output_branch();
extern char *output_shift();
extern char *output_movedouble();
extern char *output_movepcrel();
+extern char *output_jump_label_table();
+extern char *output_far_jump();
+#define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
-#define ADJUST_INSN_LENGTH(insn, length) \
- adjust_insn_length (insn, insn_lengths)
+/* Generate calls to memcpy, memcmp and memset. */
+#define TARGET_MEM_FUNCTIONS
+#define HANDLE_PRAGMA(finput) return handle_pragma (finput)
+/* Set when processing a function with pragma interrupt turned on. */
+extern int pragma_interrupt;
+#define MOVE_RATIO (TARGET_SMALLCODE ? 2 : 16)
+\f
+/* Instructions with unfilled delay slots take up an extra two bytes for
+ the nop in the delay slot. */
+
+#define ADJUST_INSN_LENGTH(X, LENGTH) \
+ if (((GET_CODE (X) == INSN \
+ && GET_CODE (PATTERN (X)) != SEQUENCE \
+ && GET_CODE (PATTERN (X)) != USE \
+ && GET_CODE (PATTERN (X)) != CLOBBER) \
+ || GET_CODE (X) == CALL_INSN \
+ || (GET_CODE (X) == JUMP_INSN \
+ && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
+ && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
+ && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
+ LENGTH += 2;
+
+/* Enable a bug fix for the shorten_branches pass. */
+#define SHORTEN_WITH_ADJUST_INSN_LENGTH
+\f
+/* Define the codes that are matched by predicates in sh.c. */
+#define PREDICATE_CODES \
+ {"arith_reg_operand", {SUBREG, REG}}, \
+ {"arith_operand", {SUBREG, REG, CONST_INT}}, \
+ {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
+ {"logical_operand", {SUBREG, REG, CONST_INT}}, \
+ {"general_movsrc_operand", {SUBREG, REG, CONST_INT, MEM}}, \
+ {"general_movdst_operand", {SUBREG, REG, CONST_INT, MEM}},
+
+/* Define this macro if it is advisable to hold scalars in registers
+ in a wider mode than that declared by the program. In such cases,
+ the value is constrained to be within the bounds of the declared
+ type, but kept valid in the wider mode. The signedness of the
+ extension may differ from that of the type.
+
+ Leaving the unsignedp unchanged gives better code than always setting it
+ to 0. This is despite the fact that we have only signed char and short
+ load instructions. */
+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
+ if (GET_MODE_CLASS (MODE) == MODE_INT \
+ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
+ MODE = SImode;
+
+/* PROMOTE_FUNCTION_ARGS and PROMOTE_FUNCTION_RETURN appear to have no
+ effect, because all unprototyped char/shorts are already promoted to
+ int, and because PROMOTE_PROTOTYPES causes all prototypes char/shorts
+ to be promoted to it. */
+
+/* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
+ and poping arguments. However, we do have push/pop instructions, and
+ rather limited offsets (4 bits) in load/store instructions, so it isn't
+ clear if this would give better code. If implemented, should check for
+ compatibility problems. */
+
+/* ??? Define ADJUST_COSTS? */
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