2005-11-07 Paolo Bonzini <bonzini@gnu.org>

[pf3gnuchains/gcc-fork.git] / gcc / config / rs6000 / predicates.md

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index da813da..4ce00b0 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -271,59 +271,55 @@
 (define_predicate "easy_vector_constant"
   (match_code "const_vector")
 {
-  int cst, cst2;
-
-  if (!TARGET_ALTIVEC && !TARGET_SPE)
-    return 0;
-
-  if (zero_constant (op, mode)
-      && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
-         || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
-    return 1;
-
-  if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
-    return 0;
-
-  if (TARGET_SPE && mode == V1DImode)
-    return 0;
+  if (ALTIVEC_VECTOR_MODE (mode))
+    {
+      if (zero_constant (op, mode))
+        return true;
+      if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
+        return false;
 
-  cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
-  cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
-
-  /* Limit SPE vectors to 15 bits signed.  These we can generate with:
-       li r0, CONSTANT1
-       evmergelo r0, r0, r0
-       li r0, CONSTANT2
-
-     I don't know how efficient it would be to allow bigger constants,
-     considering we'll have an extra 'ori' for every 'li'.  I doubt 5
-     instructions is better than a 64-bit memory load, but I don't
-     have the e500 timing specs.  */
-  if (TARGET_SPE && mode == V2SImode
-      && cst  >= -0x7fff && cst <= 0x7fff
-      && cst2 >= -0x7fff && cst2 <= 0x7fff)
-    return 1;
+      return easy_altivec_constant (op, mode);
+    }
 
-  if (TARGET_ALTIVEC
-      && easy_vector_same (op, mode))
+  if (SPE_VECTOR_MODE (mode))
     {
-      cst = easy_vector_splat_const (cst, mode);
-      if (EASY_VECTOR_15_ADD_SELF (cst)
-         || EASY_VECTOR_15 (cst))
-       return 1;
+      int cst, cst2;
+      if (zero_constant (op, mode))
+       return true;
+      if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
+        return false;
+
+      /* Limit SPE vectors to 15 bits signed.  These we can generate with:
+          li r0, CONSTANT1
+          evmergelo r0, r0, r0
+          li r0, CONSTANT2
+
+        I don't know how efficient it would be to allow bigger constants,
+        considering we'll have an extra 'ori' for every 'li'.  I doubt 5
+        instructions is better than a 64-bit memory load, but I don't
+        have the e500 timing specs.  */
+      if (mode == V2SImode)
+       {
+         cst  = INTVAL (CONST_VECTOR_ELT (op, 0));
+         cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
+         return cst  >= -0x7fff && cst <= 0x7fff
+                && cst2 >= -0x7fff && cst2 <= 0x7fff;
+       }
     }
-  return 0;
+
+  return false;
 })
 
 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
 (define_predicate "easy_vector_constant_add_self"
   (and (match_code "const_vector")
        (and (match_test "TARGET_ALTIVEC")
-           (and (match_test "easy_vector_same (op, mode)")
-                (match_test "EASY_VECTOR_15_ADD_SELF
-                               (easy_vector_splat_const
-                                 (INTVAL (CONST_VECTOR_ELT (op, 0)),
-                                  mode))")))))
+           (match_test "easy_altivec_constant (op, mode)")))
+{
+  rtx last = CONST_VECTOR_ELT (op, GET_MODE_NUNITS (mode) - 1);
+  HOST_WIDE_INT val = (char) (INTVAL (last) & 255);
+  return EASY_VECTOR_15_ADD_SELF (val);
+})
 
 ;; Return 1 if operand is constant zero (scalars and vectors).
 (define_predicate "zero_constant"