/* Definitions of target machine for GNU compiler.
Matsushita MN10300 series
Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
- 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+ 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GCC.
} \
else if (TARGET_AM33) \
builtin_define ("__AM33__=1"); \
+ \
+ builtin_define (TARGET_ALLOW_LIW ? \
+ "__LIW__" : "__NO_LIW__");\
+ \
} \
while (0)
-extern GTY(()) int mn10300_unspec_int_label_counter;
-
-enum processor_type
-{
- PROCESSOR_MN10300,
- PROCESSOR_AM33,
- PROCESSOR_AM33_2,
- PROCESSOR_AM34
-};
+#ifndef MN10300_OPTS_H
+#include "config/mn10300/mn10300-opts.h"
+#endif
-extern enum processor_type mn10300_processor;
extern enum processor_type mn10300_tune_cpu;
#define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33)
#define PROCESSOR_DEFAULT PROCESSOR_MN10300
#endif
-/* Print subsidiary information on the compiler version in use. */
-
-#define TARGET_VERSION fprintf (stderr, " (MN10300)");
-
\f
/* Target machine storage layout */
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 0
+
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "long int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
\f
/* Standard register usage. */
#define LAST_EXTENDED_REGNUM 17
#define FIRST_FP_REGNUM 18
#define LAST_FP_REGNUM 49
-#define MDR_REGNUM 50
+/* #define MDR_REG 50 */
/* #define CC_REG 51 */
#define FIRST_ARGUMENT_REGNUM 0
and are not available for the register allocator. */
#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \
- , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
- , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 \
+ { 0, 0, 0, 0, /* data regs */ \
+ 0, 0, 0, 0, /* addr regs */ \
+ 1, /* arg reg */ \
+ 1, /* sp reg */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \
+ 0, 0, /* fp regs (18-19) */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \
+ 0, /* mdr reg */ \
+ 1 /* cc reg */ \
}
/* 1 for registers not available across function calls.
like. */
#define CALL_USED_REGISTERS \
- { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \
- , 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
- , 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+ { 1, 1, 0, 0, /* data regs */ \
+ 1, 1, 0, 0, /* addr regs */ \
+ 1, /* arg reg */ \
+ 1, /* sp reg */ \
+ 1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \
+ 1, 1, /* fp regs (18-19) */ \
+ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \
+ 1, /* mdr reg */ \
+ 1 /* cc reg */ \
}
/* Note: The definition of CALL_REALLY_USED_REGISTERS is not
#define REG_ALLOC_ORDER \
{ 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
, 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
- , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 51 \
+ , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \
}
/* Return number of consecutive hard regs needed starting at reg REGNO
enum reg_class
{
- NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
- DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
- EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
- SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
- FP_REGS, FP_ACC_REGS, CC_REGS,
- GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+ NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, SP_OR_ADDRESS_REGS,
+ EXTENDED_REGS, FP_REGS, FP_ACC_REGS, CC_REGS, MDR_REGS,
+ GENERAL_REGS, SP_OR_GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
-#define REG_CLASS_NAMES \
-{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
- "SP_REGS", "DATA_OR_ADDRESS_REGS", "SP_OR_ADDRESS_REGS", \
- "EXTENDED_REGS", \
- "DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
- "SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
- "FP_REGS", "FP_ACC_REGS", "CC_REGS", \
- "GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
+#define REG_CLASS_NAMES \
+{ "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \
+ "EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \
+ "GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
}
/* Define which registers fit in which classes.
{ 0x0000000f, 0 }, /* DATA_REGS */ \
{ 0x000001f0, 0 }, /* ADDRESS_REGS */ \
{ 0x00000200, 0 }, /* SP_REGS */ \
- { 0x000001ff, 0 }, /* DATA_OR_ADDRESS_REGS */ \
{ 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \
{ 0x0003fc00, 0 }, /* EXTENDED_REGS */ \
- { 0x0003fc0f, 0 }, /* DATA_OR_EXTENDED_REGS */ \
- { 0x0003fdf0, 0 }, /* ADDRESS_OR_EXTENDED_REGS */ \
- { 0x0003fe00, 0 }, /* SP_OR_EXTENDED_REGS */ \
- { 0x0003fff0, 0 }, /* SP_OR_ADDRESS_OR_EXTENDED_REGS */ \
{ 0xfffc0000, 0x3ffff },/* FP_REGS */ \
{ 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
{ 0x00000000, 0x80000 },/* CC_REGS */ \
+ { 0x00000000, 0x40000 },/* MDR_REGS */ \
{ 0x0003fdff, 0 }, /* GENERAL_REGS */ \
+ { 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \
{ 0xffffffff, 0xfffff } /* ALL_REGS */ \
}
-/* The following macro defines cover classes for Integrated Register
- Allocator. Cover classes is a set of non-intersected register
- classes covering all hard registers used for register allocation
- purpose. Any move between two registers of a cover class should be
- cheaper than load or store of the registers. The macro value is
- array of register classes with LIM_REG_CLASSES used as the end
- marker. */
-
-#define IRA_COVER_CLASSES \
-{ \
- GENERAL_REGS, FP_REGS, LIM_REG_CLASSES \
-}
-
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
(REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
(REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
(REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
+ (REGNO) == MDR_REG ? MDR_REGS : \
(REGNO) == CC_REG ? CC_REGS : \
NO_REGS)
/* The class value for index registers, and the one for base regs. */
-#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
-#define BASE_REG_CLASS SP_OR_ADDRESS_REGS
+#define INDEX_REG_CLASS \
+ (TARGET_AM33 ? GENERAL_REGS : DATA_REGS)
+#define BASE_REG_CLASS \
+ (TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS)
/* Macros to check register numbers against specific register classes. */
# define REG_STRICT 1
#endif
-# define REGNO_IN_RANGE_P(regno,min,max,strict) \
- (IN_RANGE ((regno), (min), (max)) \
- || ((strict) \
- ? (reg_renumber \
- && reg_renumber[(regno)] >= (min) \
- && reg_renumber[(regno)] <= (max)) \
- : (regno) >= FIRST_PSEUDO_REGISTER))
-
#define REGNO_DATA_P(regno, strict) \
- (REGNO_IN_RANGE_P ((regno), FIRST_DATA_REGNUM, LAST_DATA_REGNUM, \
- (strict)))
+ mn10300_regno_in_class_p (regno, DATA_REGS, strict)
#define REGNO_ADDRESS_P(regno, strict) \
- (REGNO_IN_RANGE_P ((regno), FIRST_ADDRESS_REGNUM, LAST_ADDRESS_REGNUM, \
- (strict)))
-#define REGNO_SP_P(regno, strict) \
- (REGNO_IN_RANGE_P ((regno), STACK_POINTER_REGNUM, STACK_POINTER_REGNUM, \
- (strict)))
+ mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
#define REGNO_EXTENDED_P(regno, strict) \
- (REGNO_IN_RANGE_P ((regno), FIRST_EXTENDED_REGNUM, LAST_EXTENDED_REGNUM, \
- (strict)))
-#define REGNO_AM33_P(regno, strict) \
- (REGNO_DATA_P ((regno), (strict)) || REGNO_ADDRESS_P ((regno), (strict)) \
- || REGNO_EXTENDED_P ((regno), (strict)))
-#define REGNO_FP_P(regno, strict) \
- (REGNO_IN_RANGE_P ((regno), FIRST_FP_REGNUM, LAST_FP_REGNUM, (strict)))
+ mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict)
+#define REGNO_GENERAL_P(regno, strict) \
+ mn10300_regno_in_class_p (regno, GENERAL_REGS, strict)
#define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \
- (REGNO_SP_P ((regno), (strict)) \
- || REGNO_ADDRESS_P ((regno), (strict)) \
- || REGNO_EXTENDED_P ((regno), (strict)))
+ mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict)
#define REGNO_OK_FOR_BASE_P(regno) \
(REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT))
#define REG_OK_FOR_BASE_P(X) \
(REGNO_OK_FOR_BASE_P (REGNO (X)))
#define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \
- (REGNO_SP_P ((regno), (strict)) || REGNO_ADDRESS_P ((regno), (strict)))
+ mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
#define REGNO_OK_FOR_BIT_BASE_P(regno) \
(REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT))
#define REG_OK_FOR_BIT_BASE_P(X) \
(REGNO_OK_FOR_BIT_BASE_P (REGNO (X)))
#define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \
- (REGNO_DATA_P ((regno), (strict)) || REGNO_EXTENDED_P ((regno), (strict)))
+ mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict)
#define REGNO_OK_FOR_INDEX_P(regno) \
(REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT))
#define REG_OK_FOR_INDEX_P(X) \
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
(!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
-#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
- mn10300_secondary_reload_class(CLASS,MODE,IN)
-
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
#define FIRST_PARM_OFFSET(FNDECL) 4
+/* But the CFA is at the arg pointer directly, not at the first argument. */
+#define ARG_POINTER_CFA_OFFSET(FNDECL) 0
+
#define ELIMINABLE_REGS \
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
/* Length in units of the trampoline for entering a nested function. */
-#define TRAMPOLINE_SIZE 0x1b
-
-#define TRAMPOLINE_ALIGNMENT 32
+#define TRAMPOLINE_SIZE 16
+#define TRAMPOLINE_ALIGNMENT 32
/* A C expression whose value is RTL representing the value of the return
address for the frame COUNT steps up from the current frame.
? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
: (rtx) 0)
-#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, MDR_REGNUM)
+/* The return address is saved both in the stack and in MDR. Using
+ the stack location is handiest for what unwinding needs. */
+#define INCOMING_RETURN_ADDR_RTX \
+ gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
\f
/* Maximum number of registers that can appear in a valid memory address. */
#define MAX_REGS_PER_ADDRESS 2
\f
-#define HAVE_POST_INCREMENT (TARGET_AM33)
+/* We have post-increments. */
+#define HAVE_POST_INCREMENT TARGET_AM33
+#define HAVE_POST_MODIFY_DISP TARGET_AM33
+
+/* ... But we don't want to use them for block moves. Small offsets are
+ just as effective, at least for inline block move sizes, and appears
+ to produce cleaner code. */
+#define USE_LOAD_POST_INCREMENT(M) 0
+#define USE_STORE_POST_INCREMENT(M) 0
/* Accept either REG or SUBREG where a register is valid. */
&& REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \
(strict))))
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
+do { \
+ rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
+ if (new_x) \
+ { \
+ X = new_x; \
+ goto WIN; \
+ } \
+} while (0)
\f
-/* Nonzero if the constant value X is a legitimate general operand.
- It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-#define LEGITIMATE_CONSTANT_P(X) mn10300_legitimate_constant_p (X)
-
/* Zero if this needs fixing up to become PIC. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
/* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */
#define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X))
\f
-#define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (X)
+#define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y)
#define REVERSIBLE_CC_MODE(MODE) 0
\f
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- ((CLASS1 == CLASS2 && (CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS)) ? 2 :\
- ((CLASS1 == ADDRESS_REGS || CLASS1 == DATA_REGS) && \
- (CLASS2 == ADDRESS_REGS || CLASS2 == DATA_REGS)) ? 4 : \
- (CLASS1 == SP_REGS && CLASS2 == ADDRESS_REGS) ? 2 : \
- (CLASS1 == ADDRESS_REGS && CLASS2 == SP_REGS) ? 4 : \
- ! TARGET_AM33 ? 6 : \
- (CLASS1 == SP_REGS || CLASS2 == SP_REGS) ? 6 : \
- (CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS) ? 6 : \
- (CLASS1 == FP_REGS || CLASS2 == FP_REGS) ? 6 : \
- (CLASS1 == EXTENDED_REGS || CLASS2 == EXTENDED_REGS) ? 4 : \
- 4)
-
/* Nonzero if access to memory by bytes or half words is no faster
than accessing full words. */
#define SLOW_BYTE_ACCESS 1
#define ASM_OUTPUT_LABELREF(FILE, NAME) \
asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME))
-#define ASM_PN_FORMAT "%s___%lu"
-
/* This is how we tell the assembler that two symbols have the same value. */
#define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
#define DWARF2_DEBUGGING_INFO 1
-
#define DWARF2_ASM_LINE_DEBUG_INFO 1
-/* GDB always assumes the current function's frame begins at the value
- of the stack pointer upon entry to the current function. Accessing
- local variables and parameters passed on the stack is done using the
- base of the frame + an offset provided by GCC.
-
- For functions which have frame pointers this method works fine;
- the (frame pointer) == (stack pointer at function entry) and GCC provides
- an offset relative to the frame pointer.
-
- This loses for functions without a frame pointer; GCC provides an offset
- which is relative to the stack pointer after adjusting for the function's
- frame size. GDB would prefer the offset to be relative to the value of
- the stack pointer at the function's entry. Yuk! */
-#define DEBUGGER_AUTO_OFFSET(X) \
- ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
- + (frame_pointer_needed \
- ? 0 : - mn10300_initial_offset (FRAME_POINTER_REGNUM, \
- STACK_POINTER_REGNUM)))
-
-#define DEBUGGER_ARG_OFFSET(OFFSET, X) \
- ((GET_CODE (X) == PLUS ? OFFSET : 0) \
- + (frame_pointer_needed \
- ? 0 : - mn10300_initial_offset (ARG_POINTER_REGNUM, \
- STACK_POINTER_REGNUM)))
-
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE Pmode