;; Note that this value does not account for the delay slot
;; instruction, whose length is added separately. If the RTL
;; pattern has no explicit delay slot, mips_adjust_insn_length
- ;; will add the length of the implicit nop.
+ ;; will add the length of the implicit nop. The values for
+ ;; forward and backward branches will be different as well.
(eq_attr "type" "branch")
- (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
- (const_int 131072))
- (const_int 4)
+ (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
+ (le (minus (pc) (match_dup 1)) (const_int 131068)))
+ (const_int 4)
(ne (symbol_ref "flag_pic") (const_int 0))
(const_int 24)
] (const_int 12))
(const_string "yes")
(const_string "no"))))
+;; True if an instruction might assign to hi or lo when reloaded.
+;; This is used by the TUNE_MACC_CHAINS code.
+(define_attr "may_clobber_hilo" "no,yes"
+ (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")
+ (const_string "yes")
+ (const_string "no")))
+
;; Describe a user's asm statement.
(define_asm_attributes
[(set_attr "type" "multi")])
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
+ (eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
3 0)
(define_function_unit "memory" 1 0
(and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
+ (eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
2 0)
(define_function_unit "memory" 1 0
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "imul,imadd")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
+ (eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
17 17)
;; On them mips16, we want to stronly discourage a mult from appearing
1 5)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000,r3900"))
+ (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3900"))
12 12)
(define_function_unit "imuldiv" 1 0
(define_function_unit "imuldiv" 1 0
(and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
+ (eq_attr "cpu" "r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
38 38)
(define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3900"))
35 35)
(define_function_unit "imuldiv" 1 0
;; instructions to be processed in the "imuldiv" unit.
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000,r4300,r5000"))
3 0)
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
+ (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000"))
2 0)
(define_function_unit "adder" 1 1
1 0)
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900,r6000,r4300"))
4 0)
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
+ (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
2 0)
(define_function_unit "adder" 1 1
(define_function_unit "adder" 1 1
(and (eq_attr "type" "fabs,fneg,fmove")
- (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
+ (eq_attr "cpu" "r3900,r4600,r4650,r4300,r5000"))
2 0)
(define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
+ (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900,r4600,r4650,r5000"))
1 0)
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
(and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
+ (eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
7 0)
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900,r5000")))
4 0)
(define_function_unit "mult" 1 1
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r6000,r4300,r5000")))
8 0)
(define_function_unit "mult" 1 1
(and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r5000")))
5 0)
(define_function_unit "mult" 1 1
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
+ (eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300,r5000")))
23 0)
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
+ (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
12 0)
(define_function_unit "divide" 1 1
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
(and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
+ (eq_attr "cpu" "r3900,r6000,r4600,r4650,r4300")))
36 0)
(define_function_unit "divide" 1 1
(and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
+ (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
19 0)
(define_function_unit "divide" 1 1
\f
;; Include scheduling descriptions.
+(include "3000.md")
+(include "4130.md")
(include "5400.md")
(include "5500.md")
(include "7000.md")
(define_expand "conditional_trap"
[(trap_if (match_operator 0 "cmp_op"
[(match_dup 2) (match_dup 3)])
- (match_operand 1 "const_int_operand" ""))]
+ (match_operand 1 "const_int_operand"))]
"ISA_HAS_COND_TRAP"
{
if (operands[1] == const0_rtx)
(set_attr "mode" "SF")])
(define_expand "addsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_operand:SI 1 "reg_or_0_operand")
+ (match_operand:SI 2 "arith_operand")))]
""
{
/* If a large stack adjustment was forced into a register, we may be
"addu\t%$,%$,%0"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8")
(const_int 4)
(const_int 8)))])
"addu\t%0,%$,%1"
[(set_attr "type" "arith")
(set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4")
(const_int 4)
(const_int 8)))])
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
+ [(if_then_else (match_operand:VOID 2 "m16_simm8_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_simm4_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
;; simply adding a constant to a register.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" "")))]
+ (match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
})
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
})
(define_expand "adddi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
/* If a large stack adjustment was forced into a register, we may be
asked to generate rtx such as:
emit_move_insn (operands[0], tmp);
DONE;
}
-
- if (TARGET_64BIT)
- {
- emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
})
-(define_insn "adddi3_internal_1"
- [(set (match_operand:DI 0 "register_operand" "=d,&d")
- (plus:DI (match_operand:DI 1 "register_operand" "0,d")
- (match_operand:DI 2 "register_operand" "d,d")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- return (REGNO (operands[0]) == REGNO (operands[1])
- && REGNO (operands[0]) == REGNO (operands[2]))
- ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
- : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
- (match_operand:DI 2 "small_int" "P,J,N")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "@
- addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
- move\t%L0,%L1\;move\t%M0,%M1
- subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "12,8,16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_3"
+(define_insn "adddi3_internal"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:DI 2 "arith_operand" "d,Q")))]
"daddu\t%$,%$,%0"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8")
(const_int 4)
(const_int 8)))])
"daddu\t%0,%$,%1"
[(set_attr "type" "arith")
(set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4")
(const_int 4)
(const_int 8)))])
[(set_attr "type" "arith")
(set_attr "mode" "DI")
(set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
+ [(if_then_else (match_operand:VOID 2 "m16_simm5_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_simm4_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
;; simply adding a constant to a register.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(plus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" "")))]
+ (match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
[(set_attr "type" "arith")
(set_attr "mode" "SI")
(set_attr_alternative "length"
- [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
+ [(if_then_else (match_operand:VOID 2 "m16_simm8_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_simm4_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
(set_attr "mode" "SF")])
(define_expand "subsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
""
"")
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
-(define_expand "subdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-{
- if (TARGET_64BIT)
- {
- emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-})
-
-(define_insn "subdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (minus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "subdi3_internal_3"
+(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=d")
(minus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))]
;;
(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (mult:DF (match_operand:DF 1 "register_operand" "f")
- (match_operand:DF 2 "register_operand" "f")))]
+ [(set (match_operand:DF 0 "register_operand")
+ (mult:DF (match_operand:DF 1 "register_operand")
+ (match_operand:DF 2 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
(set_attr "length" "8")])
(define_expand "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (mult:SF (match_operand:SF 1 "register_operand" "f")
- (match_operand:SF 2 "register_operand" "f")))]
+ [(set (match_operand:SF 0 "register_operand")
+ (mult:SF (match_operand:SF 1 "register_operand")
+ (match_operand:SF 2 "register_operand")))]
"TARGET_HARD_FLOAT"
"")
;; respectively.
(define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
""
{
if (GENERATE_MULT3_SI || TARGET_MAD)
;; Operand 4: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))
+ [(set (match_operand:SI 0 "register_operand")
+ (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))
+ (clobber (match_operand:SI 3 "register_operand"))
(clobber (scratch:SI))])
- (set (match_operand:SI 4 "register_operand" "")
+ (set (match_operand:SI 4 "register_operand")
(unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
"GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
[(parallel
(set_attr "mode" "SI")
(set_attr "length" "8")])
+;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
+;; of "mult; mflo". They have the same latency, but the first form gives
+;; us an extra cycle to compute the operands.
+
+;; Operand 0: LO
+;; Operand 1: GPR (1st multiplication operand)
+;; Operand 2: GPR (2nd multiplication operand)
+;; Operand 3: HI
+;; Operand 4: GPR (destination)
+(define_peephole2
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand")
+ (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))
+ (clobber (match_operand:SI 3 "register_operand"))])
+ (set (match_operand:SI 4 "register_operand")
+ (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
+ "ISA_HAS_MACC && !GENERATE_MULT3_SI"
+ [(set (match_dup 0)
+ (const_int 0))
+ (parallel
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))
+ (set (match_dup 4)
+ (plus:SI (mult:SI (match_dup 1)
+ (match_dup 2))
+ (match_dup 0)))
+ (clobber (match_dup 3))])])
+
;; Multiply-accumulate patterns
;; For processors that can copy the output to a general register:
;; Split the above insn if we failed to get LO allocated.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (match_operand:SI 3 "register_operand" "")))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand"))
+ (match_operand:SI 3 "register_operand")))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
+ (clobber (match_scratch:SI 6))]
"reload_completed && !TARGET_DEBUG_D_MODE
&& GP_REG_P (true_regnum (operands[0]))
&& GP_REG_P (true_regnum (operands[3]))"
;; Splitter to copy result of MADD to a general register
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
- (match_operand:SI 3 "register_operand" "")))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand"))
+ (match_operand:SI 3 "register_operand")))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
+ (clobber (match_scratch:SI 6))]
"reload_completed && !TARGET_DEBUG_D_MODE
&& GP_REG_P (true_regnum (operands[0]))
&& true_regnum (operands[3]) == LO_REGNUM"
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])
- (set (match_dup 0) (match_dup 3))]
+ (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
"")
(define_insn "*macc"
else if (TARGET_MIPS5500)
return "madd\t%1,%2";
else
- return "macc\t%.,%1,%2";
+ /* The VR4130 assumes that there is a two-cycle latency between a macc
+ that "writes" to $0 and an instruction that reads from it. We avoid
+ this by assigning to $1 instead. */
+ return "%[macc\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
+;; An msac-like instruction implemented using negation and a macc.
+(define_insn_and_split "*msac_using_macc"
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
+ (minus:SI (match_operand:SI 1 "register_operand" "0,l")
+ (mult:SI (match_operand:SI 2 "register_operand" "d,d")
+ (match_operand:SI 3 "register_operand" "d,d"))))
+ (clobber (match_scratch:SI 4 "=h,h"))
+ (clobber (match_scratch:SI 5 "=X,1"))
+ (clobber (match_scratch:SI 6 "=d,d"))]
+ "ISA_HAS_MACC && !ISA_HAS_MSAC"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 6)
+ (neg:SI (match_dup 3)))
+ (parallel
+ [(set (match_dup 0)
+ (plus:SI (mult:SI (match_dup 2)
+ (match_dup 6))
+ (match_dup 1)))
+ (clobber (match_dup 4))
+ (clobber (match_dup 5))])]
+ ""
+ [(set_attr "type" "imadd")
+ (set_attr "length" "8")])
+
;; Patterns generated by the define_peephole2 below.
(define_insn "*macc2"
;; Operand 3: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "macc_msac_operand" ""))
- (clobber (match_operand:SI 2 "register_operand" ""))
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "macc_msac_operand"))
+ (clobber (match_operand:SI 2 "register_operand"))
(clobber (scratch:SI))])
- (set (match_operand:SI 3 "register_operand" "")
+ (set (match_operand:SI 3 "register_operand")
(unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
""
[(parallel [(set (match_dup 0)
;; Operand 7: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
+ (set (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand"))
(match_dup 0)
(parallel
- [(set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 4 "macc_msac_operand" ""))
- (clobber (match_operand:SI 5 "register_operand" ""))
+ [(set (match_operand:SI 3 "register_operand")
+ (match_operand:SI 4 "macc_msac_operand"))
+ (clobber (match_operand:SI 5 "register_operand"))
(clobber (match_dup 1))])]
"GENERATE_MULT3_SI
&& true_regnum (operands[1]) == LO_REGNUM
;; Operand 7: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" ""))
+ (set (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand"))
(match_dup 0)
(parallel
[(set (match_dup 1)
- (match_operand:SI 3 "macc_msac_operand" ""))
- (clobber (match_operand:SI 4 "register_operand" ""))
+ (match_operand:SI 3 "macc_msac_operand"))
+ (clobber (match_operand:SI 4 "register_operand"))
(clobber (scratch:SI))])
(match_dup 0)
- (set (match_operand:SI 5 "register_operand" "")
+ (set (match_operand:SI 5 "register_operand")
(unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
"GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
;; Split the above insn if we failed to get LO allocated.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (mult:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "register_operand" ""))))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (mult:SI (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "register_operand"))))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
+ (clobber (match_scratch:SI 6))]
"reload_completed && !TARGET_DEBUG_D_MODE
&& GP_REG_P (true_regnum (operands[0]))
&& GP_REG_P (true_regnum (operands[1]))"
;; Splitter to copy result of MSUB to a general register
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "register_operand" "")
- (mult:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "register_operand" ""))))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
- (clobber (match_scratch:SI 6 ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (minus:SI (match_operand:SI 1 "register_operand")
+ (mult:SI (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "register_operand"))))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
+ (clobber (match_scratch:SI 6))]
"reload_completed && !TARGET_DEBUG_D_MODE
&& GP_REG_P (true_regnum (operands[0]))
&& true_regnum (operands[1]) == LO_REGNUM"
(clobber (match_dup 4))
(clobber (match_dup 5))
(clobber (match_dup 6))])
- (set (match_dup 0) (match_dup 1))]
+ (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
"")
(define_insn "*muls"
(set_attr "mode" "SI")])
(define_expand "muldi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
"TARGET_64BIT"
{
if (GENERATE_MULT3_DI)
(define_expand "mulsidi3"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))
+ (sign_extend:DI (match_operand:SI 1 "register_operand"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand"))))
(clobber (scratch:DI))
(clobber (scratch:DI))
(clobber (scratch:DI))])]
(define_expand "umulsidi3"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(mult:DI
- (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
+ (zero_extend:DI (match_operand:SI 1 "register_operand"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand"))))
(clobber (scratch:DI))
(clobber (scratch:DI))
(clobber (scratch:DI))])]
;; _highpart patterns
(define_expand "umulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(truncate:SI
(lshiftrt:DI
- (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
- (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
+ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand"))
+ (zero_extend:DI (match_operand:SI 2 "register_operand")))
(const_int 32))))]
"ISA_HAS_MULHI || !TARGET_FIX_R4000"
{
(set_attr "length" "4")])
(define_expand "smulsi3_highpart"
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(truncate:SI
(lshiftrt:DI
- (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "register_operand" "")))
+ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand"))
+ (sign_extend:DI (match_operand:SI 2 "register_operand")))
(const_int 32))))]
"ISA_HAS_MULHI || !TARGET_FIX_R4000"
{
else if (TARGET_MIPS5500)
return "maddu\t%1,%2";
else
- return "maccu\t%.,%1,%2";
+ /* See comment in *macc. */
+ return "%[maccu\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
else if (TARGET_MIPS5500)
return "madd\t%1,%2";
else
- return "macc\t%.,%1,%2";
+ /* See comment in *macc. */
+ return "%[macc\t%@,%1,%2%]";
}
[(set_attr "type" "imadd")
(set_attr "mode" "SI")])
;;
(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "")
- (div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
- (match_operand:DF 2 "register_operand" "")))]
+ [(set (match_operand:DF 0 "register_operand")
+ (div:DF (match_operand:DF 1 "reg_or_const_float_1_operand")
+ (match_operand:DF 2 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
if (const_float_1_operand (operands[1], DFmode))
;; errata, or if working around those errata and a slight loss of
;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
- (match_operand:SF 2 "register_operand" "")))]
+ [(set (match_operand:SF 0 "register_operand")
+ (div:SF (match_operand:SF 1 "reg_or_const_float_1_operand")
+ (match_operand:SF 2 "register_operand")))]
"TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
{
if (const_float_1_operand (operands[1], SFmode))
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
-(define_expand "negdi2"
- [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (match_dup 2))])]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-{
- if (TARGET_64BIT)
- {
- emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
- DONE;
- }
-
- operands[2] = gen_reg_rtx (SImode);
-})
-
-(define_insn "negdi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_insn "negdi2_internal_2"
+(define_insn "negdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && !TARGET_MIPS16"
;; want to use a different set of constraints when TARGET_MIPS16.
(define_expand "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (and:SI (match_operand:SI 1 "uns_arith_operand")
+ (match_operand:SI 2 "uns_arith_operand")))]
""
{
if (TARGET_MIPS16)
(set_attr "mode" "SI")])
(define_expand "anddi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (and:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "uns_arith_operand")))]
"TARGET_64BIT"
{
if (TARGET_MIPS16)
(set_attr "mode" "DI")])
(define_expand "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ior:SI (match_operand:SI 1 "uns_arith_operand")
+ (match_operand:SI 2 "uns_arith_operand")))]
""
{
if (TARGET_MIPS16)
(set_attr "mode" "SI")])
(define_expand "iordi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (ior:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (ior:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "uns_arith_operand")))]
"TARGET_64BIT"
{
if (TARGET_MIPS16)
(set_attr "mode" "DI")])
(define_expand "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (xor:SI (match_operand:SI 1 "uns_arith_operand")
+ (match_operand:SI 2 "uns_arith_operand")))]
""
"")
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
(define_expand "xordi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (xor:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (xor:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "uns_arith_operand")))]
"TARGET_64BIT"
{
if (TARGET_MIPS16)
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))
(const_int 4)])])
(set_attr "mode" "DI")])
(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
""
{
if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
(set_attr "mode" "SI")])
(define_expand "zero_extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand")))]
"TARGET_64BIT"
{
if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
(set_attr "mode" "DI")])
(define_expand "zero_extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:HI 0 "register_operand")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
""
{
if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
(set_attr "mode" "HI")])
(define_expand "zero_extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
""
{
if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
(set_attr "mode" "SI")])
(define_expand "zero_extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand")))]
"TARGET_64BIT"
{
if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
;; Extension insns.
;; Those for integer source operand are ordered widest source type first.
-(define_insn "extendsidi2"
+;; When TARGET_64BIT, all SImode integer registers should already be in
+;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
+;; therefore get rid of register->register instructions if we constrain
+;; the source to be in the same register as the destination.
+;;
+;; The register alternative has type "arith" so that the pre-reload
+;; scheduler will treat it as a move. This reflects what happens if
+;; the register alternative needs a reload.
+(define_insn_and_split "extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
"TARGET_64BIT"
"@
- sll\t%0,%1,0
+ #
lw\t%0,%1"
- [(set_attr "type" "shift,load")
- (set_attr "mode" "DI")
- (set_attr "extended_mips16" "yes,*")])
+ "&& reload_completed && register_operand (operands[1], VOIDmode)"
+ [(const_int 0)]
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+}
+ [(set_attr "type" "arith,load")
+ (set_attr "mode" "DI")])
;; These patterns originally accepted general_operands, however, slightly
;; better code is generated by only accepting register_operands, and then
;; all non-mem patterns after reload.
(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand")))]
"TARGET_64BIT"
"")
"#")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:HI 1 "register_operand")))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (const_int 48)))
(set_attr "mode" "DI")])
(define_expand "extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
""
{
if (ISA_HAS_SEB_SEH)
"#")
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extend:SI (match_operand:HI 1 "register_operand")))]
"reload_completed"
[(set (match_dup 0)
(ashift:SI (match_dup 1) (const_int 16)))
(set_attr "mode" "SI")])
(define_expand "extendqihi2"
- [(set (match_operand:HI 0 "register_operand" "")
- (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:HI 0 "register_operand")
+ (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
""
"")
"#")
(define_split
- [(set (match_operand:HI 0 "register_operand" "")
- (sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
+ [(set (match_operand:HI 0 "register_operand")
+ (sign_extend:HI (match_operand:QI 1 "register_operand")))]
"reload_completed"
[(set (match_dup 0)
(ashift:SI (match_dup 1) (const_int 24)))
(define_expand "extendqisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
""
{
if (ISA_HAS_SEB_SEH)
"#")
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extend:SI (match_operand:QI 1 "register_operand")))]
"reload_completed"
[(set (match_dup 0)
(ashift:SI (match_dup 1) (const_int 24)))
(set_attr "mode" "SI")])
(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand")))]
"TARGET_64BIT"
"")
"#")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:QI 1 "register_operand")))]
"TARGET_64BIT && reload_completed"
[(set (match_dup 0)
(ashift:DI (match_dup 1) (const_int 56)))
;; ....................
(define_expand "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=f")
- (fix:SI (match_operand:DF 1 "register_operand" "f")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (fix:SI (match_operand:DF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
if (!ISA_HAS_TRUNC_W)
(set_attr "length" "36")])
(define_expand "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=f")
- (fix:SI (match_operand:SF 1 "register_operand" "f")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (fix:SI (match_operand:SF 1 "register_operand")))]
"TARGET_HARD_FLOAT"
{
if (!ISA_HAS_TRUNC_W)
(define_expand "fixuns_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
rtx reg1 = gen_reg_rtx (DFmode);
(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
{
rtx reg1 = gen_reg_rtx (DFmode);
(define_expand "fixuns_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
"TARGET_HARD_FLOAT"
{
rtx reg1 = gen_reg_rtx (SFmode);
(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
{
rtx reg1 = gen_reg_rtx (SFmode);
;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
(define_expand "extv"
- [(set (match_operand 0 "register_operand" "")
- (sign_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
+ [(set (match_operand 0 "register_operand")
+ (sign_extract (match_operand:QI 1 "memory_operand")
+ (match_operand 2 "immediate_operand")
+ (match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_load (operands[0], operands[1],
})
(define_expand "extzv"
- [(set (match_operand 0 "register_operand" "")
- (zero_extract (match_operand:QI 1 "memory_operand" "")
- (match_operand 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")))]
+ [(set (match_operand 0 "register_operand")
+ (zero_extract (match_operand:QI 1 "memory_operand")
+ (match_operand 2 "immediate_operand")
+ (match_operand 3 "immediate_operand")))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_load (operands[0], operands[1],
})
(define_expand "insv"
- [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
- (match_operand 1 "immediate_operand" "")
- (match_operand 2 "immediate_operand" ""))
- (match_operand 3 "reg_or_0_operand" ""))]
+ [(set (zero_extract (match_operand:QI 0 "memory_operand")
+ (match_operand 1 "immediate_operand")
+ (match_operand 2 "immediate_operand"))
+ (match_operand 3 "reg_or_0_operand"))]
"!TARGET_MIPS16"
{
if (mips_expand_unaligned_store (operands[0], operands[3],
;; the compiler, have memoized the insn number already.
(define_expand "movdi"
- [(set (match_operand:DI 0 "" "")
- (match_operand:DI 1 "" ""))]
+ [(set (match_operand:DI 0 "")
+ (match_operand:DI 1 ""))]
""
{
if (mips_legitimize_move (DImode, operands[0], operands[1]))
[(const_int 4)
(const_int 4)
(const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
(const_int 8)
(const_int 12))
(const_string "*")
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(mem:DI (plus:DI (match_dup 0)
- (match_operand:DI 1 "const_int_operand" ""))))]
+ (match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
;; the compiler, have memoized the insn number already.
(define_expand "movsi"
- [(set (match_operand:SI 0 "" "")
- (match_operand:SI 1 "" ""))]
+ [(set (match_operand:SI 0 "")
+ (match_operand:SI 1 ""))]
""
{
if (mips_legitimize_move (SImode, operands[0], operands[1]))
[(const_int 4)
(const_int 4)
(const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
(const_int 8)
(const_int 12))
(const_string "*")
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(mem:SI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
+ (match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
;; instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
;; load and a neg. That's what mips_output_move will generate anyhow.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "const_int_operand" ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
(define_expand "movhi"
- [(set (match_operand:HI 0 "" "")
- (match_operand:HI 1 "" ""))]
+ [(set (match_operand:HI 0 "")
+ (match_operand:HI 1 ""))]
""
{
if (mips_legitimize_move (HImode, operands[0], operands[1]))
[(const_int 4)
(const_int 4)
(const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
(const_int 4)
(const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
+ (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
(const_int 8)
(const_int 12))
(const_string "*")
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "register_operand")
(mem:HI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
+ (match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
(define_expand "movqi"
- [(set (match_operand:QI 0 "" "")
- (match_operand:QI 1 "" ""))]
+ [(set (match_operand:QI 0 "")
+ (match_operand:QI 1 ""))]
""
{
if (mips_legitimize_move (QImode, operands[0], operands[1]))
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "register_operand")
(mem:QI (plus:SI (match_dup 0)
- (match_operand:SI 1 "const_int_operand" ""))))]
+ (match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[0]) == REG
&& M16_REG_P (REGNO (operands[0]))
;; 32-bit floating point moves
(define_expand "movsf"
- [(set (match_operand:SF 0 "" "")
- (match_operand:SF 1 "" ""))]
+ [(set (match_operand:SF 0 "")
+ (match_operand:SF 1 ""))]
""
{
if (mips_legitimize_move (SFmode, operands[0], operands[1]))
;; 64-bit floating point moves
(define_expand "movdf"
- [(set (match_operand:DF 0 "" "")
- (match_operand:DF 1 "" ""))]
+ [(set (match_operand:DF 0 "")
+ (match_operand:DF 1 ""))]
""
{
if (mips_legitimize_move (DFmode, operands[0], operands[1]))
(set_attr "length" "8,8,8,*,*")])
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "move_operand" ""))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "move_operand"))]
"reload_completed && !TARGET_64BIT
&& mips_split_64bit_move_p (operands[0], operands[1])"
[(const_int 0)]
})
(define_split
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "move_operand" ""))]
+ [(set (match_operand:DF 0 "nonimmediate_operand")
+ (match_operand:DF 1 "move_operand"))]
"reload_completed && !TARGET_64BIT
&& mips_split_64bit_move_p (operands[0], operands[1])"
[(const_int 0)]
;; The HI and LO registers are not truly independent. If we move an mthi
;; instruction before an mflo instruction, it will make the result of the
-;; mflo unpredicatable. The same goes for mtlo and mfhi.
+;; mflo unpredictable. The same goes for mtlo and mfhi.
;;
;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
;; Operand 1 is the register we want, operand 2 is the other one.
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpload")
- (set_attr "mode" "SF")
- (set_attr "length" "4")])
+ (set_attr "mode" "SF")])
;; Load the high word of operand 0 from operand 1, preserving the value
;; in the low word.
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpload")
- (set_attr "mode" "SF")
- (set_attr "length" "4")])
+ (set_attr "mode" "SF")])
;; Store the high word of operand 1 in operand 0. The corresponding
;; low-word move is done in the normal way.
return mips_output_move (operands[0], operands[1]);
}
[(set_attr "type" "xfer,fpstore")
- (set_attr "mode" "SF")
- (set_attr "length" "4")])
+ (set_attr "mode" "SF")])
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
;; of _gp from the start of this function. Operand 1 is the incoming
;; Argument 3 is the alignment
(define_expand "movstrsi"
- [(parallel [(set (match_operand:BLK 0 "general_operand" "")
- (match_operand:BLK 1 "general_operand" ""))
- (use (match_operand:SI 2 "" ""))
- (use (match_operand:SI 3 "const_int_operand" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "general_operand")
+ (match_operand:BLK 1 "general_operand"))
+ (use (match_operand:SI 2 ""))
+ (use (match_operand:SI 3 "const_int_operand"))])]
"!TARGET_MIPS16 && !TARGET_MEMCPY"
{
if (mips_expand_block_move (operands[0], operands[1], operands[2]))
;; want to use a different set of constraints when TARGET_MIPS16.
(define_expand "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashift:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ashift:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
""
{
/* On the mips16, a shift of more than 8 is a four byte instruction,
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ashift:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (ashift:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. This can be called by
+ function_arg, so we must be careful not to allocate a new
+ register if we've reached the reload pass. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16
+ && ! reload_in_progress
+ && ! reload_completed)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. This can be called by
- function_arg, so we must be careful not to allocate a new
- register if we've reached the reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (DImode);
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashldi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
-
- emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_ashldi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_ashldi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "ashldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-sll\t%M0,%L1,%2\;\
-%(b\t3f\;\
-move\t%L0,%.%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-sll\t%M0,%M1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-srl\t%3,%L1,%3\;\
-or\t%M0,%M0,%3\n\
-%~2:\;\
-sll\t%L0,%L1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashldi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sll\t%M0,%L1,%2\;move\t%L0,%.";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashldi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "ashldi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (ashift:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
&& reload_completed
&& GET_CODE (operands[2]) == CONST_INT
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
""
{
/* On the mips16, a shift of more than 8 is a four byte instruction,
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_ashrdi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_ashrdi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "ashrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-sra\t%L0,%M1,%2\;\
-%(b\t3f\;\
-sra\t%M0,%M1,31%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-srl\t%L0,%L1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-sll\t%3,%M1,%3\;\
-or\t%L0,%L0,%3\n\
-%~2:\;\
-sra\t%M0,%M1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "ashrdi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
&& reload_completed
&& GET_CODE (operands[2]) == CONST_INT
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
""
{
/* On the mips16, a shift of more than 8 is a four byte instruction,
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
;; to make it simple enough for combine to understand.
;;
;; The length here is the worst case: the length of the split version
-;; will be more accurate.
+;; will be more accurate.
(define_insn_and_split ""
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(set_attr "length" "16")])
(define_expand "lshrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_lshrdi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_lshrdi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "lshrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-srl\t%L0,%M1,%2\;\
-%(b\t3f\;\
-move\t%M0,%.%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-srl\t%L0,%L1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-sll\t%3,%M1,%3\;\
-or\t%L0,%L0,%3\n\
-%~2:\;\
-srl\t%M0,%M1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "lshrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "srl\t%L0,%M1,%2\;move\t%M0,%.";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "lshrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "small_int" "")))
- (clobber (match_operand:SI 3 "register_operand" ""))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "lshrdi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm3_b")
(const_int 4)
(const_int 8))])])
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
&& GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
(define_expand "cmpsi"
[(set (cc0)
- (compare:CC (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "arith_operand" "")))]
+ (compare:CC (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "arith_operand")))]
""
{
branch_cmp[0] = operands[0];
(define_expand "cmpdi"
[(set (cc0)
- (compare:CC (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "arith_operand" "")))]
+ (compare:CC (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "arith_operand")))]
"TARGET_64BIT"
{
branch_cmp[0] = operands[0];
(define_expand "cmpdf"
[(set (cc0)
- (compare:CC (match_operand:DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")))]
+ (compare:CC (match_operand:DF 0 "register_operand")
+ (match_operand:DF 1 "register_operand")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
branch_cmp[0] = operands[0];
(define_expand "cmpsf"
[(set (cc0)
- (compare:CC (match_operand:SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")))]
+ (compare:CC (match_operand:SF 0 "register_operand")
+ (match_operand:SF 1 "register_operand")))]
"TARGET_HARD_FLOAT"
{
branch_cmp[0] = operands[0];
[(set (pc)
(if_then_else (unordered:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ordered:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (unlt:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (unge:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (uneq:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ltgt:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (unle:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ungt:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (eq:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ne:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (gt:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ge:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (lt:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (le:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (gtu:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (geu:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (ltu:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
[(set (pc)
(if_then_else (leu:CC (cc0)
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0 ""))
(pc)))]
""
{
;; ....................
(define_expand "seq"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(eq:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (eq:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (eq:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "uns_arith_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
[(set (match_dup 0)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (eq:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (eq:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "uns_arith_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16
&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
;; On the mips16 the default code is better than using sltu.
(define_expand "sne"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(ne:SI (match_dup 1)
(match_dup 2)))]
"!TARGET_MIPS16"
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ne:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ne:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "uns_arith_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
[(set (match_dup 0)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ne:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "uns_arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (ne:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "uns_arith_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16
&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
"")
(define_expand "sgt"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(gt:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "mode" "DI")])
(define_expand "sge"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(ge:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (ge:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (ge:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
[(set (match_dup 0)
(lt:SI (match_dup 1)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ge:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (ge:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "arith_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16"
[(set (match_dup 0)
"")
(define_expand "slt"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(lt:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))])])
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))])])
(define_expand "sle"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(le:SI (match_dup 1)
(match_dup 2)))]
""
}
[(set_attr "type" "slt")
(set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
}
[(set_attr "type" "slt")
(set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (le:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (le:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
[(set (match_dup 0)
(lt:SI (match_dup 2)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (le:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (le:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16"
[(set (match_dup 0)
"")
(define_expand "sgtu"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(gtu:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "mode" "DI")])
(define_expand "sgeu"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(geu:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (geu:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "arith_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (geu:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
[(set (match_dup 0)
(ltu:SI (match_dup 1)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (geu:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "arith_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (geu:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "arith_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16"
[(set (match_dup 0)
"")
(define_expand "sltu"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(ltu:SI (match_dup 1)
(match_dup 2)))]
""
(set_attr "mode" "SI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))])])
(set_attr "mode" "DI")
(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
+ (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))])])
(define_expand "sleu"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand")
(leu:SI (match_dup 1)
(match_dup 2)))]
""
}
[(set_attr "type" "slt")
(set_attr "mode" "SI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
}
[(set_attr "type" "slt")
(set_attr "mode" "DI")
- (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
+ (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
(set_attr "length" "8")])
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (leu:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (leu:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "register_operand")))]
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
[(set (match_dup 0)
(ltu:SI (match_dup 2)
(set_attr "length" "8")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (leu:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (leu:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))]
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
&& !TARGET_MIPS16"
[(set (match_dup 0)
(set_attr "length" "8")])
(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "register_operand" "d"))]
+ [(set (pc) (match_operand 0 "register_operand"))]
""
{
rtx dest;
(define_expand "tablejump"
[(set (pc)
- (match_operand 0 "register_operand" "d"))
- (use (label_ref (match_operand 1 "" "")))]
+ (match_operand 0 "register_operand"))
+ (use (label_ref (match_operand 1 "")))]
""
{
if (TARGET_MIPS16)
(set_attr "mode" "none")])
(define_expand "tablejump_mips161"
- [(set (pc) (plus:SI (sign_extend:SI
- (match_operand:HI 0 "register_operand" "d"))
- (label_ref:SI (match_operand 1 "" ""))))]
+ [(set (pc) (plus:SI (sign_extend:SI (match_operand:HI 0 "register_operand"))
+ (label_ref:SI (match_operand 1 ""))))]
"TARGET_MIPS16 && !(Pmode == DImode)"
{
rtx t1, t2, t3;
})
(define_expand "tablejump_mips162"
- [(set (pc) (plus:DI (sign_extend:DI
- (match_operand:HI 0 "register_operand" "d"))
- (label_ref:DI (match_operand 1 "" ""))))]
+ [(set (pc) (plus:DI (sign_extend:DI (match_operand:HI 0 "register_operand"))
+ (label_ref:DI (match_operand 1 ""))))]
"TARGET_MIPS16 && Pmode == DImode"
{
rtx t1, t2, t3;
;; it takes 3 or 4 insns to do so.
(define_expand "builtin_setjmp_setup"
- [(use (match_operand 0 "register_operand" ""))]
+ [(use (match_operand 0 "register_operand"))]
"TARGET_ABICALLS"
{
rtx addr;
;; $25 for compatibility (we lose nothing by doing so).
(define_expand "builtin_longjmp"
- [(use (match_operand 0 "register_operand" "r"))]
+ [(use (match_operand 0 "register_operand"))]
"TARGET_ABICALLS"
{
/* The elements of the buffer are, in order: */
;; This is used in compiling the unwind routines.
(define_expand "eh_return"
- [(use (match_operand 0 "general_operand" ""))]
+ [(use (match_operand 0 "general_operand"))]
""
{
enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
"#")
(define_split
- [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
- (clobber (match_scratch 1 ""))]
+ [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
+ (clobber (match_scratch 1))]
"reload_completed && !TARGET_DEBUG_D_MODE"
[(const_int 0)]
{
;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
(define_expand "sibcall"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" "")) ;; next_arg_reg
- (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
+ [(parallel [(call (match_operand 0 "")
+ (match_operand 1 ""))
+ (use (match_operand 2 "")) ;; next_arg_reg
+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx
"TARGET_SIBCALLS"
{
mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
[(set_attr "type" "call")])
(define_expand "sibcall_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))])] ;; next_arg_reg
+ [(parallel [(set (match_operand 0 "")
+ (call (match_operand 1 "")
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))])] ;; next_arg_reg
"TARGET_SIBCALLS"
{
mips_expand_call (operands[0], XEXP (operands[1], 0),
[(set_attr "type" "call")])
(define_expand "call"
- [(parallel [(call (match_operand 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" "")) ;; next_arg_reg
- (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
+ [(parallel [(call (match_operand 0 "")
+ (match_operand 1 ""))
+ (use (match_operand 2 "")) ;; next_arg_reg
+ (use (match_operand 3 ""))])] ;; struct_value_size_rtx
""
{
mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
[(set_attr "type" "call")])
(define_expand "call_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))])] ;; next_arg_reg
+ [(parallel [(set (match_operand 0 "")
+ (call (match_operand 1 "")
+ (match_operand 2 "")))
+ (use (match_operand 3 ""))])] ;; next_arg_reg
""
{
mips_expand_call (operands[0], XEXP (operands[1], 0),
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0 "")
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1 "")
+ (match_operand 2 "")])]
""
{
int i;
(define_expand "prefetch"
- [(prefetch (match_operand 0 "address_operand" "")
- (match_operand 1 "const_int_operand" "")
- (match_operand 2 "const_int_operand" ""))]
+ [(prefetch (match_operand 0 "address_operand")
+ (match_operand 1 "const_int_operand")
+ (match_operand 2 "const_int_operand"))]
"ISA_HAS_PREFETCH"
{
if (symbolic_operand (operands[0], GET_MODE (operands[0])))
;; These are the main define_expand's used to make conditional moves.
(define_expand "movsicc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:SI 0 "register_operand" "")
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:SI 0 "register_operand")
(if_then_else:SI (match_dup 5)
- (match_operand:SI 2 "reg_or_0_operand" "")
- (match_operand:SI 3 "reg_or_0_operand" "")))]
+ (match_operand:SI 2 "reg_or_0_operand")
+ (match_operand:SI 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
{
gen_conditional_move (operands);
})
(define_expand "movdicc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:DI 0 "register_operand" "")
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (match_dup 5)
- (match_operand:DI 2 "reg_or_0_operand" "")
- (match_operand:DI 3 "reg_or_0_operand" "")))]
+ (match_operand:DI 2 "reg_or_0_operand")
+ (match_operand:DI 3 "reg_or_0_operand")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
{
gen_conditional_move (operands);
})
(define_expand "movsfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:SF 0 "register_operand" "")
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:SF 0 "register_operand")
(if_then_else:SF (match_dup 5)
- (match_operand:SF 2 "register_operand" "")
- (match_operand:SF 3 "register_operand" "")))]
+ (match_operand:SF 2 "register_operand")
+ (match_operand:SF 3 "register_operand")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
{
gen_conditional_move (operands);
})
(define_expand "movdfcc"
- [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
- (set (match_operand:DF 0 "register_operand" "")
+ [(set (match_dup 4) (match_operand 1 "comparison_operator"))
+ (set (match_operand:DF 0 "register_operand")
(if_then_else:DF (match_dup 5)
- (match_operand:DF 2 "register_operand" "")
- (match_operand:DF 3 "register_operand" "")))]
+ (match_operand:DF 2 "register_operand")
+ (match_operand:DF 3 "register_operand")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
{
gen_conditional_move (operands);
(set_attr "length" "8")])
(define_split
- [(match_operand 0 "small_data_pattern" "")]
+ [(match_operand 0 "small_data_pattern")]
"reload_completed"
[(match_dup 0)]
{ operands[0] = mips_rewrite_small_data (operands[0]); })
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