;; Mips.md Machine Description for MIPS based processors
;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;; Contributed by A. Lichnewsky, lich@inria.inria.fr
;; Changes by Michael Meissner, meissner@osf.org
;; <http://www.gnu.org/licenses/>.
(define_constants
- [(UNSPEC_LOAD_DF_LOW 0)
- (UNSPEC_LOAD_DF_HIGH 1)
- (UNSPEC_STORE_DF_HIGH 2)
+ [(UNSPEC_LOAD_LOW 0)
+ (UNSPEC_LOAD_HIGH 1)
+ (UNSPEC_STORE_WORD 2)
(UNSPEC_GET_FNADDR 3)
(UNSPEC_BLOCKAGE 4)
(UNSPEC_CPRESTORE 5)
- (UNSPEC_NONLOCAL_GOTO_RECEIVER 6)
+ (UNSPEC_RESTORE_GP 6)
(UNSPEC_EH_RETURN 7)
(UNSPEC_CONSTTABLE_INT 8)
(UNSPEC_CONSTTABLE_FLOAT 9)
(UNSPEC_LOAD_CALL 23)
(UNSPEC_LOAD_GOT 24)
(UNSPEC_GP 25)
- (UNSPEC_MFHILO 26)
- (UNSPEC_TLS_LDM 27)
- (UNSPEC_TLS_GET_TP 28)
+ (UNSPEC_MFHI 26)
+ (UNSPEC_MTHI 27)
+ (UNSPEC_SET_HILO 28)
+ (UNSPEC_TLS_LDM 29)
+ (UNSPEC_TLS_GET_TP 30)
(UNSPEC_MFHC1 31)
(UNSPEC_MTHC1 32)
(UNSPEC_CLEAR_HAZARD 33)
(UNSPEC_SYNCI 35)
(UNSPEC_SYNC 36)
(UNSPEC_COMPARE_AND_SWAP 37)
- (UNSPEC_SYNC_OLD_OP 38)
- (UNSPEC_SYNC_NEW_OP 39)
- (UNSPEC_SYNC_EXCHANGE 40)
- (UNSPEC_MEMORY_BARRIER 41)
+ (UNSPEC_COMPARE_AND_SWAP_12 38)
+ (UNSPEC_SYNC_OLD_OP 39)
+ (UNSPEC_SYNC_NEW_OP 40)
+ (UNSPEC_SYNC_NEW_OP_12 41)
+ (UNSPEC_SYNC_OLD_OP_12 42)
+ (UNSPEC_SYNC_EXCHANGE 43)
+ (UNSPEC_SYNC_EXCHANGE_12 44)
+ (UNSPEC_MEMORY_BARRIER 45)
+ (UNSPEC_SET_GOT_VERSION 46)
+ (UNSPEC_UPDATE_GOT_VERSION 47)
+ (UNSPEC_COPYGP 48)
(UNSPEC_ADDRESS_FIRST 100)
- (FAKE_CALL_REGNO 79)
+ (TLS_GET_TP_REGNUM 3)
+ (GOT_VERSION_REGNUM 79)
;; For MIPS Paired-Singled Floating Point Instructions.
(UNSPEC_DPAQX_SA_W_PH 446)
(UNSPEC_DPSQX_S_W_PH 447)
(UNSPEC_DPSQX_SA_W_PH 448)
+
+ ;; ST Microelectronics Loongson-2E/2F.
+ (UNSPEC_LOONGSON_PAVG 500)
+ (UNSPEC_LOONGSON_PCMPEQ 501)
+ (UNSPEC_LOONGSON_PCMPGT 502)
+ (UNSPEC_LOONGSON_PEXTR 503)
+ (UNSPEC_LOONGSON_PINSR_0 504)
+ (UNSPEC_LOONGSON_PINSR_1 505)
+ (UNSPEC_LOONGSON_PINSR_2 506)
+ (UNSPEC_LOONGSON_PINSR_3 507)
+ (UNSPEC_LOONGSON_PMADD 508)
+ (UNSPEC_LOONGSON_PMOVMSK 509)
+ (UNSPEC_LOONGSON_PMULHU 510)
+ (UNSPEC_LOONGSON_PMULH 511)
+ (UNSPEC_LOONGSON_PMULL 512)
+ (UNSPEC_LOONGSON_PMULU 513)
+ (UNSPEC_LOONGSON_PASUBUB 514)
+ (UNSPEC_LOONGSON_BIADD 515)
+ (UNSPEC_LOONGSON_PSADBH 516)
+ (UNSPEC_LOONGSON_PSHUFH 517)
+ (UNSPEC_LOONGSON_PUNPCKH 518)
+ (UNSPEC_LOONGSON_PUNPCKL 519)
+ (UNSPEC_LOONGSON_PADDD 520)
+ (UNSPEC_LOONGSON_PSUBD 521)
+
+ ;; Used in loongson2ef.md
+ (UNSPEC_LOONGSON_ALU1_TURN_ENABLED_INSN 530)
+ (UNSPEC_LOONGSON_ALU2_TURN_ENABLED_INSN 531)
+ (UNSPEC_LOONGSON_FALU1_TURN_ENABLED_INSN 532)
+ (UNSPEC_LOONGSON_FALU2_TURN_ENABLED_INSN 533)
]
)
(symbol_ref "TARGET_CALL_CLOBBERED_GP")]
(const_string "no")))
+;; Classification of moves, extensions and truncations. Most values
+;; are as for "type" (see below) but there are also the following
+;; move-specific values:
+;;
+;; constN move an N-constraint integer into a MIPS16 register
+;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
+;; to produce a sign-extended DEST, even if SRC is not
+;; properly sign-extended
+;; andi a single ANDI instruction
+;; loadpool move a constant into a MIPS16 register by loading it
+;; from the pool
+;; shift_shift a shift left followed by a shift right
+;; lui_movf an LUI followed by a MOVF (for d<-z CC moves)
+;;
+;; This attribute is used to determine the instruction's length and
+;; scheduling type. For doubleword moves, the attribute always describes
+;; the split instructions; in some cases, it is more appropriate for the
+;; scheduling type to be "multi" instead.
+(define_attr "move_type"
+ "unknown,load,fpload,store,fpstore,mtc,mfc,mthilo,mfhilo,move,fmove,
+ const,constN,signext,sll0,andi,loadpool,shift_shift,lui_movf"
+ (const_string "unknown"))
+
+;; Main data type used by the insn
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
+ (const_string "unknown"))
+
+;; True if the main data type is twice the size of a word.
+(define_attr "dword_mode" "no,yes"
+ (cond [(and (eq_attr "mode" "DI,DF")
+ (eq (symbol_ref "TARGET_64BIT") (const_int 0)))
+ (const_string "yes")
+
+ (and (eq_attr "mode" "TI,TF")
+ (ne (symbol_ref "TARGET_64BIT") (const_int 0)))
+ (const_string "yes")]
+ (const_string "no")))
+
;; Classification of each insn.
;; branch conditional branch
;; jump unconditional jump
;; prefetch memory prefetch (register + offset)
;; prefetchx memory indexed prefetch (register + register)
;; condmove conditional moves
-;; mfc transfer from coprocessor
;; mtc transfer to coprocessor
+;; mfc transfer from coprocessor
;; mthilo transfer to hi/lo registers
;; mfhilo transfer from hi/lo registers
;; const load constant
;; slt set less than instructions
;; signext sign extend instructions
;; clz the clz and clo instructions
+;; pop the pop instruction
;; trap trap if instructions
;; imul integer multiply 2 operands
;; imul3 integer multiply 3 operands
;; frsqrt2 floating point reciprocal square root step2
;; multi multiword sequence (or user asm statements)
;; nop no operation
+;; ghost an instruction that produces no real code
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,logical,shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
+ "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
+ prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
+ shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
+ fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
+ frsqrt2,multi,nop,ghost"
(cond [(eq_attr "jal" "!unset") (const_string "call")
- (eq_attr "got" "load") (const_string "load")]
+ (eq_attr "got" "load") (const_string "load")
+
+ ;; If a doubleword move uses these expensive instructions,
+ ;; it is usually better to schedule them in the same way
+ ;; as the singleword form, rather than as "multi".
+ (eq_attr "move_type" "load") (const_string "load")
+ (eq_attr "move_type" "fpload") (const_string "fpload")
+ (eq_attr "move_type" "store") (const_string "store")
+ (eq_attr "move_type" "fpstore") (const_string "fpstore")
+ (eq_attr "move_type" "mtc") (const_string "mtc")
+ (eq_attr "move_type" "mfc") (const_string "mfc")
+ (eq_attr "move_type" "mthilo") (const_string "mthilo")
+ (eq_attr "move_type" "mfhilo") (const_string "mfhilo")
+
+ ;; These types of move are always single insns.
+ (eq_attr "move_type" "fmove") (const_string "fmove")
+ (eq_attr "move_type" "loadpool") (const_string "load")
+ (eq_attr "move_type" "signext") (const_string "signext")
+ (eq_attr "move_type" "sll0") (const_string "shift")
+ (eq_attr "move_type" "andi") (const_string "logical")
+
+ ;; These types of move are always split.
+ (eq_attr "move_type" "constN,lui_movf,shift_shift")
+ (const_string "multi")
+
+ ;; These types of move are split for doubleword modes only.
+ (and (eq_attr "move_type" "move,const")
+ (eq_attr "dword_mode" "yes"))
+ (const_string "multi")
+ (eq_attr "move_type" "move") (const_string "move")
+ (eq_attr "move_type" "const") (const_string "const")]
(const_string "unknown")))
-;; Main data type used by the insn
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
- (const_string "unknown"))
-
;; Mode for conversion types (fcvt)
;; I2S integer to float single (SI/DI to SF)
;; I2D integer to float double (SI/DI to DF)
;; Is this an extended instruction in mips16 mode?
(define_attr "extended_mips16" "no,yes"
- (const_string "no"))
+ (if_then_else (ior (eq_attr "move_type" "sll0")
+ (eq_attr "type" "branch")
+ (eq_attr "jal" "direct"))
+ (const_string "yes")
+ (const_string "no")))
;; Length of instruction in bytes.
(define_attr "length" ""
- (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
+ (cond [(and (eq_attr "extended_mips16" "yes")
+ (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
+ (const_int 8)
+
+ ;; Direct branch instructions have a range of [-0x40000,0x3fffc].
;; If a branch is outside this range, we have a choice of two
;; sequences. For PIC, an out-of-range branch like:
;;
(const_int 24)
] (const_int 12))
+ ;; "Ghost" instructions occupy no space.
+ (eq_attr "type" "ghost")
+ (const_int 0)
+
(eq_attr "got" "load")
- (const_int 4)
+ (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (const_int 8)
+ (const_int 4))
(eq_attr "got" "xgot_high")
(const_int 8)
- (eq_attr "type" "const")
+ ;; In general, constant-pool loads are extended instructions.
+ (eq_attr "move_type" "loadpool")
+ (const_int 8)
+
+ ;; LUI_MOVFs are decomposed into two separate instructions.
+ (eq_attr "move_type" "lui_movf")
+ (const_int 8)
+
+ ;; SHIFT_SHIFTs are decomposed into two separate instructions.
+ ;; They are extended instructions on MIPS16 targets.
+ (eq_attr "move_type" "shift_shift")
+ (if_then_else (ne (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (const_int 16)
+ (const_int 8))
+
+ ;; Check for doubleword moves that are decomposed into two
+ ;; instructions.
+ (and (eq_attr "move_type" "mtc,mfc,mthilo,mfhilo,move")
+ (eq_attr "dword_mode" "yes"))
+ (const_int 8)
+
+ ;; Doubleword CONST{,N} moves are split into two word
+ ;; CONST{,N} moves.
+ (and (eq_attr "move_type" "const,constN")
+ (eq_attr "dword_mode" "yes"))
+ (symbol_ref "mips_split_const_insns (operands[1]) * 4")
+
+ ;; Otherwise, constants, loads and stores are handled by external
+ ;; routines.
+ (eq_attr "move_type" "const,constN")
(symbol_ref "mips_const_insns (operands[1]) * 4")
- (eq_attr "type" "load,fpload")
+ (eq_attr "move_type" "load,fpload")
(symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
- (eq_attr "type" "store,fpstore")
+ (eq_attr "move_type" "store,fpstore")
(symbol_ref "mips_load_store_insns (operands[0], insn) * 4")
;; In the worst case, a call macro will take 8 instructions:
(eq_attr "jal_macro" "yes")
(const_int 32)
- (and (eq_attr "extended_mips16" "yes")
- (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
- (const_int 8)
-
;; Various VR4120 errata require a nop to be inserted after a macc
;; instruction. The assembler does this for us, so account for
;; the worst-case length here.
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
- "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
+ "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
(const_string "yes")
(const_string "no")))
-;; Attribute defining whether or not we can use the branch-likely instructions
+;; Attribute defining whether or not we can use the branch-likely
+;; instructions.
(define_attr "branch_likely" "no,yes"
- (const
- (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
- (const_string "yes")
- (const_string "no"))))
+ (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
+ (const_string "yes")
+ (const_string "no")))
;; True if an instruction might assign to hi or lo when reloaded.
;; This is used by the TUNE_MACC_CHAINS code.
;; from the same template.
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
+;; A copy of GPR that can be used when a pattern has two independent
+;; modes.
+(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
+
+;; This mode iterator allows :HILO to be used as the mode of the
+;; concatenated HI and LO registers.
+(define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
+
;; This mode iterator allows :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
;; This mode iterator allows :MOVECC to be used anywhere that a
;; conditional-move-type condition is needed.
-(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
+(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
+ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
+
+;; 64-bit modes for which we provide move patterns.
+(define_mode_iterator MOVE64
+ [DI DF
+ (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
+ (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
+ (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
+ (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
+
+;; 128-bit modes for which we provide move patterns on 64-bit targets.
+(define_mode_iterator MOVE128 [TI TF])
;; This mode iterator allows the QI and HI extension patterns to be
;; defined from the same template.
(define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
+;; A floating-point mode for which moves involving FPRs may need to be split.
+(define_mode_iterator SPLITF
+ [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+ (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
+ (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
+ (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
+ (TF "TARGET_64BIT && TARGET_FLOAT64")])
+
;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
;; 32-bit version and "dsubu" in the 64-bit version.
(define_mode_attr d [(SI "") (DI "d")
(HA "") (SA "") (DA "d")
(UHA "") (USA "") (UDA "d")])
+;; Same as d but upper-case.
+(define_mode_attr D [(SI "") (DI "D")
+ (QQ "") (HQ "") (SQ "") (DQ "D")
+ (UQQ "") (UHQ "") (USQ "") (UDQ "D")
+ (HA "") (SA "") (DA "D")
+ (UHA "") (USA "") (UDA "D")])
+
;; This attribute gives the length suffix for a sign- or zero-extension
;; instruction.
(define_mode_attr size [(QI "b") (HI "h")])
(V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
(V2HQ "SI") (V2HA "SI")])
+;; This attribute gives the integer mode that has half the size of
+;; the controlling mode.
+(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
+ (V2SI "SI") (V4HI "SI") (V8QI "SI")
+ (TF "DI")])
+
;; This attribute works around the early SB-1 rev2 core "F2" erratum:
;;
;; In certain cases, div.s and div.ps may have a rounding error
[DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
(V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
-; This attribute gives the condition for which sqrt instructions exist.
+;; This attribute gives the conditions under which SQRT.fmt instructions
+;; can be used.
(define_mode_attr sqrt_condition
[(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
-; This attribute gives the condition for which recip and rsqrt instructions
-; exist.
+;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
+;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
+;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
+;; so for safety's sake, we apply this restriction to all targets.
(define_mode_attr recip_condition
- [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
+ [(SF "ISA_HAS_FP4")
+ (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
+ (V2SF "TARGET_SB1")])
;; This code iterator allows all branch instructions to be generated from
;; a single define_expand template.
;; to use the same template.
(define_code_iterator any_extend [sign_extend zero_extend])
+;; This code iterator allows the two right shift instructions to be
+;; generated from the same template.
+(define_code_iterator any_shiftrt [ashiftrt lshiftrt])
+
;; This code iterator allows the three shift instructions to be generated
;; from the same template.
(define_code_iterator any_shift [ashift ashiftrt lshiftrt])
+;; This code iterator allows unsigned and signed division to be generated
+;; from the same template.
+(define_code_iterator any_div [div udiv])
+
;; This code iterator allows all native floating-point comparisons to be
;; generated from the same template.
(define_code_iterator fcond [unordered uneq unlt unle eq lt le])
;; by swapping the operands.
(define_code_iterator swapped_fcond [ge gt unge ungt])
+;; Equality operators.
+(define_code_iterator equality_op [eq ne])
+
+;; These code iterators allow the signed and unsigned scc operations to use
+;; the same template.
+(define_code_iterator any_gt [gt gtu])
+(define_code_iterator any_ge [ge geu])
+(define_code_iterator any_lt [lt ltu])
+(define_code_iterator any_le [le leu])
+
;; <u> expands to an empty string when doing a signed operation and
;; "u" when doing an unsigned operation.
-(define_code_attr u [(sign_extend "") (zero_extend "u")])
+(define_code_attr u [(sign_extend "") (zero_extend "u")
+ (div "") (udiv "u")
+ (gt "") (gtu "u")
+ (ge "") (geu "u")
+ (lt "") (ltu "u")
+ (le "") (leu "u")])
;; <su> is like <u>, but the signed form expands to "s" rather than "".
(define_code_attr su [(sign_extend "s") (zero_extend "u")])
(lshiftrt "lshr")
(ior "ior")
(xor "xor")
- (and "and")])
+ (and "and")
+ (plus "add")
+ (minus "sub")])
;; <insn> expands to the name of the insn that implements a particular code.
(define_code_attr insn [(ashift "sll")
(lshiftrt "srl")
(ior "or")
(xor "xor")
- (and "and")])
+ (and "and")
+ (plus "addu")
+ (minus "subu")])
+
+;; <immediate_insn> expands to the name of the insn that implements
+;; a particular code to operate on immediate values.
+(define_code_attr immediate_insn [(ior "ori")
+ (xor "xori")
+ (and "andi")])
;; <fcond> is the c.cond.fmt condition associated with a particular code.
(define_code_attr fcond [(unordered "un")
(unge "ule")
(ungt "ult")])
-;; Atomic fetch bitwise operations.
-(define_code_iterator fetchop_bit [ior xor and])
-
-;; <immediate_insn> expands to the name of the insn that implements
-;; a particular code to operate in immediate values.
-(define_code_attr immediate_insn [(ior "ori") (xor "xori") (and "andi")])
+;; The value of the bit when the branch is taken for branch_bit patterns.
+;; Comparison is always against zero so this depends on the operator.
+(define_code_attr bbv [(eq "0") (ne "1")])
+;; This is the inverse value of bbv.
+(define_code_attr bbinv [(eq "1") (ne "0")])
\f
;; .........................
;;
;; .........................
(define_delay (and (eq_attr "type" "branch")
- (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
+ (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (eq_attr "branch_likely" "yes"))
+ [(eq_attr "can_delay" "yes")
+ (nil)
+ (eq_attr "can_delay" "yes")])
+
+;; Branches that don't have likely variants do not annul on false.
+(define_delay (and (eq_attr "type" "branch")
+ (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
+ (eq_attr "branch_likely" "no"))
[(eq_attr "can_delay" "yes")
(nil)
- (and (eq_attr "branch_likely" "yes")
- (eq_attr "can_delay" "yes"))])
+ (nil)])
(define_delay (eq_attr "type" "jump")
[(eq_attr "can_delay" "yes")
(define_cpu_unit "alu" "alu")
(define_cpu_unit "imuldiv" "imuldiv")
+;; Ghost instructions produce no real code and introduce no hazards.
+;; They exist purely to express an effect on dataflow.
+(define_insn_reservation "ghost" 0
+ (eq_attr "type" "ghost")
+ "nothing")
+
(include "4k.md")
(include "5k.md")
(include "20kc.md")
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
+(include "xlr.md")
+(include "loongson2ef.md")
(include "generic.md")
\f
;;
if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
&& operands[1] == const0_rtx)
{
- mips_gen_conditional_trap (operands);
+ mips_expand_conditional_trap (GET_CODE (operands[0]));
DONE;
}
- else
- FAIL;
+ FAIL;
})
(define_insn "*conditional_trap<mode>"
;; simply adding a constant to a register.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0x7f
&& INTVAL (operands[1]) <= 0x7f + 0x7f)
|| (INTVAL (operands[1]) < - 0x80
})
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (match_operand:SI 1 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (match_operand:SI 1 "d_operand")
(match_operand:SI 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && REG_P (operands[1])
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0x7f)
|| (INTVAL (operands[2]) < - 0x8
})
(define_split
- [(set (match_operand:DI 0 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
(plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) > 0xf
&& INTVAL (operands[1]) <= 0xf + 0xf)
|| (INTVAL (operands[1]) < - 0x10
})
(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
+ (plus:DI (match_operand:DI 1 "d_operand")
(match_operand:DI 2 "const_int_operand")))]
"TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && REG_P (operands[1])
- && M16_REG_P (REGNO (operands[1]))
&& REGNO (operands[0]) != REGNO (operands[1])
- && GET_CODE (operands[2]) == CONST_INT
&& ((INTVAL (operands[2]) > 0x7
&& INTVAL (operands[2]) <= 0x7 + 0xf)
|| (INTVAL (operands[2]) < - 0x8
;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively.
-(define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))]
+(define_expand "mul<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (mult:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "register_operand")))]
""
{
- if (ISA_HAS_MUL3)
- emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+ if (ISA_HAS_<D>MUL3)
+ emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
else if (TARGET_FIX_R4000)
- emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_expand "muldi3"
- [(set (match_operand:DI 0 "register_operand")
- (mult:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))]
- "TARGET_64BIT"
-{
- if (TARGET_FIX_R4000)
- emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
else
- emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
+ emit_insn
+ (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
DONE;
})
-(define_insn "mulsi3_mult3"
+(define_insn "mulsi3_mul3"
[(set (match_operand:SI 0 "register_operand" "=d,l")
(mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d")))
- (clobber (match_scratch:SI 3 "=h,h"))
- (clobber (match_scratch:SI 4 "=l,X"))]
+ (clobber (match_scratch:SI 3 "=l,X"))]
"ISA_HAS_MUL3"
{
if (which_alternative == 1)
[(set_attr "type" "imul3,imul")
(set_attr "mode" "SI")])
+(define_insn "muldi3_mul3"
+ [(set (match_operand:DI 0 "register_operand" "=d,l")
+ (mult:DI (match_operand:DI 1 "register_operand" "d,d")
+ (match_operand:DI 2 "register_operand" "d,d")))
+ (clobber (match_scratch:DI 3 "=l,X"))]
+ "ISA_HAS_DMUL3"
+{
+ if (which_alternative == 1)
+ return "dmult\t%1,%2";
+ return "dmul\t%0,%1,%2";
+}
+ [(set_attr "type" "imul3,imul")
+ (set_attr "mode" "DI")])
+
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
;; if it can set the GPR directly.
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
-;; Operand 3: HI
-;; Operand 4: GPR (destination)
+;; Operand 3: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
(clobber (scratch:SI))])
- (set (match_operand:SI 4 "register_operand")
- (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
[(parallel
- [(set (match_dup 4)
+ [(set (match_dup 3)
(mult:SI (match_dup 1)
(match_dup 2)))
- (clobber (match_dup 3))
(clobber (match_dup 0))])])
(define_insn "mul<mode>3_internal"
[(set (match_operand:GPR 0 "register_operand" "=l")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "register_operand" "d")))
- (clobber (match_scratch:GPR 3 "=h"))]
+ (match_operand:GPR 2 "register_operand" "d")))]
"!TARGET_FIX_R4000"
"<d>mult\t%1,%2"
[(set_attr "type" "imul")
[(set (match_operand:GPR 0 "register_operand" "=d")
(mult:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (clobber (match_scratch:GPR 3 "=h"))
- (clobber (match_scratch:GPR 4 "=l"))]
+ (clobber (match_scratch:GPR 3 "=l"))]
"TARGET_FIX_R4000"
"<d>mult\t%1,%2\;mflo\t%0"
[(set_attr "type" "imul")
;; Operand 0: LO
;; Operand 1: GPR (1st multiplication operand)
;; Operand 2: GPR (2nd multiplication operand)
-;; Operand 3: HI
-;; Operand 4: GPR (destination)
+;; Operand 3: GPR (destination)
(define_peephole2
- [(parallel
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))])
- (set (match_operand:SI 4 "register_operand")
- (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
+ [(set (match_operand:SI 0 "lo_operand")
+ (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand")))
+ (set (match_operand:SI 3 "d_operand")
+ (match_dup 0))]
"ISA_HAS_MACC && !ISA_HAS_MUL3"
[(set (match_dup 0)
(const_int 0))
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
(match_dup 0)))
- (set (match_dup 4)
+ (set (match_dup 3)
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
- (match_dup 0)))
- (clobber (match_dup 3))])])
+ (match_dup 0)))])])
;; Multiply-accumulate patterns
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
(match_operand:SI 2 "register_operand" "d,d,d"))
(match_operand:SI 3 "register_operand" "0,l,*d")))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,3,l"))
- (clobber (match_scratch:SI 6 "=X,X,&d"))]
+ (clobber (match_scratch:SI 4 "=X,3,l"))
+ (clobber (match_scratch:SI 5 "=X,X,&d"))]
"(TARGET_MIPS3900
|| GENERATE_MADD_MSUB)
&& !TARGET_MIPS16"
(set_attr "mode" "SI")
(set_attr "length" "4,4,8")])
-;; Split the above insn if we failed to get LO allocated.
+;; Split *mul_acc_si if both the source and destination accumulator
+;; values are GPRs.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
- (match_operand:SI 3 "register_operand")))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[3]))"
- [(parallel [(set (match_dup 6)
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_operand:SI 3 "d_operand")))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed"
+ [(parallel [(set (match_dup 5)
(mult:SI (match_dup 1) (match_dup 2)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])
- (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
"")
-;; Splitter to copy result of MADD to a general register
+;; Split *mul_acc_si if the destination accumulator value is in a GPR
+;; and the source accumulator value is in LO.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
- (match_operand:SI 3 "register_operand")))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[3]) == LO_REGNUM"
+ [(set (match_operand:SI 0 "d_operand")
+ (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
+ (match_operand:SI 2 "d_operand"))
+ (match_operand:SI 3 "lo_operand")))
+ (clobber (match_dup 3))
+ (clobber (scratch:SI))]
+ "reload_completed"
[(parallel [(set (match_dup 3)
(plus:SI (mult:SI (match_dup 1) (match_dup 2))
(match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
- "")
+ (clobber (scratch:SI))
+ (clobber (scratch:SI))])
+ (set (match_dup 0) (match_dup 3))])
(define_insn "*macc"
[(set (match_operand:SI 0 "register_operand" "=l,d")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))
(match_operand:SI 3 "register_operand" "0,l")))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,3"))]
+ (clobber (match_scratch:SI 4 "=X,3"))]
"ISA_HAS_MACC"
{
if (which_alternative == 1)
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,1"))]
+ (clobber (match_scratch:SI 4 "=X,1"))]
"ISA_HAS_MSAC"
{
if (which_alternative == 1)
(minus:SI (match_operand:SI 1 "register_operand" "0,l")
(mult:SI (match_operand:SI 2 "register_operand" "d,d")
(match_operand:SI 3 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 4 "=h,h"))
- (clobber (match_scratch:SI 5 "=X,1"))
- (clobber (match_scratch:SI 6 "=d,d"))]
+ (clobber (match_scratch:SI 4 "=X,1"))
+ (clobber (match_scratch:SI 5 "=d,d"))]
"ISA_HAS_MACC && !ISA_HAS_MSAC"
"#"
"&& reload_completed"
- [(set (match_dup 6)
+ [(set (match_dup 5)
(neg:SI (match_dup 3)))
(parallel
[(set (match_dup 0)
(plus:SI (mult:SI (match_dup 2)
- (match_dup 6))
+ (match_dup 5))
(match_dup 1)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])]
+ (clobber (match_dup 4))])]
""
[(set_attr "type" "imadd")
(set_attr "length" "8")])
(set (match_operand:SI 3 "register_operand" "=d")
(plus:SI (mult:SI (match_dup 1)
(match_dup 2))
- (match_dup 0)))
- (clobber (match_scratch:SI 4 "=h"))]
+ (match_dup 0)))]
"ISA_HAS_MACC && reload_completed"
"macc\t%3,%1,%2"
[(set_attr "type" "imadd")
(set (match_operand:SI 3 "register_operand" "=d")
(minus:SI (match_dup 0)
(mult:SI (match_dup 1)
- (match_dup 2))))
- (clobber (match_scratch:SI 4 "=h"))]
+ (match_dup 2))))]
"ISA_HAS_MSAC && reload_completed"
"msac\t%3,%1,%2"
[(set_attr "type" "imadd")
;;
;; Operand 0: LO
;; Operand 1: macc/msac
-;; Operand 2: HI
-;; Operand 3: GPR (destination)
+;; Operand 2: GPR (destination)
(define_peephole2
[(parallel
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "lo_operand")
(match_operand:SI 1 "macc_msac_operand"))
- (clobber (match_operand:SI 2 "register_operand"))
(clobber (scratch:SI))])
- (set (match_operand:SI 3 "register_operand")
- (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 2 "d_operand")
+ (match_dup 0))]
""
[(parallel [(set (match_dup 0)
(match_dup 1))
- (set (match_dup 3)
- (match_dup 1))
- (clobber (match_dup 2))])]
- "")
+ (set (match_dup 2)
+ (match_dup 1))])])
;; When we have a three-address multiplication instruction, it should
;; be faster to do a separate multiply and add, rather than moving
;; Operand 2: GPR (addend)
;; Operand 3: GPR (destination)
;; Operand 4: macc/msac
-;; Operand 5: HI
-;; Operand 6: new multiplication
-;; Operand 7: new addition/subtraction
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
- [(set (match_operand:SI 3 "register_operand")
+ [(set (match_operand:SI 3 "d_operand")
(match_operand:SI 4 "macc_msac_operand"))
- (clobber (match_operand:SI 5 "register_operand"))
(clobber (match_dup 1))])]
- "ISA_HAS_MUL3
- && true_regnum (operands[1]) == LO_REGNUM
- && peep2_reg_dead_p (2, operands[1])
- && GP_REG_P (true_regnum (operands[3]))"
+ "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
[(parallel [(set (match_dup 0)
- (match_dup 6))
- (clobber (match_dup 5))
+ (match_dup 5))
(clobber (match_dup 1))])
(set (match_dup 3)
- (match_dup 7))]
+ (match_dup 6))]
{
- operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
- operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
+ operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
operands[2], operands[0]);
})
;; Operand 1: LO
;; Operand 2: GPR (addend)
;; Operand 3: macc/msac
-;; Operand 4: HI
-;; Operand 5: GPR (destination)
-;; Operand 6: new multiplication
-;; Operand 7: new addition/subtraction
+;; Operand 4: GPR (destination)
+;; Operand 5: new multiplication
+;; Operand 6: new addition/subtraction
(define_peephole2
[(match_scratch:SI 0 "d")
- (set (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand"))
+ (set (match_operand:SI 1 "lo_operand")
+ (match_operand:SI 2 "d_operand"))
(match_dup 0)
(parallel
[(set (match_dup 1)
(match_operand:SI 3 "macc_msac_operand"))
- (clobber (match_operand:SI 4 "register_operand"))
(clobber (scratch:SI))])
(match_dup 0)
- (set (match_operand:SI 5 "register_operand")
- (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
+ (set (match_operand:SI 4 "d_operand")
+ (match_dup 1))]
"ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
[(parallel [(set (match_dup 0)
- (match_dup 6))
- (clobber (match_dup 4))
+ (match_dup 5))
(clobber (match_dup 1))])
- (set (match_dup 5)
- (match_dup 7))]
+ (set (match_dup 4)
+ (match_dup 6))]
{
- operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
- operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
+ operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
operands[2], operands[0]);
})
(minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
(mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
(match_operand:SI 3 "register_operand" "d,d,d"))))
- (clobber (match_scratch:SI 4 "=h,h,h"))
- (clobber (match_scratch:SI 5 "=X,1,l"))
- (clobber (match_scratch:SI 6 "=X,X,&d"))]
+ (clobber (match_scratch:SI 4 "=X,1,l"))
+ (clobber (match_scratch:SI 5 "=X,X,&d"))]
"GENERATE_MADD_MSUB"
"@
msub\t%2,%3
(set_attr "mode" "SI")
(set_attr "length" "4,8,8")])
-;; Split the above insn if we failed to get LO allocated.
+;; Split *mul_sub_si if both the source and destination accumulator
+;; values are GPRs.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (mult:SI (match_operand:SI 2 "register_operand")
- (match_operand:SI 3 "register_operand"))))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && GP_REG_P (true_regnum (operands[1]))"
- [(parallel [(set (match_dup 6)
+ [(set (match_operand:SI 0 "d_operand")
+ (minus:SI (match_operand:SI 1 "d_operand")
+ (mult:SI (match_operand:SI 2 "d_operand")
+ (match_operand:SI 3 "d_operand"))))
+ (clobber (match_operand:SI 4 "lo_operand"))
+ (clobber (match_operand:SI 5 "d_operand"))]
+ "reload_completed"
+ [(parallel [(set (match_dup 5)
(mult:SI (match_dup 2) (match_dup 3)))
- (clobber (match_dup 4))
- (clobber (match_dup 5))])
- (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
+ (clobber (match_dup 4))])
+ (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
"")
-;; Splitter to copy result of MSUB to a general register
+;; Split *mul_acc_si if the destination accumulator value is in a GPR
+;; and the source accumulator value is in LO.
(define_split
- [(set (match_operand:SI 0 "register_operand")
- (minus:SI (match_operand:SI 1 "register_operand")
- (mult:SI (match_operand:SI 2 "register_operand")
- (match_operand:SI 3 "register_operand"))))
- (clobber (match_scratch:SI 4))
- (clobber (match_scratch:SI 5))
- (clobber (match_scratch:SI 6))]
- "reload_completed && !TARGET_DEBUG_D_MODE
- && GP_REG_P (true_regnum (operands[0]))
- && true_regnum (operands[1]) == LO_REGNUM"
+ [(set (match_operand:SI 0 "d_operand")
+ (minus:SI (match_operand:SI 1 "lo_operand")
+ (mult:SI (match_operand:SI 2 "d_operand")
+ (match_operand:SI 3 "d_operand"))))
+ (clobber (match_dup 1))
+ (clobber (scratch:SI))]
+ "reload_completed"
[(parallel [(set (match_dup 1)
(minus:SI (match_dup 1)
(mult:SI (match_dup 2) (match_dup 3))))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])
- (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
+ (clobber (scratch:SI))
+ (clobber (scratch:SI))])
+ (set (match_dup 0) (match_dup 1))]
"")
(define_insn "*muls"
- [(set (match_operand:SI 0 "register_operand" "=l,d")
+ [(set (match_operand:SI 0 "register_operand" "=l,d")
(neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "register_operand" "d,d"))))
- (clobber (match_scratch:SI 3 "=h,h"))
- (clobber (match_scratch:SI 4 "=X,l"))]
+ (clobber (match_scratch:SI 3 "=X,l"))]
"ISA_HAS_MULS"
"@
muls\t$0,%1,%2
[(set_attr "type" "imul,imul3")
(set_attr "mode" "SI")])
-;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
-
(define_expand "<u>mulsidi3"
- [(parallel
- [(set (match_operand:DI 0 "register_operand")
- (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
- (any_extend:DI (match_operand:SI 2 "register_operand"))))
- (clobber (scratch:DI))
- (clobber (scratch:DI))
- (clobber (scratch:DI))])]
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
+ (any_extend:DI (match_operand:SI 2 "register_operand"))))]
"!TARGET_64BIT || !TARGET_FIX_R4000"
{
- if (!TARGET_64BIT)
- {
- if (!TARGET_FIX_R4000)
- emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
- operands[2]));
- else
- emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
+ if (TARGET_64BIT)
+ emit_insn (gen_<u>mulsidi3_64bit (operands[0], operands[1], operands[2]));
+ else if (TARGET_FIX_R4000)
+ emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
+ operands[2]));
+ else
+ emit_insn (gen_<u>mulsidi3_32bit (operands[0], operands[1], operands[2]));
+ DONE;
})
-(define_insn "<u>mulsidi3_32bit_internal"
+(define_insn "<u>mulsidi3_32bit"
[(set (match_operand:DI 0 "register_operand" "=x")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(clobber (match_scratch:DI 3 "=x"))]
"!TARGET_64BIT && TARGET_FIX_R4000"
- "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
+ "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "12")])
-(define_insn_and_split "*<u>mulsidi3_64bit"
+(define_insn_and_split "<u>mulsidi3_64bit"
[(set (match_operand:DI 0 "register_operand" "=d")
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
- (clobber (match_scratch:DI 3 "=l"))
- (clobber (match_scratch:DI 4 "=h"))
- (clobber (match_scratch:DI 5 "=d"))]
+ (clobber (match_scratch:TI 3 "=x"))
+ (clobber (match_scratch:DI 4 "=d"))]
"TARGET_64BIT && !TARGET_FIX_R4000"
"#"
"&& reload_completed"
- [(parallel
- [(set (match_dup 3)
- (sign_extend:DI
- (mult:SI (match_dup 1)
- (match_dup 2))))
- (set (match_dup 4)
- (ashiftrt:DI
- (mult:DI (any_extend:DI (match_dup 1))
- (any_extend:DI (match_dup 2)))
- (const_int 32)))])
-
- ;; OP5 <- LO, OP0 <- HI
- (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
- (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
-
- ;; Zero-extend OP5.
- (set (match_dup 5)
- (ashift:DI (match_dup 5)
+ [(set (match_dup 3)
+ (unspec:TI [(mult:DI (any_extend:DI (match_dup 1))
+ (any_extend:DI (match_dup 2)))]
+ UNSPEC_SET_HILO))
+
+ ;; OP4 <- LO, OP0 <- HI
+ (set (match_dup 4) (match_dup 5))
+ (set (match_dup 0) (unspec:DI [(match_dup 3)] UNSPEC_MFHI))
+
+ ;; Zero-extend OP4.
+ (set (match_dup 4)
+ (ashift:DI (match_dup 4)
(const_int 32)))
- (set (match_dup 5)
- (lshiftrt:DI (match_dup 5)
+ (set (match_dup 4)
+ (lshiftrt:DI (match_dup 4)
(const_int 32)))
;; Shift OP0 into place.
;; OR the two halves together
(set (match_dup 0)
(ior:DI (match_dup 0)
- (match_dup 5)))]
- ""
+ (match_dup 4)))]
+ { operands[5] = gen_rtx_REG (DImode, LO_REGNUM); }
[(set_attr "type" "imul")
(set_attr "mode" "SI")
(set_attr "length" "24")])
-(define_insn "*<u>mulsidi3_64bit_parts"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (sign_extend:DI
- (mult:SI (match_operand:SI 2 "register_operand" "d")
- (match_operand:SI 3 "register_operand" "d"))))
- (set (match_operand:DI 1 "register_operand" "=h")
- (ashiftrt:DI
- (mult:DI (any_extend:DI (match_dup 2))
- (any_extend:DI (match_dup 3)))
- (const_int 32)))]
+(define_insn "<u>mulsidi3_64bit_hilo"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (unspec:TI
+ [(mult:DI
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
+ UNSPEC_SET_HILO))]
"TARGET_64BIT && !TARGET_FIX_R4000"
- "mult<u>\t%2,%3"
+ "mult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
(any_extend:DI (match_operand:SI 2 "register_operand")))
(const_int 32))))]
- "ISA_HAS_MULHI || !TARGET_FIX_R4000"
+ ""
{
if (ISA_HAS_MULHI)
emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
DONE;
})
-(define_insn "<su>mulsi3_highpart_internal"
- [(set (match_operand:SI 0 "register_operand" "=h")
+(define_insn_and_split "<su>mulsi3_highpart_internal"
+ [(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(const_int 32))))
(clobber (match_scratch:SI 3 "=l"))]
- "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
- "mult<u>\t%1,%2"
+ "!ISA_HAS_MULHI"
+ { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
+ "&& reload_completed && !TARGET_FIX_R4000"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_ti (operands[0], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhisi_di (operands[0], hilo));
+ }
+ DONE;
+}
[(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "SI")
+ (set_attr "length" "8")])
(define_insn "<su>mulsi3_highpart_mulhi_internal"
- [(set (match_operand:SI 0 "register_operand" "=h,d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(mult:DI
- (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
- (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=l,l"))
- (clobber (match_scratch:SI 4 "=X,h"))]
+ (clobber (match_scratch:SI 3 "=l"))]
"ISA_HAS_MULHI"
- "@
- mult<u>\t%1,%2
- mulhi<u>\t%0,%1,%2"
- [(set_attr "type" "imul,imul3")
+ "mulhi<u>\t%0,%1,%2"
+ [(set_attr "type" "imul3")
(set_attr "mode" "SI")])
(define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
- [(set (match_operand:SI 0 "register_operand" "=h,d")
+ [(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI
(lshiftrt:DI
(neg:DI
(mult:DI
- (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
- (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
+ (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
+ (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
(const_int 32))))
- (clobber (match_scratch:SI 3 "=l,l"))
- (clobber (match_scratch:SI 4 "=X,h"))]
+ (clobber (match_scratch:SI 3 "=l"))]
"ISA_HAS_MULHI"
- "@
- mulshi<u>\t%.,%1,%2
- mulshi<u>\t%0,%1,%2"
- [(set_attr "type" "imul,imul3")
+ "mulshi<u>\t%0,%1,%2"
+ [(set_attr "type" "imul3")
(set_attr "mode" "SI")])
;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
;; errata MD(0), which says that dmultu does not always produce the
;; correct result.
-(define_insn "<su>muldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "=h")
+(define_insn_and_split "<su>muldi3_highpart"
+ [(set (match_operand:DI 0 "register_operand" "=d")
(truncate:DI
(lshiftrt:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
- (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
(const_int 64))))
(clobber (match_scratch:DI 3 "=l"))]
- "TARGET_64BIT && !TARGET_FIX_R4000
+ "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
+ "&& reload_completed && !TARGET_FIX_R4000"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhidi_ti (operands[0], hilo));
+ DONE;
+}
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")
+ (set_attr "length" "8")])
+
+(define_expand "<u>mulditi3"
+ [(set (match_operand:TI 0 "register_operand")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
+ (any_extend:TI (match_operand:DI 2 "register_operand"))))]
+ "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+{
+ if (TARGET_FIX_R4000)
+ emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
+ operands[2]));
+ DONE;
+})
+
+(define_insn "<u>mulditi3_internal"
+ [(set (match_operand:TI 0 "register_operand" "=x")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
+ "TARGET_64BIT
+ && !TARGET_FIX_R4000
&& !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
"dmult<u>\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
+(define_insn "<u>mulditi3_r4000"
+ [(set (match_operand:TI 0 "register_operand" "=d")
+ (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
+ (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
+ (clobber (match_scratch:TI 3 "=x"))]
+ "TARGET_64BIT
+ && TARGET_FIX_R4000
+ && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
+ "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")
+ (set_attr "length" "12")])
+
;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
;; instruction. The HI/LO registers are used as a 64-bit accumulator.
[(set (match_operand:SI 0 "register_operand" "+l")
(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))
- (match_dup 0)))
- (clobber (match_scratch:SI 3 "=h"))]
+ (match_dup 0)))]
"TARGET_MAD"
"mad\t%1,%2"
[(set_attr "type" "imadd")
;; Floating point multiply accumulate instructions.
-(define_insn "*madd<mode>"
+(define_insn "*madd4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"madd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*msub<mode>"
+(define_insn "*madd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "madd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*msub4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_FP4 && TARGET_FUSED_MADD"
+ "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
"msub.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmadd<mode>"
+(define_insn "*msub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
+ "msub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (plus:ANYF
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmadd<mode>_fastmath"
+(define_insn "*nmadd3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (plus:ANYF
+ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmadd4<mode>_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
(match_operand:ANYF 2 "register_operand" "f"))
(match_operand:ANYF 3 "register_operand" "f")))]
- "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
"nmadd.<fmt>\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmsub<mode>"
+(define_insn "*nmadd3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
+ (match_operand:ANYF 2 "register_operand" "f"))
+ (match_operand:ANYF 3 "register_operand" "0")))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmadd.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(neg:ANYF (minus:ANYF
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))
(match_operand:ANYF 1 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
&& HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-(define_insn "*nmsub<mode>_fastmath"
+(define_insn "*nmsub3<mode>"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (neg:ANYF (minus:ANYF
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "f"))
+ (match_operand:ANYF 1 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
+(define_insn "*nmsub4<mode>_fastmath"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(minus:ANYF
(match_operand:ANYF 1 "register_operand" "f")
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
(match_operand:ANYF 3 "register_operand" "f"))))]
- "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
+ "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
+ && TARGET_FUSED_MADD
&& !HONOR_SIGNED_ZEROS (<MODE>mode)
&& !HONOR_NANS (<MODE>mode)"
"nmsub.<fmt>\t%0,%1,%2,%3"
[(set_attr "type" "fmadd")
(set_attr "mode" "<UNITMODE>")])
-\f
+
+(define_insn "*nmsub3<mode>_fastmath"
+ [(set (match_operand:ANYF 0 "register_operand" "=f")
+ (minus:ANYF
+ (match_operand:ANYF 1 "register_operand" "f")
+ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
+ (match_operand:ANYF 3 "register_operand" "0"))))]
+ "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
+ && TARGET_FUSED_MADD
+ && !HONOR_SIGNED_ZEROS (<MODE>mode)
+ && !HONOR_NANS (<MODE>mode)"
+ "nmsub.<fmt>\t%0,%1,%2"
+ [(set_attr "type" "fmadd")
+ (set_attr "mode" "<UNITMODE>")])
+
;;
;; ....................
;;
"<divide_condition>"
{
if (const_1_operand (operands[1], <MODE>mode))
- if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+ if (!(<recip_condition> && flag_unsafe_math_optimizations))
operands[1] = force_reg (<MODE>mode, operands[1]);
})
;; VR4120 errata MD(A1): signed division instructions do not work correctly
;; with negative operands. We use special libgcc functions instead.
-(define_insn "divmod<mode>4"
+(define_insn_and_split "divmod<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(div:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (set (match_operand:GPR 3 "register_operand" "=h")
+ (set (match_operand:GPR 3 "register_operand" "=d")
(mod:GPR (match_dup 1)
(match_dup 2)))]
"!TARGET_FIX_VR4120"
- { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
- [(set_attr "type" "idiv")
- (set_attr "mode" "<MODE>")])
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_divmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
+ }
+ DONE;
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
-(define_insn "udivmod<mode>4"
+(define_insn_and_split "udivmod<mode>4"
[(set (match_operand:GPR 0 "register_operand" "=l")
(udiv:GPR (match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "register_operand" "d")))
- (set (match_operand:GPR 3 "register_operand" "=h")
+ (set (match_operand:GPR 3 "register_operand" "=d")
(umod:GPR (match_dup 1)
(match_dup 2)))]
""
- { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+{
+ rtx hilo;
+
+ if (TARGET_64BIT)
+ {
+ hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_ti (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_ti (operands[3], hilo));
+ }
+ else
+ {
+ hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
+ emit_insn (gen_udivmod<mode>4_hilo_di (hilo, operands[1], operands[2]));
+ emit_insn (gen_mfhi<mode>_di (operands[3], hilo));
+ }
+ DONE;
+}
+ [(set_attr "type" "idiv")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+
+(define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO
+ [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d"))]
+ UNSPEC_SET_HILO))]
+ ""
+ { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
[(set_attr "type" "idiv")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
\f
;;
;; ....................
"<d>clz\t%0,%1"
[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
+
+;;
+;; ...................
+;;
+;; Count number of set bits.
+;;
+;; ...................
+;;
+
+(define_insn "popcount<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
+ "ISA_HAS_POP"
+ "<d>pop\t%0,%1"
+ [(set_attr "type" "pop")
+ (set_attr "mode" "<MODE>")])
\f
;;
;; ....................
"@
sll\t%0,%1,0
sw\t%1,%0"
- [(set_attr "type" "shift,store")
- (set_attr "mode" "SI")
- (set_attr "extended_mips16" "yes,*")])
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
(define_insn "truncdihi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
"@
sll\t%0,%1,0
sh\t%1,%0"
- [(set_attr "type" "shift,store")
- (set_attr "mode" "SI")
- (set_attr "extended_mips16" "yes,*")])
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
(define_insn "truncdiqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
"@
sll\t%0,%1,0
sb\t%1,%0"
- [(set_attr "type" "shift,store")
- (set_attr "mode" "SI")
- (set_attr "extended_mips16" "yes,*")])
+ [(set_attr "move_type" "sll0,store")
+ (set_attr "mode" "SI")])
;; Combiner patterns to optimize shift/truncate combinations.
-(define_insn ""
+(define_insn "*ashr_trunc<mode>"
[(set (match_operand:SUBDI 0 "register_operand" "=d")
(truncate:SUBDI
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "const_arith_operand" ""))))]
- "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
+ "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
"dsra\t%0,%1,%2"
[(set_attr "type" "shift")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-(define_insn ""
+(define_insn "*lshr32_trunc<mode>"
[(set (match_operand:SUBDI 0 "register_operand" "=d")
(truncate:SUBDI
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
"TARGET_64BIT && !TARGET_MIPS16"
"dsra\t%0,%1,32"
[(set_attr "type" "shift")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
+;; Logical shift by 32 or more results in proper SI values so
+;; truncation is removed by the middle end.
+(define_insn "*<optab>_trunc<mode>_exts"
+ [(set (match_operand:SUBDI 0 "register_operand" "=d")
+ (truncate:SUBDI
+ (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "const_arith_operand" ""))))]
+ "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
+ "exts\t%0,%1,%2,31"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
-;; Combiner patterns for truncate/sign_extend combinations. They use
-;; the shift/truncate patterns above.
+;; Combiner patterns for truncate/sign_extend combinations. The SI versions
+;; use the shift/truncate patterns above.
-(define_insn_and_split ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (sign_extend:SI
- (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
+(define_insn_and_split "*extenddi_truncate<mode>"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (sign_extend:DI
+ (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
- (const_int 48)))
+ (match_dup 3)))
(set (match_dup 0)
- (truncate:SI (ashiftrt:DI (match_dup 2)
- (const_int 48))))]
- { operands[2] = gen_lowpart (DImode, operands[0]); })
+ (ashiftrt:DI (match_dup 2)
+ (match_dup 3)))]
+{
+ operands[2] = gen_lowpart (DImode, operands[0]);
+ operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
+})
-(define_insn_and_split ""
+(define_insn_and_split "*extendsi_truncate<mode>"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI
- (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
+ (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"#"
"&& reload_completed"
[(set (match_dup 2)
(ashift:DI (match_dup 1)
- (const_int 56)))
+ (match_dup 3)))
(set (match_dup 0)
(truncate:SI (ashiftrt:DI (match_dup 2)
- (const_int 56))))]
- { operands[2] = gen_lowpart (DImode, operands[0]); })
-
+ (match_dup 3))))]
+{
+ operands[2] = gen_lowpart (DImode, operands[0]);
+ operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
+})
;; Combiner patterns to optimize truncate/zero_extend combinations.
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (truncate:HI
- (match_operand:DI 1 "register_operand" "d"))))]
+(define_insn "*zero_extend<mode>_trunchi"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR
+ (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xffff"
- [(set_attr "type" "logical")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d")
- (zero_extend:SI (truncate:QI
- (match_operand:DI 1 "register_operand" "d"))))]
+(define_insn "*zero_extend<mode>_truncqi"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (zero_extend:GPR
+ (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "logical")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "logical")
+ (set_attr "mode" "<MODE>")])
(define_insn ""
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (truncate:QI
- (match_operand:DI 1 "register_operand" "d"))))]
+ (zero_extend:HI
+ (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "logical")
- (set_attr "mode" "HI")])
+ [(set_attr "type" "logical")
+ (set_attr "mode" "HI")])
\f
;;
;; ....................
(set (match_dup 0)
(lshiftrt:DI (match_dup 0) (const_int 32)))]
{ operands[1] = gen_lowpart (DImode, operands[1]); }
- [(set_attr "type" "multi,load")
- (set_attr "mode" "DI")
- (set_attr "length" "8,*")])
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "DI")])
;; Combine is not allowed to convert this insn into a zero_extendsidi2
;; because of TRULY_NOOP_TRUNCATION.
(set (match_dup 0)
(lshiftrt:DI (match_dup 0) (const_int 32)))]
""
- [(set_attr "type" "multi,load")
- (set_attr "mode" "DI")
- (set_attr "length" "8,*")])
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "DI")])
(define_expand "zero_extend<SHORT:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand")
"@
andi\t%0,%1,<SHORT:mask>
l<SHORT:size>u\t%0,%1"
- [(set_attr "type" "logical,load")
+ [(set_attr "move_type" "andi,load")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
(zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
"GENERATE_MIPS16E"
"ze<SHORT:size>\t%0"
- [(set_attr "type" "arith")
+ ;; This instruction is effectively a special encoding of ANDI.
+ [(set_attr "move_type" "andi")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
(zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
"TARGET_MIPS16"
"l<SHORT:size>u\t%0,%1"
- [(set_attr "type" "load")
+ [(set_attr "move_type" "load")
(set_attr "mode" "<GPR:MODE>")])
(define_expand "zero_extendqihi2"
"@
andi\t%0,%1,0x00ff
lbu\t%0,%1"
- [(set_attr "type" "logical,load")
+ [(set_attr "move_type" "andi,load")
(set_attr "mode" "HI")])
(define_insn "*zero_extendqihi2_mips16"
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_MIPS16"
"lbu\t%0,%1"
- [(set_attr "type" "load")
+ [(set_attr "move_type" "load")
(set_attr "mode" "HI")])
\f
;;
emit_note (NOTE_INSN_DELETED);
DONE;
}
- [(set_attr "type" "arith,load")
+ [(set_attr "move_type" "move,load")
(set_attr "mode" "DI")])
(define_expand "extend<SHORT:mode><GPR:mode>2"
"@
se<SHORT:size>\t%0
l<SHORT:size>\t%0,%1"
- [(set_attr "type" "signext,load")
+ [(set_attr "move_type" "signext,load")
(set_attr "mode" "<GPR:MODE>")])
(define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
- GET_MODE_BITSIZE (<SHORT:MODE>mode));
}
- [(set_attr "type" "arith,load")
- (set_attr "mode" "<GPR:MODE>")
- (set_attr "length" "8,*")])
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "<GPR:MODE>")])
(define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
"@
se<SHORT:size>\t%0,%1
l<SHORT:size>\t%0,%1"
- [(set_attr "type" "signext,load")
+ [(set_attr "move_type" "signext,load")
(set_attr "mode" "<GPR:MODE>")])
(define_expand "extendqihi2"
"@
seb\t%0
lb\t%0,%1"
- [(set_attr "type" "signext,load")
+ [(set_attr "move_type" "signext,load")
(set_attr "mode" "SI")])
(define_insn_and_split "*extendqihi2"
operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
- GET_MODE_BITSIZE (QImode));
}
- [(set_attr "type" "multi,load")
- (set_attr "mode" "SI")
- (set_attr "length" "8,*")])
+ [(set_attr "move_type" "shift_shift,load")
+ (set_attr "mode" "SI")])
(define_insn "*extendqihi2_seb"
[(set (match_operand:HI 0 "register_operand" "=d,d")
"@
seb\t%0,%1
lb\t%0,%1"
- [(set_attr "type" "signext,load")
+ [(set_attr "move_type" "signext,load")
(set_attr "mode" "SI")])
(define_insn "extendsfdf2"
"trunc.w.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "cnv_mode" "D2I")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "D2I")])
(define_insn "fix_truncdfsi2_macro"
[(set (match_operand:SI 0 "register_operand" "=f")
"trunc.w.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "cnv_mode" "S2I")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "S2I")])
(define_insn "fix_truncsfsi2_macro"
[(set (match_operand:SI 0 "register_operand" "=f")
"trunc.l.d %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "cnv_mode" "D2I")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "D2I")])
(define_insn "fix_truncsfdi2"
"trunc.l.s %0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "cnv_mode" "S2I")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "S2I")])
(define_insn "floatsidf2"
"cvt.d.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "cnv_mode" "I2D")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "I2D")])
(define_insn "floatdidf2"
"cvt.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
- (set_attr "cnv_mode" "I2D")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "I2D")])
(define_insn "floatsisf2"
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "cnv_mode" "I2S")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "I2S")])
(define_insn "floatdisf2"
"cvt.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
- (set_attr "cnv_mode" "I2S")
- (set_attr "length" "4")])
+ (set_attr "cnv_mode" "I2S")])
(define_expand "fixuns_truncdfsi2"
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+ emit_use (stack_pointer_rtx);
DONE;
}
})
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+ emit_use (stack_pointer_rtx);
DONE;
})
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+ emit_use (stack_pointer_rtx);
DONE;
})
/* Allow REG_NOTES to be set on last insn (labels don't have enough
fields, and can't be used for REG_NOTES anyway). */
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+ emit_use (stack_pointer_rtx);
DONE;
})
\f
(define_expand "extv"
[(set (match_operand 0 "register_operand")
- (sign_extract (match_operand:QI 1 "memory_operand")
- (match_operand 2 "immediate_operand")
- (match_operand 3 "immediate_operand")))]
+ (sign_extract (match_operand 1 "nonimmediate_operand")
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
"!TARGET_MIPS16"
{
- if (mips_expand_unaligned_load (operands[0], operands[1],
- INTVAL (operands[2]),
- INTVAL (operands[3])))
+ if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
+ INTVAL (operands[2]),
+ INTVAL (operands[3])))
DONE;
+ else if (register_operand (operands[1], GET_MODE (operands[0]))
+ && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
+ {
+ if (GET_MODE (operands[0]) == DImode)
+ emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
+ operands[3]));
+ else
+ emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
+ operands[3]));
+ DONE;
+ }
else
FAIL;
})
+(define_insn "extv<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
+ "exts\t%0,%1,%3,%m2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
+
(define_expand "extzv"
[(set (match_operand 0 "register_operand")
(zero_extract (match_operand 1 "nonimmediate_operand")
- (match_operand 2 "immediate_operand")
- (match_operand 3 "immediate_operand")))]
+ (match_operand 2 "const_int_operand")
+ (match_operand 3 "const_int_operand")))]
"!TARGET_MIPS16"
{
- if (mips_expand_unaligned_load (operands[0], operands[1],
- INTVAL (operands[2]),
- INTVAL (operands[3])))
+ if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
+ INTVAL (operands[2]),
+ INTVAL (operands[3])))
DONE;
- else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
+ else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
+ INTVAL (operands[3])))
{
if (GET_MODE (operands[0]) == DImode)
emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
(define_insn "extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:SI 2 "immediate_operand" "I")
- (match_operand:SI 3 "immediate_operand" "I")))]
- "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" "")))]
+ "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
+ INTVAL (operands[3]))"
"<d>ext\t%0,%1,%3,%2"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
+(define_insn "*extzv_trunc<mode>_exts"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (truncate:GPR
+ (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand 2 "const_int_operand" "")
+ (match_operand 3 "const_int_operand" ""))))]
+ "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
+ "exts\t%0,%1,%3,31"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "<MODE>")])
+
(define_expand "insv"
[(set (zero_extract (match_operand 0 "nonimmediate_operand")
(match_operand 3 "reg_or_0_operand"))]
"!TARGET_MIPS16"
{
- if (mips_expand_unaligned_store (operands[0], operands[3],
- INTVAL (operands[1]),
- INTVAL (operands[2])))
+ if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
+ INTVAL (operands[1]),
+ INTVAL (operands[2])))
DONE;
- else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
+ else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
+ INTVAL (operands[2])))
{
if (GET_MODE (operands[0]) == DImode)
emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
(match_operand:SI 1 "immediate_operand" "I")
(match_operand:SI 2 "immediate_operand" "I"))
(match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
- "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
+ "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
+ INTVAL (operands[2]))"
"<d>ins\t%0,%z3,%2,%1"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")])
+;; Combiner pattern for cins (clear and insert bit field). We can
+;; implement mask-and-shift-left operation with this. Note that if
+;; the upper bit of the mask is set in an SImode operation, the mask
+;; itself will be sign-extended. mask_low_and_shift_len will
+;; therefore be greater than our threshold of 32.
+
+(define_insn "*cins<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (and:GPR
+ (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "const_int_operand" ""))
+ (match_operand:GPR 3 "const_int_operand" "")))]
+ "ISA_HAS_CINS
+ && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
+{
+ operands[3] =
+ GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
+ return "cins\t%0,%1,%2,%m3";
+}
+ [(set_attr "type" "shift")
+ (set_attr "mode" "<MODE>")])
+
;; Unaligned word moves generated by the bit field patterns.
;;
;; As far as the rtl is concerned, both the left-part and right-part
UNSPEC_LOAD_LEFT))]
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>l\t%0,%2"
- [(set_attr "type" "load")
+ [(set_attr "move_type" "load")
(set_attr "mode" "<MODE>")])
(define_insn "mov_<load>r"
UNSPEC_LOAD_RIGHT))]
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
"<load>r\t%0,%2"
- [(set_attr "type" "load")
+ [(set_attr "move_type" "load")
(set_attr "mode" "<MODE>")])
(define_insn "mov_<store>l"
UNSPEC_STORE_LEFT))]
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>l\t%z1,%2"
- [(set_attr "type" "store")
+ [(set_attr "move_type" "store")
(set_attr "mode" "<MODE>")])
(define_insn "mov_<store>r"
UNSPEC_STORE_RIGHT))]
"!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
"<store>r\t%z1,%2"
- [(set_attr "type" "store")
+ [(set_attr "move_type" "store")
(set_attr "mode" "<MODE>")])
;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
;; dsll32 op1,op1,0
;; daddu op1,op1,op0
(define_peephole2
- [(set (match_operand:DI 1 "register_operand")
+ [(set (match_operand:DI 1 "d_operand")
(high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
(match_scratch:DI 0 "d")]
"TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
;;
;; on MIPS16 targets.
(define_split
- [(set (match_operand:SI 0 "register_operand" "=d")
- (high:SI (match_operand:SI 1 "absolute_symbolic_operand" "")))]
+ [(set (match_operand:SI 0 "d_operand")
+ (high:SI (match_operand:SI 1 "absolute_symbolic_operand")))]
"TARGET_MIPS16 && reload_completed"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 16)))]
(define_insn_and_split "*got_disp<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
(match_operand:P 1 "got_disp_operand" ""))]
- "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
+ "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
"#"
"&& reload_completed"
- [(set (match_dup 0)
- (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
-{
- operands[2] = pic_offset_table_rtx;
- operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
-}
+ [(set (match_dup 0) (match_dup 2))]
+ { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
[(set_attr "got" "load")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "*got_page<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
(high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
- "TARGET_EXPLICIT_RELOCS"
+ "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
"#"
"&& reload_completed"
- [(set (match_dup 0)
- (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
-{
- operands[2] = pic_offset_table_rtx;
- operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
-}
+ [(set (match_dup 0) (match_dup 2))]
+ { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
[(set_attr "got" "load")
(set_attr "mode" "<MODE>")])
+;; Convenience expander that generates the rhs of a load_got<mode> insn.
+(define_expand "unspec_got<mode>"
+ [(unspec:P [(match_operand:P 0)
+ (match_operand:P 1)] UNSPEC_LOAD_GOT)])
+
;; Lower-level instructions for loading an address from the GOT.
;; We could use MEMs, but an unspec gives more optimization
;; opportunities.
UNSPEC_LOAD_GOT))]
""
"<load>\t%0,%R2(%1)"
- [(set_attr "type" "load")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "4")])
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
;; Instructions for adding the low 16 bits of an address to a register.
-;; Operand 2 is the address: print_operand works out which relocation
+;; Operand 2 is the address: mips_print_operand works out which relocation
;; should be applied.
(define_insn "*low<mode>"
"<d>addiu\t%0,%R2"
[(set_attr "type" "arith")
(set_attr "mode" "<MODE>")
- (set_attr "length" "8")])
+ (set_attr "extended_mips16" "yes")])
+
+;; Expose MIPS16 uses of the global pointer after reload if the function
+;; is responsible for setting up the register itself.
+(define_split
+ [(set (match_operand:GPR 0 "d_operand")
+ (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
+ "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
+ [(set (match_dup 0) (match_dup 1))]
+ { operands[1] = pic_offset_table_rtx; })
;; Allow combine to split complex const_int load sequences, using operand 2
;; to store the intermediate results. See move_operand for details.
""
[(const_int 0)]
{
- mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
+ mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
DONE;
})
(reg:GPR 31))]
"TARGET_MIPS16"
"<store>\t$31,%0"
- [(set_attr "type" "store")
+ [(set_attr "move_type" "store")
(set_attr "mode" "<MODE>")])
(define_insn "*movdi_32bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
- (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
- "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
- && (register_operand (operands[0], DImode)
- || reg_or_0_operand (operands[1], DImode))"
- { return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,load,mfc,store")
- (set_attr "mode" "DI")
- (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
-
-(define_insn "*movdi_gp32_fp64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m")
- (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f"))]
- "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
+ "!TARGET_64BIT && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
- (set_attr "mode" "DI")
- (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "DI")])
(define_insn "*movdi_32bit_mips16"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,multi,multi,multi,load,store,mfhilo")
- (set_attr "mode" "DI")
- (set_attr "length" "8,8,8,8,12,*,*,8")])
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "DI")])
(define_insn "*movdi_64bit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
- (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
+ (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
"TARGET_64BIT && !TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
- (set_attr "mode" "DI")
- (set_attr "length" "4,*,*,*,*,4,*,4,*,4,8,*,8,*")])
+ [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "DI")])
(define_insn "*movdi_64bit_mips16"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
- (match_operand:DI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
+ (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
"TARGET_64BIT && TARGET_MIPS16
&& (register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
- (set_attr "mode" "DI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
- (const_int 8)
- (const_int 12))
- (const_int 8)
- (const_string "*")
- (const_string "*")
- (const_string "*")])])
-
+ [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+ (set_attr "mode" "DI")])
;; On the mips16, we can split ld $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:DI 0 "register_operand")
+ [(set (match_operand:DI 0 "d_operand")
(mem:DI (plus:DI (match_dup 0)
(match_operand:DI 1 "const_int_operand"))))]
"TARGET_64BIT && TARGET_MIPS16 && reload_completed
&& !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x10)
|| (INTVAL (operands[1]) >= 32 * 8
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
- (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
+ (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
- (set_attr "mode" "SI")
- (set_attr "length" "4,*,*,*,*,4,*,4,*,4,4,4,4,4,*,4,*")])
+ [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore")
+ (set_attr "mode" "SI")])
(define_insn "*movsi_mips16"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m")
- (match_operand:SI 1 "move_operand" "d,d,y,K,N,kf,U,m,d"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
+ (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
"TARGET_MIPS16
&& (register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,move,move,arith,arith,load,const,load,store")
- (set_attr "mode" "SI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
- (const_int 8)
- (const_int 12))
- (const_int 8)
- (const_string "*")
- (const_string "*")
- (const_string "*")])])
+ [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo")
+ (set_attr "mode" "SI")])
;; On the mips16, we can split lw $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(mem:SI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32 * 4
;; instructions.
(define_split
- [(set (match_operand:SI 0 "register_operand")
+ [(set (match_operand:SI 0 "d_operand")
(match_operand:SI 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& INTVAL (operands[1]) >= 0x100
&& INTVAL (operands[1]) <= 0xff + 0x7f"
[(set (match_dup 0) (match_dup 1))
(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,move,load,store,mfc,mtc,fmove,fpload,fpstore")
- (set_attr "mode" "SI")
- (set_attr "length" "8,4,*,*,4,4,4,*,*")])
+ [(set_attr "move_type" "lui_movf,move,load,store,mfc,mtc,fmove,fpload,fpstore")
+ (set_attr "mode" "SI")])
;; Reload condition code registers. reload_incc and reload_outcc
;; both handle moves from arbitrary operands into condition code
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
+ mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
DONE;
})
(clobber (match_operand:TF 2 "register_operand" "=&f"))]
"ISA_HAS_8CC && TARGET_HARD_FLOAT"
{
- mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
+ mips_expand_fcc_reload (operands[0], operands[1], operands[2]);
DONE;
})
"ISA_HAS_LWXS"
"lwxs\t%0,%1(%2)"
[(set_attr "type" "load")
- (set_attr "mode" "SI")
- (set_attr "length" "4")])
+ (set_attr "mode" "SI")])
;; 16-bit Integer moves
})
(define_insn "*movhi_internal"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
- (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
- "@
- move\t%0,%1
- li\t%0,%1
- lhu\t%0,%1
- sh\t%z1,%0
- mfc1\t%0,%1
- mtc1\t%1,%0
- mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
- (set_attr "mode" "HI")
- (set_attr "length" "4,4,*,*,4,4,4")])
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "HI")])
(define_insn "*movhi_mips16"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
- (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
"TARGET_MIPS16
&& (register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode))"
- "@
- move\t%0,%1
- move\t%0,%1
- move\t%0,%1
- li\t%0,%1
- #
- lhu\t%0,%1
- sh\t%1,%0"
- [(set_attr "type" "move,move,move,arith,arith,load,store")
- (set_attr "mode" "HI")
- (set_attr_alternative "length"
- [(const_int 4)
- (const_int 4)
- (const_int 4)
- (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
- (const_int 4)
- (const_int 8))
- (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
- (const_int 8)
- (const_int 12))
- (const_string "*")
- (const_string "*")])])
-
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "HI")])
;; On the mips16, we can split lh $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:HI 0 "register_operand")
+ [(set (match_operand:HI 0 "d_operand")
(mem:HI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32 * 2
})
(define_insn "*movqi_internal"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*x")
- (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*d"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
"!TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
- "@
- move\t%0,%1
- li\t%0,%1
- lbu\t%0,%1
- sb\t%z1,%0
- mfc1\t%0,%1
- mtc1\t%1,%0
- mt%0\t%1"
- [(set_attr "type" "move,arith,load,store,mfc,mtc,mthilo")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,*,*,4,4,4")])
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "QI")])
(define_insn "*movqi_mips16"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
- (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
"TARGET_MIPS16
&& (register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
- "@
- move\t%0,%1
- move\t%0,%1
- move\t%0,%1
- li\t%0,%1
- #
- lbu\t%0,%1
- sb\t%1,%0"
- [(set_attr "type" "move,move,move,arith,arith,load,store")
- (set_attr "mode" "QI")
- (set_attr "length" "4,4,4,4,8,*,*")])
+ { return mips_output_move (operands[0], operands[1]); }
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "QI")])
;; On the mips16, we can split lb $r,N($r) into an add and a load,
;; when the original load is a 4 byte instruction but the add and the
;; load are 2 2 byte instructions.
(define_split
- [(set (match_operand:QI 0 "register_operand")
+ [(set (match_operand:QI 0 "d_operand")
(mem:QI (plus:SI (match_dup 0)
(match_operand:SI 1 "const_int_operand"))))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && REG_P (operands[0])
- && M16_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
&& ((INTVAL (operands[1]) < 0
&& INTVAL (operands[1]) >= -0x80)
|| (INTVAL (operands[1]) >= 32
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "SF")])
(define_insn "*movsf_softfloat"
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,load,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,*,*")])
+ [(set_attr "move_type" "move,load,store")
+ (set_attr "mode" "SF")])
(define_insn "*movsf_mips16"
[(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
&& (register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "move,move,move,load,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,4,*,*")])
-
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "SF")])
;; 64-bit floating point moves
DONE;
})
-(define_insn "*movdf_hardfloat_64bit"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
- (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
- && (register_operand (operands[0], DFmode)
- || reg_or_0_operand (operands[1], DFmode))"
- { return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "mode" "DF")
- (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
-
-;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
-(define_insn "*movdf_hardfloat_32bit"
+(define_insn "*movdf_hardfloat"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
(match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "mode" "DF")
- (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "DF")])
(define_insn "*movdf_softfloat"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
- (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
+ (match_operand:DF 1 "move_operand" "dG,m,dG"))]
"(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,load,store,mfc,mtc,fmove")
- (set_attr "mode" "DF")
- (set_attr "length" "8,*,*,4,4,4")])
+ [(set_attr "move_type" "move,load,store")
+ (set_attr "mode" "DF")])
(define_insn "*movdf_mips16"
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
&& (register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "multi,multi,multi,load,store")
- (set_attr "mode" "DF")
- (set_attr "length" "8,8,8,*,*")])
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "DF")])
+
+;; 128-bit integer moves
+
+(define_expand "movti"
+ [(set (match_operand:TI 0)
+ (match_operand:TI 1))]
+ "TARGET_64BIT"
+{
+ if (mips_legitimize_move (TImode, operands[0], operands[1]))
+ DONE;
+})
+
+(define_insn "*movti"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
+ (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
+ "TARGET_64BIT
+ && !TARGET_MIPS16
+ && (register_operand (operands[0], TImode)
+ || reg_or_0_operand (operands[1], TImode))"
+ "#"
+ [(set_attr "move_type" "move,const,load,store,mthilo,mfhilo")
+ (set_attr "mode" "TI")])
+
+(define_insn "*movti_mips16"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
+ (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
+ "TARGET_64BIT
+ && TARGET_MIPS16
+ && (register_operand (operands[0], TImode)
+ || register_operand (operands[1], TImode))"
+ "#"
+ [(set_attr "move_type" "move,move,move,const,constN,load,store,mfhilo")
+ (set_attr "mode" "TI")])
+
+;; 128-bit floating point moves
+
+(define_expand "movtf"
+ [(set (match_operand:TF 0)
+ (match_operand:TF 1))]
+ "TARGET_64BIT"
+{
+ if (mips_legitimize_move (TFmode, operands[0], operands[1]))
+ DONE;
+})
+
+;; This pattern handles both hard- and soft-float cases.
+(define_insn "*movtf"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
+ (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
+ "TARGET_64BIT
+ && !TARGET_MIPS16
+ && (register_operand (operands[0], TFmode)
+ || reg_or_0_operand (operands[1], TFmode))"
+ "#"
+ [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
+ (set_attr "mode" "TF")])
+
+(define_insn "*movtf_mips16"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
+ (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
+ "TARGET_64BIT
+ && TARGET_MIPS16
+ && (register_operand (operands[0], TFmode)
+ || register_operand (operands[1], TFmode))"
+ "#"
+ [(set_attr "move_type" "move,move,move,load,store")
+ (set_attr "mode" "TF")])
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand")
- (match_operand:DI 1 "move_operand"))]
+ [(set (match_operand:MOVE64 0 "nonimmediate_operand")
+ (match_operand:MOVE64 1 "move_operand"))]
"reload_completed && !TARGET_64BIT
&& mips_split_64bit_move_p (operands[0], operands[1])"
[(const_int 0)]
{
- mips_split_64bit_move (operands[0], operands[1]);
+ mips_split_doubleword_move (operands[0], operands[1]);
DONE;
})
(define_split
- [(set (match_operand:DF 0 "nonimmediate_operand")
- (match_operand:DF 1 "move_operand"))]
- "reload_completed && !TARGET_64BIT
- && mips_split_64bit_move_p (operands[0], operands[1])"
+ [(set (match_operand:MOVE128 0 "nonimmediate_operand")
+ (match_operand:MOVE128 1 "move_operand"))]
+ "TARGET_64BIT && reload_completed"
[(const_int 0)]
{
- mips_split_64bit_move (operands[0], operands[1]);
+ mips_split_doubleword_move (operands[0], operands[1]);
DONE;
})
;; When generating mips16 code, split moves of negative constants into
;; a positive "li" followed by a negation.
(define_split
- [(set (match_operand 0 "register_operand")
+ [(set (match_operand 0 "d_operand")
(match_operand 1 "const_int_operand"))]
"TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
[(set (match_dup 2)
DONE;
})
-(define_insn "movv2sf_hardfloat_64bit"
+(define_insn "*movv2sf"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
(match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
"TARGET_HARD_FLOAT
- && TARGET_64BIT
&& TARGET_PAIRED_SINGLE_FLOAT
&& (register_operand (operands[0], V2SFmode)
|| reg_or_0_operand (operands[1], V2SFmode))"
{ return mips_output_move (operands[0], operands[1]); }
- [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
- (set_attr "mode" "SF")
- (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
+ [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
+ (set_attr "mode" "DF")])
-;; The HI and LO registers are not truly independent. If we move an mthi
-;; instruction before an mflo instruction, it will make the result of the
-;; mflo unpredictable. The same goes for mtlo and mfhi.
+;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
+;; for the reason why we can't just use (reg:GPR HI_REGNUM).
;;
-;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
-;; Operand 1 is the register we want, operand 2 is the other one.
-;;
-;; When generating VR4120 or VR4130 code, we use macc{,hi} and
-;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
-;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
+;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
+;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
+;; and the errata related to -mfix-vr4130.
+(define_insn "mfhi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unspec:GPR [(match_operand:HILO 1 "register_operand" "x")]
+ UNSPEC_MFHI))]
+ ""
+ { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
+ [(set_attr "move_type" "mfhilo")
+ (set_attr "mode" "<GPR:MODE>")])
-(define_expand "mfhilo_<mode>"
- [(set (match_operand:GPR 0 "register_operand")
- (unspec:GPR [(match_operand:GPR 1 "register_operand")
- (match_operand:GPR 2 "register_operand")]
- UNSPEC_MFHILO))])
+;; Set the high part of a HI/LO value, given that the low part has
+;; already been set. See mips_hard_regno_mode_ok_p for the reason
+;; why we can't just use (reg:GPR HI_REGNUM).
+(define_insn "mthi<GPR:mode>_<HILO:mode>"
+ [(set (match_operand:HILO 0 "register_operand" "=x")
+ (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
+ (match_operand:GPR 2 "register_operand" "l")]
+ UNSPEC_MTHI))]
+ ""
+ "mthi\t%z1"
+ [(set_attr "move_type" "mthilo")
+ (set_attr "mode" "SI")])
-(define_insn "*mfhilo_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
- (match_operand:GPR 2 "register_operand" "l,h")]
- UNSPEC_MFHILO))]
- "!ISA_HAS_MACCHI"
- "mf%1\t%0"
- [(set_attr "type" "mfhilo")
- (set_attr "mode" "<MODE>")])
+;; Emit a doubleword move in which exactly one of the operands is
+;; a floating-point register. We can't just emit two normal moves
+;; because of the constraints imposed by the FPU register model;
+;; see mips_cannot_change_mode_class for details. Instead, we keep
+;; the FPR whole and use special patterns to refer to each word of
+;; the other operand.
-(define_insn "*mfhilo_<mode>_macc"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
- (match_operand:GPR 2 "register_operand" "l,h")]
- UNSPEC_MFHILO))]
- "ISA_HAS_MACCHI"
- "@
- <d>macchi\t%0,%.,%.
- <d>macc\t%0,%.,%."
- [(set_attr "type" "mfhilo")
- (set_attr "mode" "<MODE>")])
-
-;; Patterns for loading or storing part of a paired floating point
-;; register. We need them because odd-numbered floating-point registers
-;; are not fully independent: see mips_split_64bit_move.
+(define_expand "move_doubleword_fpr<mode>"
+ [(set (match_operand:SPLITF 0)
+ (match_operand:SPLITF 1))]
+ ""
+{
+ if (FP_REG_RTX_P (operands[0]))
+ {
+ rtx low = mips_subword (operands[1], 0);
+ rtx high = mips_subword (operands[1], 1);
+ emit_insn (gen_load_low<mode> (operands[0], low));
+ if (ISA_HAS_MXHC1)
+ emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
+ else
+ emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
+ }
+ else
+ {
+ rtx low = mips_subword (operands[0], 0);
+ rtx high = mips_subword (operands[0], 1);
+ emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
+ if (ISA_HAS_MXHC1)
+ emit_insn (gen_mfhc1<mode> (high, operands[1]));
+ else
+ emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
+ }
+ DONE;
+})
;; Load the low word of operand 0 with operand 1.
-(define_insn "load_df_low"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
- UNSPEC_LOAD_DF_LOW))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
+(define_insn "load_low<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
+ UNSPEC_LOAD_LOW))]
+ "TARGET_HARD_FLOAT"
{
operands[0] = mips_subword (operands[0], 0);
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "mtc,fpload")
- (set_attr "mode" "SF")])
+ [(set_attr "move_type" "mtc,fpload")
+ (set_attr "mode" "<HALFMODE>")])
;; Load the high word of operand 0 from operand 1, preserving the value
;; in the low word.
-(define_insn "load_df_high"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
- (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
- (match_operand:DF 2 "register_operand" "0,0")]
- UNSPEC_LOAD_DF_HIGH))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
+(define_insn "load_high<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
+ (match_operand:SPLITF 2 "register_operand" "0,0")]
+ UNSPEC_LOAD_HIGH))]
+ "TARGET_HARD_FLOAT"
{
operands[0] = mips_subword (operands[0], 1);
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "mtc,fpload")
- (set_attr "mode" "SF")])
-
-;; Store the high word of operand 1 in operand 0. The corresponding
-;; low-word move is done in the normal way.
-(define_insn "store_df_high"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
- (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
- UNSPEC_STORE_DF_HIGH))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
+ [(set_attr "move_type" "mtc,fpload")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
+;; high word and 0 to store the low word.
+(define_insn "store_word<mode>"
+ [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
+ (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
+ (match_operand 2 "const_int_operand")]
+ UNSPEC_STORE_WORD))]
+ "TARGET_HARD_FLOAT"
{
- operands[1] = mips_subword (operands[1], 1);
+ operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
return mips_output_move (operands[0], operands[1]);
}
- [(set_attr "type" "mfc,fpstore")
- (set_attr "mode" "SF")])
+ [(set_attr "move_type" "mfc,fpstore")
+ (set_attr "mode" "<HALFMODE>")])
;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
;; value in the low word.
-(define_insn "mthc1"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
- (match_operand:DF 2 "register_operand" "0")]
- UNSPEC_MTHC1))]
- "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+(define_insn "mthc1<mode>"
+ [(set (match_operand:SPLITF 0 "register_operand" "=f")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
+ (match_operand:SPLITF 2 "register_operand" "0")]
+ UNSPEC_MTHC1))]
+ "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
"mthc1\t%z1,%0"
- [(set_attr "type" "mtc")
- (set_attr "mode" "SF")])
-
-;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
-;; low-word move is done in the normal way.
-(define_insn "mfhc1"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
- UNSPEC_MFHC1))]
- "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
+ [(set_attr "move_type" "mtc")
+ (set_attr "mode" "<HALFMODE>")])
+
+;; Move high word of operand 1 to operand 0 using mfhc1.
+(define_insn "mfhc1<mode>"
+ [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
+ (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
+ UNSPEC_MFHC1))]
+ "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
"mfhc1\t%0,%1"
- [(set_attr "type" "mfc")
- (set_attr "mode" "SF")])
+ [(set_attr "move_type" "mfc")
+ (set_attr "mode" "<HALFMODE>")])
;; Move a constant that satisfies CONST_GP_P into operand 0.
-(define_expand "load_const_gp"
- [(set (match_operand 0 "register_operand" "=d")
- (const (unspec [(const_int 0)] UNSPEC_GP)))])
+(define_expand "load_const_gp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
;; of _gp from the start of this function. Operand 1 is the incoming
;; function address.
-(define_insn_and_split "loadgp_newabi"
- [(unspec_volatile [(match_operand 0 "" "")
- (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
+(define_insn_and_split "loadgp_newabi_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1)
+ (match_operand:P 2 "register_operand" "d")]
+ UNSPEC_LOADGP))]
"mips_current_loadgp_style () == LOADGP_NEWABI"
"#"
""
- [(set (match_dup 2) (match_dup 3))
- (set (match_dup 2) (match_dup 4))
- (set (match_dup 2) (match_dup 5))]
-{
- operands[2] = pic_offset_table_rtx;
- operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
- operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
- operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
+ [(set (match_dup 0) (match_dup 3))
+ (set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (match_dup 5))]
+{
+ operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
+ operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
+ operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
}
[(set_attr "length" "12")])
;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
-(define_insn_and_split "loadgp_absolute"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
+(define_insn_and_split "loadgp_absolute_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1)] UNSPEC_LOADGP))]
"mips_current_loadgp_style () == LOADGP_ABSOLUTE"
"#"
""
[(const_int 0)]
{
- mips_emit_move (pic_offset_table_rtx, operands[0]);
+ mips_emit_move (operands[0], operands[1]);
DONE;
}
[(set_attr "length" "8")])
-;; The use of gp is hidden when not using explicit relocations.
;; This blockage instruction prevents the gp load from being
;; scheduled after an implicit use of gp. It also prevents
;; the load from being deleted as dead.
(define_insn "loadgp_blockage"
- [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
+ [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
""
""
- [(set_attr "type" "unknown")
- (set_attr "mode" "none")
- (set_attr "length" "0")])
+ [(set_attr "type" "ghost")
+ (set_attr "mode" "none")])
;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
;; and operand 1 is the __GOTT_INDEX__ symbol.
-(define_insn "loadgp_rtp"
- [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
- (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
+(define_insn_and_split "loadgp_rtp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec_volatile:P [(match_operand:P 1 "symbol_ref_operand")
+ (match_operand:P 2 "symbol_ref_operand")]
+ UNSPEC_LOADGP))]
"mips_current_loadgp_style () == LOADGP_RTP"
"#"
- [(set_attr "length" "12")])
-
-(define_split
- [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
- (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
- "mips_current_loadgp_style () == LOADGP_RTP"
- [(set (match_dup 2) (high:P (match_dup 3)))
- (set (match_dup 2) (unspec:P [(match_dup 2)
+ ""
+ [(set (match_dup 0) (high:P (match_dup 3)))
+ (set (match_dup 0) (unspec:P [(match_dup 0)
(match_dup 3)] UNSPEC_LOAD_GOT))
- (set (match_dup 2) (unspec:P [(match_dup 2)
+ (set (match_dup 0) (unspec:P [(match_dup 0)
(match_dup 4)] UNSPEC_LOAD_GOT))]
{
- operands[2] = pic_offset_table_rtx;
- operands[3] = mips_unspec_address (operands[0], SYMBOL_ABSOLUTE);
- operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
-})
+ operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
+ operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
+}
+ [(set_attr "length" "12")])
+
+;; Initialize the global pointer for MIPS16 code. Operand 0 is the
+;; global pointer and operand 1 is the MIPS16 register that holds
+;; the required value.
+(define_insn_and_split "copygp_mips16"
+ [(set (match_operand:SI 0 "register_operand" "=y")
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
+ UNSPEC_COPYGP))]
+ "TARGET_MIPS16"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (match_dup 1))])
;; Emit a .cprestore directive, which normally expands to a single store
;; instruction. Note that we continue to use .cprestore for explicit reloc
(clobber (reg:SI 31))]
"ISA_HAS_SYNCI"
{
- return ".set\tpush\n"
- "\t.set\tnoreorder\n"
- "\t.set\tnomacro\n"
- "\tbal\t1f\n"
+ return "%(%<bal\t1f\n"
"\tnop\n"
"1:\taddiu\t$31,$31,12\n"
"\tjr.hb\t$31\n"
- "\tnop\n"
- "\t.set\tpop";
+ "\tnop%>%)";
}
[(set_attr "length" "20")])
-;; Atomic memory operations.
-
-(define_insn "memory_barrier"
- [(set (mem:BLK (scratch))
- (unspec:BLK [(const_int 0)] UNSPEC_MEMORY_BARRIER))]
- "GENERATE_SYNC"
- "%|sync%-")
-
-(define_insn "sync_compare_and_swap<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR [(match_operand:GPR 2 "register_operand" "d,d")
- (match_operand:GPR 3 "arith_operand" "I,d")]
- UNSPEC_COMPARE_AND_SWAP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_COMPARE_AND_SWAP ("<d>", "li");
- else
- return MIPS_COMPARE_AND_SWAP ("<d>", "move");
-}
- [(set_attr "length" "32")])
-
-(define_insn "sync_add<mode>"
- [(set (match_operand:GPR 0 "memory_operand" "+R,R")
- (unspec_volatile:GPR
- [(plus:GPR (match_dup 0)
- (match_operand:GPR 1 "arith_operand" "I,d"))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_OP ("<d>", "<d>addiu");
- else
- return MIPS_SYNC_OP ("<d>", "<d>addu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_sub<mode>"
- [(set (match_operand:GPR 0 "memory_operand" "+R")
- (unspec_volatile:GPR
- [(minus:GPR (match_dup 0)
- (match_operand:GPR 1 "register_operand" "d"))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- return MIPS_SYNC_OP ("<d>", "<d>subu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_old_add<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(plus:GPR (match_dup 1)
- (match_operand:GPR 2 "arith_operand" "I,d"))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_OLD_OP ("<d>", "<d>addiu");
- else
- return MIPS_SYNC_OLD_OP ("<d>", "<d>addu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_old_sub<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=&d")
- (match_operand:GPR 1 "memory_operand" "+R"))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(minus:GPR (match_dup 1)
- (match_operand:GPR 2 "register_operand" "d"))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- return MIPS_SYNC_OLD_OP ("<d>", "<d>subu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_new_add<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
- (match_operand:GPR 2 "arith_operand" "I,d")))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(plus:GPR (match_dup 1) (match_dup 2))]
- UNSPEC_SYNC_NEW_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_NEW_OP ("<d>", "<d>addiu");
- else
- return MIPS_SYNC_NEW_OP ("<d>", "<d>addu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_new_sub<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=&d")
- (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
- (match_operand:GPR 2 "register_operand" "d")))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(minus:GPR (match_dup 1) (match_dup 2))]
- UNSPEC_SYNC_NEW_OP))]
- "GENERATE_LL_SC"
-{
- return MIPS_SYNC_NEW_OP ("<d>", "<d>subu");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_<optab><mode>"
- [(set (match_operand:GPR 0 "memory_operand" "+R,R")
- (unspec_volatile:GPR
- [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
- (match_dup 0))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_OP ("<d>", "<immediate_insn>");
- else
- return MIPS_SYNC_OP ("<d>", "<insn>");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_old_<optab><mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
- (match_dup 1))]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>");
- else
- return MIPS_SYNC_OLD_OP ("<d>", "<insn>");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_new_<optab><mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR
- [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
- (match_dup 1))]
- UNSPEC_SYNC_NEW_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>");
- else
- return MIPS_SYNC_NEW_OP ("<d>", "<insn>");
-}
- [(set_attr "length" "28")])
-
-(define_insn "sync_nand<mode>"
- [(set (match_operand:GPR 0 "memory_operand" "+R,R")
- (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_NAND ("<d>", "andi");
- else
- return MIPS_SYNC_NAND ("<d>", "and");
-}
- [(set_attr "length" "32")])
-
-(define_insn "sync_old_nand<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
- UNSPEC_SYNC_OLD_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_OLD_NAND ("<d>", "andi");
- else
- return MIPS_SYNC_OLD_NAND ("<d>", "and");
-}
- [(set_attr "length" "32")])
-
-(define_insn "sync_new_nand<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
- UNSPEC_SYNC_NEW_OP))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_NEW_NAND ("<d>", "andi");
- else
- return MIPS_SYNC_NEW_NAND ("<d>", "and");
-}
- [(set_attr "length" "32")])
-
-(define_insn "sync_lock_test_and_set<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d,&d")
- (match_operand:GPR 1 "memory_operand" "+R,R"))
- (set (match_dup 1)
- (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
- UNSPEC_SYNC_EXCHANGE))]
- "GENERATE_LL_SC"
-{
- if (which_alternative == 0)
- return MIPS_SYNC_EXCHANGE ("<d>", "li");
- else
- return MIPS_SYNC_EXCHANGE ("<d>", "move");
-}
- [(set_attr "length" "24")])
\f
;; Block moves, see mips.c for more details.
;; Argument 0 is the destination
so, for a shift between 8 and 16, it is just as fast to do two
shifts of 8 or less. If there is a lot of shifting going on, we
may win in CSE. Otherwise combine will put the shifts back
- together again. This can be called by function_arg, so we must
+ together again. This can be called by mips_function_arg, so we must
be careful not to allocate a new register if we've reached the
reload pass. */
if (TARGET_MIPS16
;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
(define_split
- [(set (match_operand:GPR 0 "register_operand")
- (any_shift:GPR (match_operand:GPR 1 "register_operand")
+ [(set (match_operand:GPR 0 "d_operand")
+ (any_shift:GPR (match_operand:GPR 1 "d_operand")
(match_operand:GPR 2 "const_int_operand")))]
"TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
- && GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) > 8
&& INTVAL (operands[2]) <= 16"
[(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
}
}
[(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+ (set_attr "mode" "none")])
(define_expand "b<code>"
[(set (pc)
(pc)))]
""
{
- gen_conditional_branch (operands, <CODE>);
+ mips_expand_conditional_branch (operands, <CODE>);
DONE;
})
(if_then_else (match_operand 0)
(label_ref (match_operand 1))
(pc)))])
+
+;; Branch if bit is set/clear.
+
+(define_insn "*branch_bit<bbv><mode>"
+ [(set (pc)
+ (if_then_else
+ (equality_op (zero_extract:GPR
+ (match_operand:GPR 1 "register_operand" "d")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0))
+ (label_ref (match_operand 0 ""))
+ (pc)))]
+ "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+ return
+ mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
+ MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "branch_likely" "no")])
+
+(define_insn "*branch_bit<bbv><mode>_inverted"
+ [(set (pc)
+ (if_then_else
+ (equality_op (zero_extract:GPR
+ (match_operand:GPR 1 "register_operand" "d")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0))
+ (pc)
+ (label_ref (match_operand 0 ""))))]
+ "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+{
+ return
+ mips_output_conditional_branch (insn, operands,
+ MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
+ MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
+}
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")
+ (set_attr "branch_likely" "no")])
\f
;;
;; ....................
;;
;; ....................
+;; Destination is always set in SI mode.
+
(define_expand "seq"
[(set (match_operand:SI 0 "register_operand")
(eq:SI (match_dup 1)
(match_dup 2)))]
""
- { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; })
-(define_insn "*seq_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (eq:GPR (match_operand:GPR 1 "register_operand" "d")
- (const_int 0)))]
- "!TARGET_MIPS16"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%0,%1,1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*seq_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t")
- (eq:GPR (match_operand:GPR 1 "register_operand" "d")
- (const_int 0)))]
- "TARGET_MIPS16"
+(define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%1,1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
+
+;; Generate sltiu unless using seq results in better code.
+(define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ seq\t%0,%1,%2
+ sltiu\t%0,%1,1
+ seqi\t%0,%1,%2"
+ [(set_attr "type" "slt")
+ (set_attr "mode" "<GPR:MODE>")])
;; "sne" uses sltu instructions in which the first operand is $0.
;; This isn't possible in mips16 code.
(ne:SI (match_dup 1)
(match_dup 2)))]
"!TARGET_MIPS16"
- { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; })
-(define_insn "*sne_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (ne:GPR (match_operand:GPR 1 "register_operand" "d")
- (const_int 0)))]
- "!TARGET_MIPS16"
+(define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 0)))]
+ "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
"sltu\t%0,%.,%1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "sgt"
- [(set (match_operand:SI 0 "register_operand")
- (gt:SI (match_dup 1)
- (match_dup 2)))]
- ""
- { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
-
-(define_insn "*sgt_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (gt:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
- "!TARGET_MIPS16"
- "slt\t%0,%z2,%1"
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*sgt_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t")
- (gt:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "register_operand" "d")))]
- "TARGET_MIPS16"
- "slt\t%2,%1"
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "sge"
- [(set (match_operand:SI 0 "register_operand")
- (ge:SI (match_dup 1)
- (match_dup 2)))]
- ""
- { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
-
-(define_insn "*sge_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (ge:GPR (match_operand:GPR 1 "register_operand" "d")
- (const_int 1)))]
- "!TARGET_MIPS16"
- "slt\t%0,%.,%1"
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "slt"
- [(set (match_operand:SI 0 "register_operand")
- (lt:SI (match_dup 1)
- (match_dup 2)))]
- ""
- { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
-
-(define_insn "*slt_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (lt:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "arith_operand" "dI")))]
- "!TARGET_MIPS16"
- "slt\t%0,%1,%2"
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*slt_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t,t")
- (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
- (match_operand:GPR 2 "arith_operand" "d,I")))]
- "TARGET_MIPS16"
- "slt\t%1,%2"
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")
- (set_attr_alternative "length"
- [(const_int 4)
- (if_then_else (match_operand 2 "m16_uimm8_1")
- (const_int 4)
- (const_int 8))])])
-
-(define_expand "sle"
- [(set (match_operand:SI 0 "register_operand")
- (le:SI (match_dup 1)
- (match_dup 2)))]
- ""
- { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
-
-(define_insn "*sle_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (le:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "sle_operand" "")))]
- "!TARGET_MIPS16"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return "slt\t%0,%1,%2";
-}
- [(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*sle_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t")
- (le:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "sle_operand" "")))]
- "TARGET_MIPS16"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return "slt\t%1,%2";
-}
+;; Generate sltu unless using sne results in better code.
+(define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
+ [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
+ (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
+ (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
+ "ISA_HAS_SEQ_SNE"
+ "@
+ sne\t%0,%1,%2
+ sltu\t%0,%.,%1
+ snei\t%0,%1,%2"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")
- (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
- (const_int 4)
- (const_int 8)))])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_expand "sgtu"
+(define_expand "sgt<u>"
[(set (match_operand:SI 0 "register_operand")
- (gtu:SI (match_dup 1)
- (match_dup 2)))]
+ (any_gt:SI (match_dup 1)
+ (match_dup 2)))]
""
- { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_insn "*sgtu_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
+(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
"!TARGET_MIPS16"
- "sltu\t%0,%z2,%1"
+ "slt<u>\t%0,%z2,%1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*sgtu_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t")
- (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "register_operand" "d")))]
+(define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
- "sltu\t%2,%1"
+ "slt<u>\t%2,%1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_expand "sgeu"
+(define_expand "sge<u>"
[(set (match_operand:SI 0 "register_operand")
- (geu:SI (match_dup 1)
- (match_dup 2)))]
+ (any_ge:SI (match_dup 1)
+ (match_dup 2)))]
""
- { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_insn "*sge_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (geu:GPR (match_operand:GPR 1 "register_operand" "d")
- (const_int 1)))]
+(define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (const_int 1)))]
"!TARGET_MIPS16"
- "sltu\t%0,%.,%1"
+ "slt<u>\t%0,%.,%1"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_expand "sltu"
+(define_expand "slt<u>"
[(set (match_operand:SI 0 "register_operand")
- (ltu:SI (match_dup 1)
- (match_dup 2)))]
+ (any_lt:SI (match_dup 1)
+ (match_dup 2)))]
""
- { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_insn "*sltu_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "arith_operand" "dI")))]
+(define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "arith_operand" "dI")))]
"!TARGET_MIPS16"
- "sltu\t%0,%1,%2"
+ "slt<u>\t%0,%1,%2"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*sltu_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t,t")
- (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
- (match_operand:GPR 2 "arith_operand" "d,I")))]
+(define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t,t")
+ (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "arith_operand" "d,I")))]
"TARGET_MIPS16"
- "sltu\t%1,%2"
+ "slt<u>\t%1,%2"
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")
+ (set_attr "mode" "<GPR:MODE>")
(set_attr_alternative "length"
[(const_int 4)
(if_then_else (match_operand 2 "m16_uimm8_1")
(const_int 4)
(const_int 8))])])
-(define_expand "sleu"
+(define_expand "sle<u>"
[(set (match_operand:SI 0 "register_operand")
- (leu:SI (match_dup 1)
- (match_dup 2)))]
+ (any_le:SI (match_dup 1)
+ (match_dup 2)))]
""
- { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
+ { if (mips_expand_scc (<CODE>, operands[0])) DONE; else FAIL; })
-(define_insn "*sleu_<mode>"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (leu:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "sleu_operand" "")))]
+(define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
+ [(set (match_operand:GPR2 0 "register_operand" "=d")
+ (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "sle_operand" "")))]
"!TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return "sltu\t%0,%1,%2";
+ return "slt<u>\t%0,%1,%2";
}
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<GPR:MODE>")])
-(define_insn "*sleu_<mode>_mips16"
- [(set (match_operand:GPR 0 "register_operand" "=t")
- (leu:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:GPR 2 "sleu_operand" "")))]
+(define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
+ [(set (match_operand:GPR2 0 "register_operand" "=t")
+ (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "sle_operand" "")))]
"TARGET_MIPS16"
{
operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
- return "sltu\t%1,%2";
+ return "slt<u>\t%1,%2";
}
[(set_attr "type" "slt")
- (set_attr "mode" "<MODE>")
+ (set_attr "mode" "<GPR:MODE>")
(set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
(label_ref (match_operand 0 "" "")))]
"TARGET_MIPS16"
"b\t%l0"
- [(set_attr "type" "branch")
- (set_attr "mode" "none")
- (set_attr "length" "8")])
+ [(set_attr "type" "branch")
+ (set_attr "mode" "none")])
(define_expand "indirect_jump"
[(set (pc) (match_operand 0 "register_operand"))]
mips_emit_move (pv, lab);
emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
mips_emit_move (gp, gpv);
- emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
- emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
- emit_insn (gen_rtx_USE (VOIDmode, gp));
+ emit_use (hard_frame_pointer_rtx);
+ emit_use (stack_pointer_rtx);
+ emit_use (gp);
emit_indirect_jump (pv);
DONE;
})
[(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
""
""
- [(set_attr "type" "unknown")
- (set_attr "mode" "none")
- (set_attr "length" "0")])
+ [(set_attr "type" "ghost")
+ (set_attr "mode" "none")])
(define_expand "epilogue"
[(const_int 2)]
;; Trivial return. Make it look like a normal return insn as that
;; allows jump optimizations to work better.
-(define_insn "return"
+(define_expand "return"
+ [(return)]
+ "mips_can_use_return_insn ()"
+ { mips_expand_before_return (); })
+
+(define_insn "*return"
[(return)]
"mips_can_use_return_insn ()"
"%*j\t$31%/"
[(use (match_operand 0 "general_operand"))]
""
{
- enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
-
- if (GET_MODE (operands[0]) != gpr_mode)
- operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
+ if (GET_MODE (operands[0]) != word_mode)
+ operands[0] = convert_to_mode (word_mode, operands[0], 0);
if (TARGET_64BIT)
emit_insn (gen_eh_set_lr_di (operands[0]));
else
emit_insn (gen_eh_set_lr_si (operands[0]));
-
DONE;
})
(define_split
[(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
(clobber (match_scratch 1))]
- "reload_completed && !TARGET_DEBUG_D_MODE"
+ "reload_completed"
[(const_int 0)]
{
mips_set_return_address (operands[0], operands[1]);
DONE;
})
-(define_insn_and_split "nonlocal_goto_receiver"
+(define_expand "exception_receiver"
+ [(const_int 0)]
+ "TARGET_USE_GOT"
+{
+ /* See the comment above load_call<mode> for details. */
+ emit_insn (gen_set_got_version ());
+
+ /* If we have a call-clobbered $gp, restore it from its save slot. */
+ if (HAVE_restore_gp)
+ emit_insn (gen_restore_gp ());
+ DONE;
+})
+
+(define_expand "nonlocal_goto_receiver"
+ [(const_int 0)]
+ "TARGET_USE_GOT"
+{
+ /* See the comment above load_call<mode> for details. */
+ emit_insn (gen_set_got_version ());
+ DONE;
+})
+
+;; Restore $gp from its .cprestore stack slot. The instruction remains
+;; volatile until all uses of $28 are exposed.
+(define_insn_and_split "restore_gp"
[(set (reg:SI 28)
- (unspec_volatile:SI [(const_int 0)] UNSPEC_NONLOCAL_GOTO_RECEIVER))]
+ (unspec_volatile:SI [(const_int 0)] UNSPEC_RESTORE_GP))
+ (clobber (match_scratch:SI 0 "=&d"))]
"TARGET_CALL_CLOBBERED_GP"
"#"
"&& reload_completed"
[(const_int 0)]
{
- mips_restore_gp ();
+ mips_restore_gp (operands[0]);
DONE;
}
- [(set_attr "type" "load")
+ [(set_attr "type" "load")
(set_attr "length" "12")])
\f
;;
;; potentially modify the GOT entry. And once a stub has been called,
;; we must not call it again.
;;
-;; We represent this restriction using an imaginary fixed register that
-;; acts like a GOT version number. By making the register call-clobbered,
-;; we tell the target-independent code that the address could be changed
-;; by any call insn.
+;; We represent this restriction using an imaginary, fixed, call-saved
+;; register called GOT_VERSION_REGNUM. The idea is to make the register
+;; live throughout the function and to change its value after every
+;; potential call site. This stops any rtx value that uses the register
+;; from being computed before an earlier call. To do this, we:
+;;
+;; - Ensure that the register is live on entry to the function,
+;; so that it is never thought to be used uninitalized.
+;;
+;; - Ensure that the register is live on exit from the function,
+;; so that it is live throughout.
+;;
+;; - Make each call (lazily-bound or not) use the current value
+;; of GOT_VERSION_REGNUM, so that updates of the register are
+;; not moved across call boundaries.
+;;
+;; - Add "ghost" definitions of the register to the beginning of
+;; blocks reached by EH and ABNORMAL_CALL edges, because those
+;; edges may involve calls that normal paths don't. (E.g. the
+;; unwinding code that handles a non-call exception may change
+;; lazily-bound GOT entries.) We do this by making the
+;; exception_receiver and nonlocal_goto_receiver expanders emit
+;; a set_got_version instruction.
+;;
+;; - After each call (lazily-bound or not), use a "ghost"
+;; update_got_version instruction to change the register's value.
+;; This instruction mimics the _possible_ effect of the dynamic
+;; resolver during the call and it remains live even if the call
+;; itself becomes dead.
+;;
+;; - Leave GOT_VERSION_REGNUM out of all register classes.
+;; The register is therefore not a valid register_operand
+;; and cannot be moved to or from other registers.
+
+;; Convenience expander that generates the rhs of a load_call<mode> insn.
+(define_expand "unspec_call<mode>"
+ [(unspec:P [(match_operand:P 0)
+ (match_operand:P 1)
+ (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL)])
+
(define_insn "load_call<mode>"
[(set (match_operand:P 0 "register_operand" "=d")
- (unspec:P [(match_operand:P 1 "register_operand" "r")
+ (unspec:P [(match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "immediate_operand" "")
- (reg:P FAKE_CALL_REGNO)]
- UNSPEC_LOAD_CALL))]
+ (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
"TARGET_USE_GOT"
"<load>\t%0,%R2(%1)"
- [(set_attr "type" "load")
- (set_attr "mode" "<MODE>")
- (set_attr "length" "4")])
+ [(set_attr "got" "load")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "set_got_version"
+ [(set (reg:SI GOT_VERSION_REGNUM)
+ (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
+ "TARGET_USE_GOT"
+ ""
+ [(set_attr "type" "ghost")])
+
+(define_insn "update_got_version"
+ [(set (reg:SI GOT_VERSION_REGNUM)
+ (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
+ "TARGET_USE_GOT"
+ ""
+ [(set_attr "type" "ghost")])
;; Sibling calls. All these patterns use jump instructions.
(use (match_operand 3 ""))])] ;; struct_value_size_rtx
"TARGET_SIBCALLS"
{
- mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
+ mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
+ operands[1], operands[2], false);
DONE;
})
(use (match_operand 3 ""))])] ;; next_arg_reg
"TARGET_SIBCALLS"
{
- mips_expand_call (operands[0], XEXP (operands[1], 0),
- operands[2], operands[3], true);
+ mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
+ operands[2], operands[3], false);
DONE;
})
(use (match_operand 3 ""))])] ;; struct_value_size_rtx
""
{
- mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
+ mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
+ operands[1], operands[2], false);
DONE;
})
"reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
[(const_int 0)]
{
- emit_call_insn (gen_call_split (operands[0], operands[1]));
- if (!find_reg_note (operands[2], REG_NORETURN, 0))
- mips_restore_gp ();
+ mips_split_call (operands[2], gen_call_split (operands[0], operands[1]));
DONE;
}
- [(set_attr "jal" "indirect,direct")
- (set_attr "extended_mips16" "no,yes")])
+ [(set_attr "jal" "indirect,direct")])
+
+(define_insn "call_split"
+ [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
+ (match_operand 1 "" ""))
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 0); }
+ [(set_attr "type" "call")])
;; A pattern for calls that must be made directly. It is used for
;; MIPS16 calls that the linker may need to redirect to a hard-float
;; stub; the linker relies on the call relocation type to detect when
;; such redirection is needed.
-(define_insn "call_internal_direct"
+(define_insn_and_split "call_internal_direct"
[(call (mem:SI (match_operand 0 "const_call_insn_operand"))
(match_operand 1))
(const_int 1)
(clobber (reg:SI 31))]
""
- { return MIPS_CALL ("jal", operands, 0); })
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[2],
+ gen_call_direct_split (operands[0], operands[1]));
+ DONE;
+}
+ [(set_attr "type" "call")])
-(define_insn "call_split"
- [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
- (match_operand 1 "" ""))
+(define_insn "call_direct_split"
+ [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
+ (match_operand 1))
+ (const_int 1)
(clobber (reg:SI 31))
(clobber (reg:SI 28))]
"TARGET_SPLIT_CALLS"
(use (match_operand 3 ""))])] ;; next_arg_reg
""
{
- mips_expand_call (operands[0], XEXP (operands[1], 0),
+ mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
operands[2], operands[3], false);
DONE;
})
"reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
[(const_int 0)]
{
- emit_call_insn (gen_call_value_split (operands[0], operands[1],
- operands[2]));
- if (!find_reg_note (operands[3], REG_NORETURN, 0))
- mips_restore_gp ();
+ mips_split_call (operands[3],
+ gen_call_value_split (operands[0], operands[1],
+ operands[2]));
DONE;
}
- [(set_attr "jal" "indirect,direct")
- (set_attr "extended_mips16" "no,yes")])
+ [(set_attr "jal" "indirect,direct")])
(define_insn "call_value_split"
[(set (match_operand 0 "register_operand" "")
[(set_attr "type" "call")])
;; See call_internal_direct.
-(define_insn "call_value_internal_direct"
+(define_insn_and_split "call_value_internal_direct"
[(set (match_operand 0 "register_operand")
(call (mem:SI (match_operand 1 "const_call_insn_operand"))
(match_operand 2)))
(const_int 1)
(clobber (reg:SI 31))]
""
- { return MIPS_CALL ("jal", operands, 1); })
+ { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
+ "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
+ [(const_int 0)]
+{
+ mips_split_call (operands[3],
+ gen_call_value_direct_split (operands[0], operands[1],
+ operands[2]));
+ DONE;
+}
+ [(set_attr "type" "call")])
+
+(define_insn "call_value_direct_split"
+ [(set (match_operand 0 "register_operand")
+ (call (mem:SI (match_operand 1 "const_call_insn_operand"))
+ (match_operand 2)))
+ (const_int 1)
+ (clobber (reg:SI 31))
+ (clobber (reg:SI 28))]
+ "TARGET_SPLIT_CALLS"
+ { return MIPS_CALL ("jal", operands, 1); }
+ [(set_attr "type" "call")])
;; See comment for call_internal.
(define_insn_and_split "call_value_multiple_internal"
"reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
[(const_int 0)]
{
- emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
- operands[2], operands[3]));
- if (!find_reg_note (operands[4], REG_NORETURN, 0))
- mips_restore_gp ();
+ mips_split_call (operands[4],
+ gen_call_value_multiple_split (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
}
- [(set_attr "jal" "indirect,direct")
- (set_attr "extended_mips16" "no,yes")])
+ [(set_attr "jal" "indirect,direct")])
(define_insn "call_value_multiple_split"
[(set (match_operand 0 "register_operand" "")
(const_int 0)])
(match_operand:SCALARF 2 "register_operand" "f,0")
(match_operand:SCALARF 3 "register_operand" "0,f")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_FP_CONDMOVE"
"@
mov%T4.<fmt>\t%0,%2,%1
mov%t4.<fmt>\t%0,%3,%1"
(match_operand:GPR 3 "reg_or_0_operand")))]
"ISA_HAS_CONDMOVE"
{
- gen_conditional_move (operands);
+ mips_expand_conditional_move (operands);
DONE;
})
(if_then_else:SCALARF (match_dup 5)
(match_operand:SCALARF 2 "register_operand")
(match_operand:SCALARF 3 "register_operand")))]
- "ISA_HAS_CONDMOVE"
+ "ISA_HAS_FP_CONDMOVE"
{
- gen_conditional_move (operands);
+ mips_expand_conditional_move (operands);
DONE;
})
\f
[(set_attr "type" "arith")
(set_attr "extended_mips16" "yes")])
-; Thread-Local Storage
-
-; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
-; MIPS architecture defines this register, and no current
-; implementation provides it; instead, any OS which supports TLS is
-; expected to trap and emulate this instruction. rdhwr is part of the
-; MIPS 32r2 specification, but we use it on any architecture because
-; we expect it to be emulated. Use .set to force the assembler to
-; accept it.
-
-(define_insn "tls_get_tp_<mode>"
- [(set (match_operand:P 0 "register_operand" "=v")
- (unspec:P [(const_int 0)]
- UNSPEC_TLS_GET_TP))]
+;; Thread-Local Storage
+
+;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
+;; MIPS architecture defines this register, and no current
+;; implementation provides it; instead, any OS which supports TLS is
+;; expected to trap and emulate this instruction. rdhwr is part of the
+;; MIPS 32r2 specification, but we use it on any architecture because
+;; we expect it to be emulated. Use .set to force the assembler to
+;; accept it.
+;;
+;; We do not use a constraint to force the destination to be $3
+;; because $3 can appear explicitly as a function return value.
+;; If we leave the use of $3 implicit in the constraints until
+;; reload, we may end up making a $3 return value live across
+;; the instruction, leading to a spill failure when reloading it.
+(define_insn_and_split "tls_get_tp_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=d")
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
+ (clobber (reg:P TLS_GET_TP_REGNUM))]
"HAVE_AS_TLS && !TARGET_MIPS16"
- ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
+ "#"
+ "&& reload_completed"
+ [(set (reg:P TLS_GET_TP_REGNUM)
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
+ (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
+ ""
[(set_attr "type" "unknown")
; Since rdhwr always generates a trap for now, putting it in a delay
; slot would make the kernel's emulation of it much slower.
(set_attr "can_delay" "no")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
+
+(define_insn "*tls_get_tp_<mode>_split"
+ [(set (reg:P TLS_GET_TP_REGNUM)
+ (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
+ "HAVE_AS_TLS && !TARGET_MIPS16"
+ ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
+ [(set_attr "type" "unknown")
+ ; See tls_get_tp_<mode>
+ (set_attr "can_delay" "no")
(set_attr "mode" "<MODE>")])
\f
+;; Synchronization instructions.
+
+(include "sync.md")
+
; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
(include "mips-ps-3d.md")
; MIPS fixed-point instructions.
(include "mips-fixed.md")
+
+; ST-Microelectronics Loongson-2E/2F-specific patterns.
+(include "loongson.md")
OSDN Git Service
