/* Subroutines used for MIPS code generation.
Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
#include "target.h"
#include "target-def.h"
#include "integrate.h"
+#include "langhooks.h"
+#include "cfglayout.h"
+#include "sched-int.h"
/* Enumeration for all of the relational tests, so that we can build
arrays indexed by the test type, and not worry about the order
ITEST_MAX
};
-/* Return true if it is likely that the given mode will be accessed
- using only a single instruction. */
-#define SINGLE_WORD_MODE_P(MODE) \
- ((MODE) != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
-
-/* True if the given SYMBOL_REF is for an internally-generated symbol. */
-#define INTERNAL_SYMBOL_P(SYM) \
- (XSTR (SYM, 0)[0] == '*' && XSTR (SYM, 0)[1] == LOCAL_LABEL_PREFIX[0])
-
/* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
#define UNSPEC_ADDRESS_P(X) \
(GET_CODE (X) == UNSPEC \
#define UNSPEC_ADDRESS_TYPE(X) \
((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
-/* True if X is (const $gp). This is used to initialize the mips16
- gp pseudo register. */
+/* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
+ to initialize the mips16 gp pseudo register. */
#define CONST_GP_P(X) \
- (GET_CODE (X) == CONST && XEXP (X, 0) == pic_offset_table_rtx)
+ (GET_CODE (X) == CONST \
+ && GET_CODE (XEXP (X, 0)) == UNSPEC \
+ && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
/* The maximum distance between the top of the stack frame and the
value $sp has when we save & restore registers.
multi-instruction addu sequence. Use 0x7fe0 to work around this. */
#define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
-/* Classifies a SYMBOL_REF, LABEL_REF or UNSPEC address.
-
- SYMBOL_GENERAL
- Used when none of the below apply.
-
- SYMBOL_SMALL_DATA
- The symbol refers to something in a small data section.
-
- SYMBOL_CONSTANT_POOL
- The symbol refers to something in the mips16 constant pool.
-
- SYMBOL_GOT_LOCAL
- The symbol refers to local data that will be found using
- the global offset table.
-
- SYMBOL_GOT_GLOBAL
- Likewise non-local data.
-
- SYMBOL_GOTOFF_PAGE
- An UNSPEC wrapper around a SYMBOL_GOT_LOCAL. It represents the
- offset from _gp of a GOT page entry.
-
- SYMBOL_GOTOFF_GLOBAL
- An UNSPEC wrapper around a SYMBOL_GOT_GLOBAL. It represents the
- the offset from _gp of the symbol's GOT entry.
-
- SYMBOL_GOTOFF_CALL
- Like SYMBOL_GOTOFF_GLOBAL, but used when calling a global function.
- The GOT entry is allowed to point to a stub rather than to the
- function itself.
-
- SYMBOL_GOTOFF_LOADGP
- An UNSPEC wrapper around a function's address. It represents the
- offset of _gp from the start of the function. */
-enum mips_symbol_type {
- SYMBOL_GENERAL,
- SYMBOL_SMALL_DATA,
- SYMBOL_CONSTANT_POOL,
- SYMBOL_GOT_LOCAL,
- SYMBOL_GOT_GLOBAL,
- SYMBOL_GOTOFF_PAGE,
- SYMBOL_GOTOFF_GLOBAL,
- SYMBOL_GOTOFF_CALL,
- SYMBOL_GOTOFF_LOADGP
-};
-#define NUM_SYMBOL_TYPES (SYMBOL_GOTOFF_LOADGP + 1)
-
+/* True if INSN is a mips.md pattern or asm statement. */
+#define USEFUL_INSN_P(INSN) \
+ (INSN_P (INSN) \
+ && GET_CODE (PATTERN (INSN)) != USE \
+ && GET_CODE (PATTERN (INSN)) != CLOBBER \
+ && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
+ && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
+
+/* If INSN is a delayed branch sequence, return the first instruction
+ in the sequence, otherwise return INSN itself. */
+#define SEQ_BEGIN(INSN) \
+ (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
+ ? XVECEXP (PATTERN (INSN), 0, 0) \
+ : (INSN))
+
+/* Likewise for the last instruction in a delayed branch sequence. */
+#define SEQ_END(INSN) \
+ (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
+ ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
+ : (INSN))
+
+/* Execute the following loop body with SUBINSN set to each instruction
+ between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
+#define FOR_EACH_SUBINSN(SUBINSN, INSN) \
+ for ((SUBINSN) = SEQ_BEGIN (INSN); \
+ (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
+ (SUBINSN) = NEXT_INSN (SUBINSN))
/* Classifies an address.
register and the second is the stack slot. */
typedef void (*mips_save_restore_fn) (rtx, rtx);
-struct constant;
+struct mips16_constant;
struct mips_arg_info;
struct mips_address_info;
struct mips_integer_op;
+struct mips_sim;
static enum mips_symbol_type mips_classify_symbol (rtx);
static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
+static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
static rtx mips_force_temporary (rtx, rtx);
static rtx mips_split_symbol (rtx, rtx);
-static rtx mips_unspec_address (rtx, enum mips_symbol_type);
-static rtx mips_unspec_offset_high (rtx, rtx, enum mips_symbol_type);
-static rtx mips_load_got (rtx, rtx, enum mips_symbol_type);
+static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
static rtx mips_add_offset (rtx, HOST_WIDE_INT);
static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
static unsigned int mips_build_lower (struct mips_integer_op *,
static enum internal_test map_test_to_internal_test (enum rtx_code);
static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
enum rtx_code *);
+static void mips_load_call_address (rtx, rtx, int);
static bool mips_function_ok_for_sibcall (tree, tree);
static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
mips_save_restore_fn);
static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
+static void mips_output_cplocal (void);
+static void mips_emit_loadgp (void);
static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
static void mips_set_frame_expr (rtx);
static rtx mips_frame_set (rtx, rtx);
static void mips_save_reg (rtx, rtx);
static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
static void mips_restore_reg (rtx, rtx);
+static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+ HOST_WIDE_INT, tree);
static int symbolic_expression_p (rtx);
static void mips_select_rtx_section (enum machine_mode, rtx,
unsigned HOST_WIDE_INT);
static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
ATTRIBUTE_UNUSED;
static bool mips_in_small_data_p (tree);
-static void mips_encode_section_info (tree, rtx, int);
static int mips_fpr_return_fields (tree, tree *);
static bool mips_return_in_msb (tree);
static rtx mips_return_fpr_pair (enum machine_mode mode,
static rtx mips16_gp_pseudo_reg (void);
static void mips16_fp_args (FILE *, int, int);
static void build_mips16_function_stub (FILE *);
-static void mips16_optimize_gp (void);
-static rtx add_constant (struct constant **, rtx, enum machine_mode);
-static void dump_constants (struct constant *, rtx);
-static rtx mips_find_symbol (rtx);
+static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
+static void dump_constants (struct mips16_constant *, rtx);
+static int mips16_insn_length (rtx);
+static int mips16_rewrite_pool_refs (rtx *, void *);
static void mips16_lay_out_constants (void);
+static void mips_sim_reset (struct mips_sim *);
+static void mips_sim_init (struct mips_sim *, state_t);
+static void mips_sim_next_cycle (struct mips_sim *);
+static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
+static int mips_sim_wait_regs_2 (rtx *, void *);
+static void mips_sim_wait_regs_1 (rtx *, void *);
+static void mips_sim_wait_regs (struct mips_sim *, rtx);
+static void mips_sim_wait_units (struct mips_sim *, rtx);
+static void mips_sim_wait_insn (struct mips_sim *, rtx);
+static void mips_sim_record_set (rtx, rtx, void *);
+static void mips_sim_issue_insn (struct mips_sim *, rtx);
+static void mips_sim_issue_nop (struct mips_sim *);
+static void mips_sim_finish_insn (struct mips_sim *, rtx);
+static void vr4130_avoid_branch_rt_conflict (rtx);
+static void vr4130_align_insns (void);
static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
static void mips_avoid_hazards (void);
static void mips_reorg (void);
static bool mips_matching_cpu_name_p (const char *, const char *);
static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
+static bool mips_return_in_memory (tree, tree);
+static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
+static void mips_macc_chains_record (rtx);
+static void mips_macc_chains_reorder (rtx *, int);
+static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
+static bool vr4130_true_reg_dependence_p (rtx);
+static bool vr4130_swap_insns_p (rtx, rtx);
+static void vr4130_reorder (rtx *, int);
+static void mips_promote_ready (rtx *, int, int);
+static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
+static int mips_variable_issue (FILE *, int, rtx, int);
static int mips_adjust_cost (rtx, rtx, rtx, int);
static int mips_issue_rate (void);
static int mips_use_dfa_pipeline_interface (void);
+static int mips_multipass_dfa_lookahead (void);
static void mips_init_libfuncs (void);
+static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
+ tree, int *, int);
static tree mips_build_builtin_va_list (void);
#if TARGET_IRIX
};
struct machine_function GTY(()) {
- /* Pseudo-reg holding the address of the current function when
- generating embedded PIC code. */
- rtx embedded_pic_fnaddr_rtx;
-
/* Pseudo-reg holding the value of $28 in a mips16 function which
refers to GP relative global variables. */
rtx mips16_gp_pseudo_rtx;
/* Current frame information, calculated by compute_frame_size. */
struct mips_frame_info frame;
- /* Length of instructions in function; mips16 only. */
- long insns_len;
-
/* The register to use as the global pointer within this function. */
unsigned int global_pointer;
can support a given mode. */
char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
-/* The length of all strings seen when compiling for the mips16. This
- is used to tell how many strings are in the constant pool, so that
- we can see if we may have an overflow. This is reset each time the
- constant pool is output. */
-int mips_string_length;
-
-/* When generating mips16 code, a list of all strings that are to be
- output after the current function. */
-
-static GTY(()) rtx mips16_strings;
-
-/* In mips16 mode, we build a list of all the string constants we see
- in a particular function. */
-
-struct string_constant
-{
- struct string_constant *next;
- const char *label;
-};
-
-static struct string_constant *string_constants;
-
/* List of all MIPS punctuation characters used by print_operand. */
char mips_print_operand_punct[256];
/* Map GCC register number to debugger register number. */
int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
-/* An alias set for the GOT. */
-static int mips_got_alias_set;
-
/* A copy of the original flag_delayed_branch: see override_options. */
static int mips_flag_delayed_branch;
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
- "$fcc5","$fcc6","$fcc7","", "", "", "", "",
+ "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec",
"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
- "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
+ "$fcc5","$fcc6","$fcc7","$rap", "", "$arg", "$frame", "$fakec",
"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
"$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
HI_REG, LO_REG, NO_REGS, ST_REGS,
ST_REGS, ST_REGS, ST_REGS, ST_REGS,
ST_REGS, ST_REGS, ST_REGS, NO_REGS,
- NO_REGS, NO_REGS, NO_REGS, NO_REGS,
+ NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
{ "vr4100", PROCESSOR_R4100, 3 },
{ "vr4111", PROCESSOR_R4111, 3 },
{ "vr4120", PROCESSOR_R4120, 3 },
+ { "vr4130", PROCESSOR_R4130, 3 },
{ "vr4300", PROCESSOR_R4300, 3 },
{ "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
{ "r4600", PROCESSOR_R4600, 3 },
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
+#undef TARGET_SCHED_REORDER
+#define TARGET_SCHED_REORDER mips_sched_reorder
+#undef TARGET_SCHED_VARIABLE_ISSUE
+#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST mips_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
+ mips_multipass_dfa_lookahead
#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST mips_address_cost
-#undef TARGET_ENCODE_SECTION_INFO
-#define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
#undef TARGET_IN_SMALL_DATA_P
#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
+
+#undef TARGET_PROMOTE_FUNCTION_ARGS
+#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
+#undef TARGET_PROMOTE_FUNCTION_RETURN
+#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
+
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY mips_return_in_memory
#undef TARGET_RETURN_IN_MSB
#define TARGET_RETURN_IN_MSB mips_return_in_msb
+#undef TARGET_ASM_OUTPUT_MI_THUNK
+#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
+#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
+#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
+
+#undef TARGET_SETUP_INCOMING_VARARGS
+#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
mips_classify_symbol (rtx x)
{
if (GET_CODE (x) == LABEL_REF)
- return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
+ {
+ if (TARGET_MIPS16)
+ return SYMBOL_CONSTANT_POOL;
+ if (TARGET_ABICALLS)
+ return SYMBOL_GOT_LOCAL;
+ return SYMBOL_GENERAL;
+ }
if (GET_CODE (x) != SYMBOL_REF)
abort ();
return SYMBOL_GENERAL;
}
- if (INTERNAL_SYMBOL_P (x))
- {
- /* The symbol is a local label. For TARGET_MIPS16, SYMBOL_REF_FLAG
- will be set if the symbol refers to a string in the current
- function's constant pool. */
- if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
- return SYMBOL_CONSTANT_POOL;
-
- if (TARGET_ABICALLS)
- return SYMBOL_GOT_LOCAL;
- }
-
if (SYMBOL_REF_SMALL_P (x))
return SYMBOL_SMALL_DATA;
if (TARGET_ABICALLS)
- return (SYMBOL_REF_FLAG (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL);
+ {
+ if (SYMBOL_REF_DECL (x) == 0)
+ return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
+
+ /* There are three cases to consider:
+
+ - o32 PIC (either with or without explicit relocs)
+ - n32/n64 PIC without explicit relocs
+ - n32/n64 PIC with explicit relocs
+
+ In the first case, both local and global accesses will use an
+ R_MIPS_GOT16 relocation. We must correctly predict which of
+ the two semantics (local or global) the assembler and linker
+ will apply. The choice doesn't depend on the symbol's
+ visibility, so we deliberately ignore decl_visibility and
+ binds_local_p here.
+
+ In the second case, the assembler will not use R_MIPS_GOT16
+ relocations, but it chooses between local and global accesses
+ in the same way as for o32 PIC.
+
+ In the third case we have more freedom since both forms of
+ access will work for any kind of symbol. However, there seems
+ little point in doing things differently. */
+ if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
+ return SYMBOL_GOT_GLOBAL;
+
+ return SYMBOL_GOT_LOCAL;
+ }
return SYMBOL_GENERAL;
}
}
+/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
+ to the same object as SYMBOL. */
+
+static bool
+mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
+{
+ if (GET_CODE (symbol) != SYMBOL_REF)
+ return false;
+
+ if (CONSTANT_POOL_ADDRESS_P (symbol)
+ && offset >= 0
+ && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
+ return true;
+
+ if (SYMBOL_REF_DECL (symbol) != 0
+ && offset >= 0
+ && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
+ return true;
+
+ return false;
+}
+
+
/* Return true if X is a symbolic constant that can be calculated in
the same way as a bare symbol. If it is, store the type of the
symbol in *SYMBOL_TYPE. */
switch (*symbol_type)
{
case SYMBOL_GENERAL:
- /* %hi() and %lo() can handle anything. */
+ case SYMBOL_64_HIGH:
+ case SYMBOL_64_MID:
+ case SYMBOL_64_LOW:
+ /* If the target has 64-bit pointers and the object file only
+ supports 32-bit symbols, the values of those symbols will be
+ sign-extended. In this case we can't allow an arbitrary offset
+ in case the 32-bit value X + OFFSET has a different sign from X. */
+ if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
+ return mips_offset_within_object_p (x, offset);
+
+ /* In other cases the relocations can handle any offset. */
return true;
+ case SYMBOL_CONSTANT_POOL:
+ /* Allow constant pool references to be converted to LABEL+CONSTANT.
+ In this case, we no longer have access to the underlying constant,
+ but the original symbol-based access was known to be valid. */
+ if (GET_CODE (x) == LABEL_REF)
+ return true;
+
+ /* Fall through. */
+
case SYMBOL_SMALL_DATA:
/* Make sure that the offset refers to something within the
- -G limit. If the offset is allowed to grow too much,
- it could overflow the range of %gp_rel(). */
- return (offset > 0 && offset < mips_section_threshold);
-
- case SYMBOL_CONSTANT_POOL:
- /* Similarly check the range of offsets for mips16 constant
- pool entries. */
- return (CONSTANT_POOL_ADDRESS_P (x)
- && offset > 0
- && offset < (int) GET_MODE_SIZE (get_pool_mode (x)));
+ underlying object. This should guarantee that the final
+ PC- or GP-relative offset is within the 16-bit limit. */
+ return mips_offset_within_object_p (x, offset);
case SYMBOL_GOT_LOCAL:
case SYMBOL_GOTOFF_PAGE:
/* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
int
-mips_reg_mode_ok_for_base_p (rtx reg, enum machine_mode mode, int strict)
+mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
{
- return (strict
- ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
- : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
+ if (regno >= FIRST_PSEUDO_REGISTER)
+ {
+ if (!strict)
+ return true;
+ regno = reg_renumber[regno];
+ }
+
+ /* These fake registers will be eliminated to either the stack or
+ hard frame pointer, both of which are usually valid base registers.
+ Reload deals with the cases where the eliminated form isn't valid. */
+ if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
+ return true;
+
+ /* In mips16 mode, the stack pointer can only address word and doubleword
+ values, nothing smaller. There are two problems here:
+
+ (a) Instantiating virtual registers can introduce new uses of the
+ stack pointer. If these virtual registers are valid addresses,
+ the stack pointer should be too.
+
+ (b) Most uses of the stack pointer are not made explicit until
+ FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
+ We don't know until that stage whether we'll be eliminating to the
+ stack pointer (which needs the restriction) or the hard frame
+ pointer (which doesn't).
+
+ All in all, it seems more consistent to only enforce this restriction
+ during and after reload. */
+ if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
+ return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
+
+ return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
}
x = SUBREG_REG (x);
return (GET_CODE (x) == REG
- && mips_reg_mode_ok_for_base_p (x, mode, strict));
+ && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
}
return true;
case SYMBOL_CONSTANT_POOL:
- /* PC-relative addressing is only available for lw, sw, ld and sd. */
+ /* PC-relative addressing is only available for lw and ld. */
return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
case SYMBOL_GOT_LOCAL:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
+ case SYMBOL_64_HIGH:
+ case SYMBOL_64_MID:
+ case SYMBOL_64_LOW:
return true;
}
abort ();
return 2;
case SYMBOL_GOT_LOCAL:
- /* For o32 and o64, the sequence is:
+ case SYMBOL_GOT_GLOBAL:
+ /* Unless -funit-at-a-time is in effect, we can't be sure whether
+ the local/global classification is accurate. See override_options
+ for details.
- lw $at,%got(symbol)
- nop
+ The worst cases are:
- and the final address is $at + %lo(symbol). A load/add
- sequence is also needed for n32 and n64. Some versions
- of GAS insert a nop in the n32/n64 sequences too so, for
- simplicity, use the worst case of 3 instructions. */
- return 3;
+ (1) For local symbols when generating o32 or o64 code. The assembler
+ will use:
- case SYMBOL_GOT_GLOBAL:
- /* When using a small GOT, we just fetch the address using
- a gp-relative load. For a big GOT, we need a sequence
- such as:
+ lw $at,%got(symbol)
+ nop
+
+ ...and the final address will be $at + %lo(symbol).
+
+ (2) For global symbols when -mxgot. The assembler will use:
- lui $at,%got_hi(symbol)
- daddu $at,$at,$gp
+ lui $at,%got_hi(symbol)
+ (d)addu $at,$at,$gp
- and the final address is $at + %got_lo(symbol). */
- return (TARGET_XGOT ? 3 : 1);
+ ...and the final address will be $at + %got_lo(symbol). */
+ return 3;
case SYMBOL_GOTOFF_PAGE:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
+ case SYMBOL_64_HIGH:
+ case SYMBOL_64_MID:
+ case SYMBOL_64_LOW:
/* Check whether the offset is a 16- or 32-bit value. */
return mips_split_p[type] ? 2 : 1;
}
struct mips_address_info addr;
int factor;
- /* Each word of a multi-word value will be accessed individually. */
- factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+ if (mode == BLKmode)
+ /* BLKmode is used for single unaligned loads and stores. */
+ factor = 1;
+ else
+ /* Each word of a multi-word value will be accessed individually. */
+ factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+
if (mips_classify_address (&addr, x, mode, false))
switch (addr.type)
{
switch (GET_CODE (x))
{
- case CONSTANT_P_RTX:
- return 1;
-
case HIGH:
if (TARGET_MIPS16
|| !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
}
+/* Return the number of instructions needed for an integer division. */
+
+int
+mips_idiv_insns (void)
+{
+ int count;
+
+ count = 1;
+ if (TARGET_CHECK_ZERO_DIV)
+ count += 2;
+ if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
+ count++;
+ return count;
+}
+
+
/* Return truth value of whether OP can be used as an operands
where a register or 16 bit unsigned integer is needed. */
}
}
-/* Accept a register or the floating point constant 1 in the appropriate mode. */
+/* Accept a register or the floating point constant 1 in the
+ appropriate mode. */
int
reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
{
- REAL_VALUE_TYPE d;
-
- switch (GET_CODE (op))
- {
- case CONST_DOUBLE:
- if (mode != GET_MODE (op)
- || (mode != DFmode && mode != SFmode))
- return 0;
-
- REAL_VALUE_FROM_CONST_DOUBLE (d, op);
- return REAL_VALUES_EQUAL (d, dconst1);
-
- default:
- return register_operand (op, mode);
- }
+ return const_float_1_operand (op, mode) || register_operand (op, mode);
}
/* Accept the floating point constant 1 in the appropriate mode. */
&& (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
}
+/* Return true if X is the right hand side of a "macc" or "msac" instruction.
+ This predicate is intended for use in peephole optimizations. */
+
+int
+macc_msac_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ if (ISA_HAS_MACC && GET_CODE (x) == PLUS && REG_P (XEXP (x, 1)))
+ x = XEXP (x, 0);
+ else if (ISA_HAS_MSAC && GET_CODE (x) == MINUS && REG_P (XEXP (x, 0)))
+ x = XEXP (x, 1);
+ else
+ return false;
+
+ return GET_CODE (x) == MULT && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1));
+}
+
/* Return nonzero if the code of this rtx pattern is EQ or NE. */
int
if (mode != GET_MODE (op))
return 0;
- return GET_RTX_CLASS (GET_CODE (op)) == '<';
+ return COMPARISON_P (op);
}
/* Return nonzero if the code is a relational operation suitable for a
if (TARGET_MIPS16)
return true;
+ /* When generating 32-bit code, allow DImode move_operands to
+ match arbitrary constants. We split them after reload. */
+ if (!TARGET_64BIT && mode == DImode)
+ return true;
+
/* Otherwise check whether the constant can be loaded in a single
instruction. */
return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
}
+/* Return true if OP is a symbolic constant of type SYMBOL_GENERAL. */
+
+int
+general_symbolic_operand (rtx op, enum machine_mode mode)
+{
+ enum mips_symbol_type symbol_type;
+
+ return ((mode == VOIDmode || mode == GET_MODE (op))
+ && mips_symbolic_constant_p (op, &symbol_type)
+ && symbol_type == SYMBOL_GENERAL);
+}
+
+
/* Return true if we're generating PIC and OP is a global symbol. */
int
&& addr.reg == stack_pointer_rtx);
}
+/* Helper function for DFA schedulers. Return true if OP is a floating
+ point register. */
+
+int
+fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return REG_P (op) && FP_REG_P (REGNO (op));
+}
+
+/* Helper function for DFA schedulers. Return true if OP is a LO reg. */
+
+int
+lo_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+ return REG_P (op) && REGNO (op) == LO_REGNUM;
+}
+\f
/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
returns a nonzero value if X is a legitimate address for a memory
/* Return an UNSPEC address with underlying address ADDRESS and symbol
type SYMBOL_TYPE. */
-static rtx
+rtx
mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
{
rtx base;
/* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
high part to BASE and return the result. Just return BASE otherwise.
+ TEMP is available as a temporary register if needed.
The returned expression can be used as the first operand to a LO_SUM. */
static rtx
-mips_unspec_offset_high (rtx base, rtx addr, enum mips_symbol_type symbol_type)
+mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
+ enum mips_symbol_type symbol_type)
{
if (mips_split_p[symbol_type])
{
addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
- base = force_reg (Pmode, expand_simple_binop (Pmode, PLUS, base, addr,
- NULL, 0, OPTAB_WIDEN));
+ addr = mips_force_temporary (temp, addr);
+ return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
}
return base;
}
-/* Return a memory reference for the GOT slot whose offset is given by
- mips_unspec_address (ADDR, SYMBOL_TYPE). Register BASE contains the
- high part of the offset plus $gp. */
-
-static rtx
-mips_load_got (rtx base, rtx addr, enum mips_symbol_type symbol_type)
-{
- rtx mem, offset;
-
- offset = mips_unspec_address (addr, symbol_type);
- mem = gen_rtx_MEM (ptr_mode, gen_rtx_LO_SUM (Pmode, base, offset));
- set_mem_alias_set (mem, mips_got_alias_set);
-
- /* GOT references can't trap. */
- MEM_NOTRAP_P (mem) = 1;
-
- /* If we allow a function's address to be lazily bound, its entry
- may change after the first call. Other entries are constant. */
- if (symbol_type != SYMBOL_GOTOFF_CALL)
- RTX_UNCHANGING_P (mem) = 1;
-
- return mem;
-}
-
-
-/* Return the offset of ADDR's GOT entry from _gp. ADDR is a
- global_got_operand. */
-
-rtx
-mips_gotoff_global (rtx addr)
-{
- return mips_unspec_address (addr, SYMBOL_GOTOFF_GLOBAL);
-}
-
-
-/* Fetch the high part of local_got_operand ADDR from the GOT. */
-
-rtx
-mips_load_got_page (rtx addr)
-{
- return mips_load_got (pic_offset_table_rtx, addr, SYMBOL_GOTOFF_PAGE);
-}
-
-
-/* Fetch the address of global_got_operand ADDR from the GOT. BASE is a
- register that holds the address _gp + %got_hi(ADDR). */
-
-rtx
-mips_load_got_global (rtx base, rtx addr)
-{
- return mips_load_got (base, addr, SYMBOL_GOTOFF_GLOBAL);
-}
-
-
/* Return a legitimate address for REG + OFFSET. This function will
create a temporary register if OFFSET is not a SMALL_OPERAND. */
return true;
}
- /* The source of an SImode move must be a move_operand. Likewise
- DImode moves on 64-bit targets. We need to deal with constants
- that would be legitimate immediate_operands but not legitimate
- move_operands. */
+ /* Check for individual, fully-reloaded mflo and mfhi instructions. */
if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
- && CONSTANT_P (src)
- && !move_operand (src, mode))
+ && REG_P (src) && MD_REG_P (REGNO (src))
+ && REG_P (dest) && GP_REG_P (REGNO (dest)))
+ {
+ int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
+ if (GET_MODE_SIZE (mode) <= 4)
+ emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
+ gen_rtx_REG (SImode, REGNO (src)),
+ gen_rtx_REG (SImode, other_regno)));
+ else
+ emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
+ gen_rtx_REG (DImode, REGNO (src)),
+ gen_rtx_REG (DImode, other_regno)));
+ return true;
+ }
+
+ /* We need to deal with constants that would be legitimate
+ immediate_operands but not legitimate move_operands. */
+ if (CONSTANT_P (src) && !move_operand (src, mode))
{
mips_legitimize_const_move (mode, dest, src);
set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
{
return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
}
-
-/* References to the string table on the mips16 only use a small
- offset if the function is small. We can't check for LABEL_REF here,
- because the offset is always large if the label is before the
- referencing instruction. */
-
-int
-m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) == SYMBOL_REF
- && SYMBOL_REF_FLAG (op)
- && cfun->machine->insns_len > 0
- && INTERNAL_SYMBOL_P (op)
- && (cfun->machine->insns_len + get_pool_size () + mips_string_length
- < 4 * 0x100))
- {
- struct string_constant *l;
-
- /* Make sure this symbol is on thelist of string constants to be
- output for this function. It is possible that it has already
- been output, in which case this requires a large offset. */
- for (l = string_constants; l != NULL; l = l->next)
- if (strcmp (l->label, XSTR (op, 0)) == 0)
- return 1;
- }
-
- return 0;
-}
-
-int
-m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- if (GET_CODE (op) == SYMBOL_REF
- && SYMBOL_REF_FLAG (op)
- && cfun->machine->insns_len > 0
- && INTERNAL_SYMBOL_P (op)
- && (cfun->machine->insns_len + get_pool_size () + mips_string_length
- < 4 * 0x20))
- {
- struct string_constant *l;
-
- /* Make sure this symbol is on thelist of string constants to be
- output for this function. It is possible that it has already
- been output, in which case this requires a large offset. */
- for (l = string_constants; l != NULL; l = l->next)
- if (strcmp (l->label, XSTR (op, 0)) == 0)
- return 1;
- }
-
- return 0;
-}
\f
static bool
mips_rtx_costs (rtx x, int code, int outer_code, int *total)
*total = COSTS_N_INSNS (2);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (3);
+ else if (TUNE_SB1)
+ *total = COSTS_N_INSNS (4);
else
*total = COSTS_N_INSNS (6);
return true;
{
if (TUNE_MIPS3000
|| TUNE_MIPS3900
- || TUNE_MIPS5000)
+ || TUNE_MIPS5000
+ || TUNE_SB1)
*total = COSTS_N_INSNS (4);
else if (TUNE_MIPS6000
|| TUNE_MIPS5400
if (mode == DFmode)
{
- if (TUNE_MIPS3000
+ if (TUNE_SB1)
+ *total = COSTS_N_INSNS (4);
+ else if (TUNE_MIPS3000
|| TUNE_MIPS3900
|| TUNE_MIPS5000)
*total = COSTS_N_INSNS (5);
*total = COSTS_N_INSNS (12);
else if (TUNE_MIPS3900)
*total = COSTS_N_INSNS (2);
- else if (TUNE_MIPS5400 || TUNE_MIPS5500)
- *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
- else if (TUNE_MIPS7000)
+ else if (TUNE_MIPS4130)
+ *total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
+ else if (TUNE_MIPS5400 || TUNE_SB1)
+ *total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
+ else if (TUNE_MIPS5500 || TUNE_MIPS7000)
*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
else if (TUNE_MIPS9000)
*total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
*total = COSTS_N_INSNS (12);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (15);
+ else if (TUNE_SB1)
+ *total = COSTS_N_INSNS (24);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS (30);
else
*total = COSTS_N_INSNS (59);
else if (TUNE_MIPS6000)
*total = COSTS_N_INSNS (16);
+ else if (TUNE_SB1)
+ *total = COSTS_N_INSNS (32);
else
*total = COSTS_N_INSNS (36);
return true;
}
- /* FALLTHRU */
+ /* Fall through. */
case UDIV:
case UMOD:
*total = COSTS_N_INSNS (38);
else if (TUNE_MIPS5000)
*total = COSTS_N_INSNS (36);
+ else if (TUNE_SB1)
+ *total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
else if (TUNE_MIPS5400 || TUNE_MIPS5500)
*total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
else
return mips_address_insns (addr, SImode);
}
\f
-/* Return a pseudo that points to the address of the current function.
- The first time it is called for a function, an initializer for the
- pseudo is emitted in the beginning of the function. */
-
-rtx
-embedded_pic_fnaddr_reg (void)
-{
- if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
- {
- rtx seq;
-
- cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
-
- /* Output code at function start to initialize the pseudo-reg. */
- /* ??? We used to do this in FINALIZE_PIC, but that does not work for
- inline functions, because it is called after RTL for the function
- has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
- does not get copied, and ends up not matching the rest of the RTL.
- This solution works, but means that we get unnecessary code to
- initialize this value every time a function is inlined into another
- function. */
- start_sequence ();
- emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
- XEXP (DECL_RTL (current_function_decl), 0)));
- seq = get_insns ();
- end_sequence ();
- push_topmost_sequence ();
- emit_insn_after (seq, get_insns ());
- pop_topmost_sequence ();
- }
-
- return cfun->machine->embedded_pic_fnaddr_rtx;
-}
-
-/* Return RTL for the offset from the current function to the argument.
- X is the symbol whose offset from the current function we want. */
-
-rtx
-embedded_pic_offset (rtx x)
-{
- /* Make sure it is emitted. */
- embedded_pic_fnaddr_reg ();
-
- return
- gen_rtx_CONST (Pmode,
- gen_rtx_MINUS (Pmode, x,
- XEXP (DECL_RTL (current_function_decl), 0)));
-}
-\f
/* Return one word of double-word value OP, taking into account the fixed
endianness of certain registers. HIGH_P is true to select the high part,
false to select the low part. */
{
if (src_code == REG)
{
- if (MD_REG_P (REGNO (src)))
- return "mf%1\t%0";
-
if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
if (mode == VOIDmode)
mode = GET_MODE (cmp1);
- /* Eliminate simple branches */
+ /* Eliminate simple branches. */
branch_p = (result == 0);
if (branch_p)
{
if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
{
- /* Comparisons against zero are simple branches */
+ /* Comparisons against zero are simple branches. */
if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
&& (! TARGET_MIPS16 || eqne_p))
return 0;
return 0;
}
- /* allocate a pseudo to calculate the value in. */
+ /* Allocate a pseudo to calculate the value in. */
result = gen_reg_rtx (mode);
}
else
{
reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
- convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
+ convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
+ mode, cmp0, cmp1), 0);
}
if (test == ITEST_NE)
{
if (! TARGET_MIPS16)
{
- convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
+ convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
if (p_invert != NULL)
*p_invert = 0;
invert = 0;
else
{
reg2 = invert ? gen_reg_rtx (mode) : result;
- convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
+ convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
reg = reg2;
}
}
reg = reg2;
one = force_reg (mode, const1_rtx);
}
- convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
+ convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
}
return result;
get_float_compare_codes (test_code, &cmp_code, &test_code);
emit_insn (gen_rtx_SET (VOIDmode, reg,
- gen_rtx (cmp_code, CCmode, cmp0, cmp1)));
+ gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
mode = CCmode;
cmp0 = reg;
break;
default:
- fatal_insn ("bad test", gen_rtx (test_code, VOIDmode, cmp0, cmp1));
+ fatal_insn ("bad test",
+ gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
}
/* Generate the branch. */
label1 = pc_rtx;
}
- emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
- gen_rtx_IF_THEN_ELSE (VOIDmode,
- gen_rtx (test_code, mode,
- cmp0, cmp1),
- label1, label2)));
+ emit_jump_insn
+ (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_IF_THEN_ELSE (VOIDmode,
+ gen_rtx_fmt_ee (test_code, mode,
+ cmp0, cmp1),
+ label1, label2)));
}
/* Emit the common code for conditional moves. OPERANDS is the array
cmp_reg = gen_reg_rtx (cmp_mode);
emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
- gen_rtx (cmp_code, cmp_mode, op0, op1)));
+ gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
emit_insn (gen_rtx_SET (op_mode, operands[0],
gen_rtx_IF_THEN_ELSE (op_mode,
- gen_rtx (move_code, VOIDmode,
- cmp_reg,
- CONST0_RTX (SImode)),
+ gen_rtx_fmt_ee (move_code,
+ VOIDmode,
+ cmp_reg,
+ const0_rtx),
operands[2], operands[3])));
}
op1 = force_reg (mode, op1);
emit_insn (gen_rtx_TRAP_IF (VOIDmode,
- gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
+ gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
+ op0, op1),
operands[1]));
}
\f
+/* Load function address ADDR into register DEST. SIBCALL_P is true
+ if the address is needed for a sibling call. */
+
+static void
+mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
+{
+ /* If we're generating PIC, and this call is to a global function,
+ try to allow its address to be resolved lazily. This isn't
+ possible for NewABI sibcalls since the value of $gp on entry
+ to the stub would be our caller's gp, not ours. */
+ if (TARGET_EXPLICIT_RELOCS
+ && !(sibcall_p && TARGET_NEWABI)
+ && global_got_operand (addr, VOIDmode))
+ {
+ rtx high, lo_sum_symbol;
+
+ high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
+ addr, SYMBOL_GOTOFF_CALL);
+ lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
+ if (Pmode == SImode)
+ emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
+ else
+ emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
+ }
+ else
+ emit_move_insn (dest, addr);
+}
+
+
/* Expand a call or call_value instruction. RESULT is where the
result will go (null for calls), ADDR is the address of the
function, ARGS_SIZE is the size of the arguments and AUX is
void
mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
{
+ rtx orig_addr, pattern, insn;
+
+ orig_addr = addr;
if (!call_insn_operand (addr, VOIDmode))
{
- if (TARGET_EXPLICIT_RELOCS && global_got_operand (addr, VOIDmode))
- {
- rtx high = mips_unspec_offset_high (pic_offset_table_rtx,
- addr, SYMBOL_GOTOFF_CALL);
- addr = mips_load_got (high, addr, SYMBOL_GOTOFF_CALL);
- }
- addr = force_reg (Pmode, addr);
+ addr = gen_reg_rtx (Pmode);
+ mips_load_call_address (addr, orig_addr, sibcall_p);
}
if (TARGET_MIPS16
&& mips16_hard_float
&& build_mips16_call_stub (result, addr, args_size,
aux == 0 ? 0 : (int) GET_MODE (aux)))
- /* Nothing more to do */;
- else if (result == 0)
- emit_call_insn (sibcall_p
- ? gen_sibcall_internal (addr, args_size)
- : gen_call_internal (addr, args_size));
+ return;
+
+ if (result == 0)
+ pattern = (sibcall_p
+ ? gen_sibcall_internal (addr, args_size)
+ : gen_call_internal (addr, args_size));
else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
{
rtx reg1, reg2;
reg1 = XEXP (XVECEXP (result, 0, 0), 0);
reg2 = XEXP (XVECEXP (result, 0, 1), 0);
- emit_call_insn
+ pattern =
(sibcall_p
? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
: gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
}
else
- emit_call_insn (sibcall_p
- ? gen_sibcall_value_internal (result, addr, args_size)
- : gen_call_value_internal (result, addr, args_size));
+ pattern = (sibcall_p
+ ? gen_sibcall_value_internal (result, addr, args_size)
+ : gen_call_value_internal (result, addr, args_size));
+
+ insn = emit_call_insn (pattern);
+
+ /* Lazy-binding stubs require $gp to be valid on entry. */
+ if (global_got_operand (orig_addr, VOIDmode))
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
}
the source has enough alignment, otherwise use left/right pairs. */
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
{
- rtx part;
-
regs[i] = gen_reg_rtx (mode);
- part = adjust_address (src, mode, offset);
- if (MEM_ALIGN (part) >= bits)
- emit_move_insn (regs[i], part);
- else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
- abort ();
+ if (MEM_ALIGN (src) >= bits)
+ emit_move_insn (regs[i], adjust_address (src, mode, offset));
+ else
+ {
+ rtx part = adjust_address (src, BLKmode, offset);
+ if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
+ abort ();
+ }
}
/* Copy the chunks to the destination. */
for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
- {
- rtx part;
-
- part = adjust_address (dest, mode, offset);
- if (MEM_ALIGN (part) >= bits)
- emit_move_insn (part, regs[i]);
- else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
- abort ();
- }
+ if (MEM_ALIGN (dest) >= bits)
+ emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
+ else
+ {
+ rtx part = adjust_address (dest, BLKmode, offset);
+ if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
+ abort ();
+ }
/* Mop up any left-over bytes. */
if (offset < length)
{
- src = adjust_address (src, mode, offset);
- dest = adjust_address (dest, mode, offset);
+ src = adjust_address (src, BLKmode, offset);
+ dest = adjust_address (dest, BLKmode, offset);
move_by_pieces (dest, src, length - offset,
MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
}
static CUMULATIVE_ARGS zero_cum;
tree param, next_param;
- if (TARGET_DEBUG_E_MODE)
- {
- fprintf (stderr,
- "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
-
- if (!fntype)
- fputc ('\n', stderr);
-
- else
- {
- tree ret_type = TREE_TYPE (fntype);
- fprintf (stderr, ", fntype code = %s, ret code = %s\n",
- tree_code_name[(int)TREE_CODE (fntype)],
- tree_code_name[(int)TREE_CODE (ret_type)]);
- }
- }
-
- *cum = zero_cum;
- cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
+ *cum = zero_cum;
+ cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
/* Determine if this function has variable arguments. This is
indicated by the last argument being 'void_type_mode' if there
if (type != 0
&& TREE_CODE (type) == RECORD_TYPE
- && (mips_abi == ABI_N32 || mips_abi == ABI_64)
+ && TARGET_NEWABI
&& TYPE_SIZE_UNIT (type)
&& host_integerp (TYPE_SIZE_UNIT (type), 1)
&& named)
return mips_pad_arg_upward (mode, type);
}
\f
-int
-mips_setup_incoming_varargs (const CUMULATIVE_ARGS *cum,
- enum machine_mode mode, tree type, int no_rtl)
+static void
+mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+ tree type, int *pretend_size, int no_rtl)
{
CUMULATIVE_ARGS local_cum;
int gp_saved, fp_saved;
if (fp_saved > 0)
{
/* We can't use move_block_from_reg, because it will use
- the wrong mode. */
+ the wrong mode. */
enum machine_mode mode;
int off, i;
/* Set OFF to the offset from virtual_incoming_args_rtx of
- the first float register. The FP save area lies below
+ the first float register. The FP save area lies below
the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
off = -gp_saved * UNITS_PER_WORD;
off &= ~(UNITS_PER_FPVALUE - 1);
}
}
}
- if (mips_abi == ABI_32 || mips_abi == ABI_O64)
- /* No need for pretend arguments: the register parameter area was
- allocated by the caller. */
- return 0;
- return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
+ if (TARGET_OLDABI)
+ {
+ /* No need for pretend arguments: the register parameter area was
+ allocated by the caller. */
+ *pretend_size = 0;
+ return;
+ }
+ *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
}
/* Create the va_list data type.
tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
tree array, index;
- record = make_node (RECORD_TYPE);
+ record = (*lang_hooks.types.make_type) (RECORD_TYPE);
f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
ptr_type_node);
f_goff = TREE_CHAIN (f_ftop);
f_foff = TREE_CHAIN (f_goff);
- ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
- gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
- ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
- goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
- foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
+ ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
+ NULL_TREE);
+ gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
+ NULL_TREE);
+ ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
+ NULL_TREE);
+ goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
+ NULL_TREE);
+ foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
+ NULL_TREE);
/* Emit code to initialize OVFL, which points to the next varargs
stack argument. CUM->STACK_WORDS gives the number of stack
rsize = UNITS_PER_WORD;
}
- addr_rtx = gen_reg_rtx (Pmode);
-
if (!EABI_FLOAT_VARARGS_P)
{
/* Case of all args in a merged stack. No need to check bounds,
/* Emit code to set addr_rtx to the valist, and postincrement
the valist by the size of the argument, rounded up to the
- next word. */
+ next word. Account for padding on big-endian targets. */
t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
size_int (rsize));
- r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
- if (r != addr_rtx)
- emit_move_insn (addr_rtx, r);
+ addr_rtx = expand_expr (t, 0, Pmode, EXPAND_NORMAL);
+ if (BYTES_BIG_ENDIAN)
+ addr_rtx = plus_constant (addr_rtx, rsize - size);
/* Flush the POSTINCREMENT. */
emit_queue();
rtx lab_over = NULL_RTX, lab_false;
HOST_WIDE_INT osize;
+ addr_rtx = gen_reg_rtx (Pmode);
+
f_ovfl = TYPE_FIELDS (va_list_type_node);
f_gtop = TREE_CHAIN (f_ovfl);
f_ftop = TREE_CHAIN (f_gtop);
lab_false = gen_label_rtx ();
lab_over = gen_label_rtx ();
- ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
+ ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
+ NULL_TREE);
if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
&& GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
{
- top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
- off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
+ top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
+ NULL_TREE);
+ off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
+ NULL_TREE);
/* When floating-point registers are saved to the stack,
each one will take up UNITS_PER_HWFPVALUE bytes, regardless
of the float's precision. */
rsize = UNITS_PER_HWFPVALUE;
+
+ /* Overflow arguments are padded to UNITS_PER_WORD bytes
+ (= PARM_BOUNDARY bits). This can be different from RSIZE
+ in two cases:
+
+ (1) On 32-bit targets when TYPE is a structure such as:
+
+ struct s { float f; };
+
+ Such structures are passed in paired FPRs, so RSIZE
+ will be 8 bytes. However, the structure only takes
+ up 4 bytes of memory, so OSIZE will only be 4.
+
+ (2) In combinations such as -mgp64 -msingle-float
+ -fshort-double. Doubles passed in registers
+ will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
+ but those passed on the stack take up
+ UNITS_PER_WORD bytes. */
+ osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
}
else
{
- top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
- off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
+ top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
+ NULL_TREE);
+ off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
+ NULL_TREE);
if (rsize > UNITS_PER_WORD)
{
/* [1] Emit code for: off &= -rsize. */
t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
+ osize = rsize;
}
- /* Every overflow argument must take up at least UNITS_PER_WORD
- bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
- than that, such as in the combination -mgp64 -msingle-float
- -fshort-double. Doubles passed in registers will then take
- up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
- take up UNITS_PER_WORD bytes. */
- osize = MAX (rsize, UNITS_PER_WORD);
/* [2] Emit code to branch if off == 0. */
r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
1, lab_false);
- /* [4] Emit code for: addr_rtx = top - off. */
+ /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
+ the argument has RSIZE - SIZE bytes of leading padding. */
t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
+ if (BYTES_BIG_ENDIAN && rsize > size)
+ t = build (PLUS_EXPR, TREE_TYPE (t), t,
+ build_int_2 (rsize - size, 0));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
emit_move_insn (addr_rtx, r);
/* [10, 11]. Emit code to store ovfl in addr_rtx, then
post-increment ovfl by osize. On big-endian machines,
- the argument has OSIZE - RSIZE bytes of leading padding. */
+ the argument has OSIZE - SIZE bytes of leading padding. */
t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
size_int (osize));
- if (BYTES_BIG_ENDIAN && osize > rsize)
+ if (BYTES_BIG_ENDIAN && osize > size)
t = build (PLUS_EXPR, TREE_TYPE (t), t,
- build_int_2 (osize - rsize, 0));
+ build_int_2 (osize - size, 0));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
emit_move_insn (addr_rtx, r);
emit_queue();
emit_label (lab_over);
}
- if (BYTES_BIG_ENDIAN && rsize != size)
- addr_rtx = plus_constant (addr_rtx, rsize - size);
if (indirect)
{
addr_rtx = force_reg (Pmode, addr_rtx);
that alignments <= UNITS_PER_WORD are preserved by the va_arg
increment mechanism. */
- if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
- && TYPE_ALIGN (type) > 64)
+ if (TARGET_NEWABI && TYPE_ALIGN (type) > 64)
align = 16;
else if (TARGET_64BIT)
align = 8;
first = adjust_address (*op, QImode, 0);
last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
- /* Allocate to LEFT and RIGHT according to endiannes. LEFT should
+ /* Allocate to LEFT and RIGHT according to endianness. LEFT should
be the upper word and RIGHT the lower word. */
if (TARGET_BIG_ENDIAN)
*left = first, *right = last;
bool
mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
{
- rtx left, right;
+ rtx left, right, temp;
/* If TARGET_64BIT, the destination of a 32-bit load will be a
paradoxical word_mode subreg. This is the only case in which
if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
return false;
+ temp = gen_reg_rtx (GET_MODE (dest));
if (GET_MODE (dest) == DImode)
{
- emit_insn (gen_mov_ldl (dest, src, left));
- emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
- right, copy_rtx (dest)));
+ emit_insn (gen_mov_ldl (temp, src, left));
+ emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
}
else
{
- emit_insn (gen_mov_lwl (dest, src, left));
- emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
- right, copy_rtx (dest)));
+ emit_insn (gen_mov_lwl (temp, src, left));
+ emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
}
return true;
}
case PROCESSOR_R4100:
case PROCESSOR_R4111:
case PROCESSOR_R4120:
+ case PROCESSOR_R4130:
target_flags |= MASK_SOFT_FLOAT;
break;
}
}
- if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+ if (!TARGET_OLDABI)
flag_pcc_struct_return = 0;
#if defined(USE_COLLECT2)
if (TARGET_SGI_O32_AS)
{
- /* They don't recognize `.[248]byte'. */
+ /* They don't recognize `.[248]byte'. */
targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
/* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
/* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
so -mabi=32 isn't usually specified. */
if (TARGET_IRIX5)
- warning ("-g is only supported using GNU as,");
+ inform ("-g is only supported using GNU as,");
else
- warning ("-g is only supported using GNU as with -mabi=32,");
- warning ("-g option disabled");
+ inform ("-g is only supported using GNU as with -mabi=32,");
+ inform ("-g option disabled");
write_symbols = NO_DEBUG;
}
}
architecture.
By default, we enable use of Branch Likely instructions on
- all architectures which support them except for MIPS32 and MIPS64
- (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
- implement them).
+ all architectures which support them with the following
+ exceptions: when creating MIPS32 or MIPS64 code, and when
+ tuning for architectures where their use tends to hurt
+ performance.
The MIPS32 and MIPS64 architecture specifications say "Software
is strongly encouraged to avoid use of Branch Likely
of the [MIPS32 and MIPS64] architecture." Therefore, we do not
issue those instructions unless instructed to do so by
-mbranch-likely. */
- if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
+ if (ISA_HAS_BRANCHLIKELY
+ && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
+ && !(TUNE_MIPS5500 || TUNE_SB1))
target_flags |= MASK_BRANCHLIKELY;
else
target_flags &= ~MASK_BRANCHLIKELY;
if (!targetm.have_named_sections)
mips_section_threshold = 0;
- /* -membedded-pic is a form of PIC code suitable for embedded
- systems. All calls are made using PC relative addressing, and
- all data is addressed using the $gp register. This requires gas,
- which does most of the work, and GNU ld, which automatically
- expands PC relative calls which are out of range into a longer
- instruction sequence. All gcc really does differently is
- generate a different sequence for a switch. */
- if (TARGET_EMBEDDED_PIC)
- {
- flag_pic = 1;
- if (TARGET_ABICALLS)
- warning ("-membedded-pic and -mabicalls are incompatible");
-
- if (g_switch_set)
- warning ("-G and -membedded-pic are incompatible");
-
- /* Setting mips_section_threshold is not required, because gas
- will force everything to be GP addressable anyhow, but
- setting it will cause gcc to make better estimates of the
- number of instructions required to access a particular data
- item. */
- mips_section_threshold = 0x7fffffff;
- }
-
/* mips_split_addresses is a half-way house between explicit
relocations and the traditional assembler macros. It can
split absolute 32-bit symbolic constants into a high/lo_sum
else
mips_split_addresses = 0;
- /* -mexplicit-relocs doesn't yet support non-PIC n64. We don't know
- how to generate %highest/%higher/%hi/%lo sequences. */
- if (mips_abi == ABI_64 && !TARGET_ABICALLS)
- {
- if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
- sorry ("non-PIC n64 with explicit relocations");
- target_flags &= ~MASK_EXPLICIT_RELOCS;
- }
-
/* Explicit relocations for "old" ABIs are a GNU extension. Unless
the user has said otherwise, assume that they are not available
with assemblers other than gas. */
&& (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
target_flags &= ~MASK_EXPLICIT_RELOCS;
+ /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
+ unless the user says otherwise.
+
+ There are two problems here:
+
+ (1) The value of an R_MIPS_GOT16 relocation depends on whether
+ the symbol is local or global. We therefore need to know
+ a symbol's binding before referring to it using %got().
+
+ (2) R_MIPS_CALL16 can only be applied to global symbols.
+
+ When not using -funit-at-a-time, a symbol's binding may change
+ after it has been used. For example, the C++ front-end will
+ initially assume that the typeinfo for an incomplete type will be
+ comdat, on the basis that the type could be completed later in the
+ file. But if the type never is completed, the typeinfo will become
+ local instead. */
+ if (!flag_unit_at_a_time
+ && TARGET_ABICALLS
+ && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
+ target_flags &= ~MASK_EXPLICIT_RELOCS;
+
/* -mrnames says to use the MIPS software convention for register
names instead of the hardware names (ie, $a0 instead of $4).
We do this by switching the names in mips_reg_names, which the
if (TARGET_NAME_REGS)
memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
+ /* -mvr4130-align is a "speed over size" optimization: it usually produces
+ faster code, but at the expense of more nops. Enable it at -O3 and
+ above. */
+ if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
+ target_flags |= MASK_VR4130_ALIGN;
+
/* When compiling for the mips16, we can not use floating point. We
record the original hard float value in mips16_hard_float. */
if (TARGET_MIPS16)
mips_print_operand_punct['~'] = 1;
mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
- mips_char_to_class['e'] = M16_NA_REGS;
mips_char_to_class['t'] = T_REG;
mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
mips_char_to_class['h'] = HI_REG;
|| (ISA_HAS_8CC && mode == TFmode));
else if (MD_REG_P (regno))
- temp = (class == MODE_INT
+ temp = (INTEGRAL_MODE_P (mode)
&& (size <= UNITS_PER_WORD
|| (regno == MD_REG_FIRST
&& size == 2 * UNITS_PER_WORD)));
/* Function to allocate machine-dependent function status. */
init_machine_status = &mips_init_machine_status;
- /* Create a unique alias set for GOT references. */
- mips_got_alias_set = new_alias_set ();
+ if (ABI_HAS_64BIT_SYMBOLS)
+ {
+ if (TARGET_EXPLICIT_RELOCS)
+ {
+ mips_split_p[SYMBOL_64_HIGH] = true;
+ mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
+ mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
+
+ mips_split_p[SYMBOL_64_MID] = true;
+ mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
+ mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
+
+ mips_split_p[SYMBOL_64_LOW] = true;
+ mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
+ mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
- if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
+ mips_split_p[SYMBOL_GENERAL] = true;
+ mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
+ }
+ }
+ else
{
- mips_split_p[SYMBOL_GENERAL] = true;
- mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
- mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
+ if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
+ {
+ mips_split_p[SYMBOL_GENERAL] = true;
+ mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
+ mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
+ }
}
if (TARGET_MIPS16)
mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
}
+
+ /* Default to working around R4000 errata only if the processor
+ was selected explicitly. */
+ if ((target_flags_explicit & MASK_FIX_R4000) == 0
+ && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
+ target_flags |= MASK_FIX_R4000;
+
+ /* Default to working around R4400 errata only if the processor
+ was selected explicitly. */
+ if ((target_flags_explicit & MASK_FIX_R4400) == 0
+ && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
+ target_flags |= MASK_FIX_R4400;
}
/* Implement CONDITIONAL_REGISTER_USAGE. */
for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
call_really_used_regs[regno] = call_used_regs[regno] = 1;
}
- /* odd registers from fp21 to fp31 are now caller saved. */
+ /* Odd registers from fp21 to fp31 are now caller saved. */
if (mips_abi == ABI_N32)
{
int regno;
'F' print part of opcode for a floating-point branch condition.
'N' print part of opcode for a branch condition, inverted.
'W' print part of opcode for a floating-point branch condition, inverted.
- 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
'B' print 'z' for EQ, 'n' for NE
'b' print 'n' for EQ, 'z' for NE
'T' print 'f' for EQ, 't' for NE
else if (letter == 'R')
print_operand_reloc (file, op, mips_lo_relocs);
- else if (letter == 'S')
- {
- char buffer[100];
-
- ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
- assemble_name (file, buffer);
- }
-
else if (letter == 'Z')
{
register int regnum;
fputs (code == EQ ? "t" : "f", file);
else if (CONST_GP_P (op))
- print_operand (file, XEXP (op, 0), letter);
+ fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
else
output_addr_const (file, op);
fputc (')', file);
}
\f
-/* Output address operand X to FILE. */
+/* Output address operand X to FILE. */
void
print_operand_address (FILE *file, rtx x)
extern_head = p;
}
- if (TARGET_IRIX && mips_abi == ABI_32
- && TREE_CODE (decl) == FUNCTION_DECL
- /* ??? Don't include alloca, since gcc will always expand it
- inline. If we don't do this, the C++ library fails to build. */
- && strcmp (name, "alloca")
- /* ??? Don't include __builtin_next_arg, because then gcc will not
- bootstrap under Irix 5.1. */
- && strcmp (name, "__builtin_next_arg"))
+ if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
{
p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
p->next = extern_head;
}
}
\f
-/* Output an ASCII string, in a space-saving way. */
+/* Output an ASCII string, in a space-saving way. PREFIX is the string
+ that should be written before the opening quote, such as "\t.ascii\t"
+ for real string data or "\t# " for a comment. */
void
-mips_output_ascii (FILE *stream, const char *string_param, size_t len)
+mips_output_ascii (FILE *stream, const char *string_param, size_t len,
+ const char *prefix)
{
size_t i;
int cur_pos = 17;
register const unsigned char *string =
(const unsigned char *)string_param;
- fprintf (stream, "\t.ascii\t\"");
+ fprintf (stream, "%s\"", prefix);
for (i = 0; i < len; i++)
{
register int c = string[i];
if (cur_pos > 72 && i+1 < len)
{
cur_pos = 17;
- fprintf (stream, "\"\n\t.ascii\t\"");
+ fprintf (stream, "\"\n%s\"", prefix);
}
}
fprintf (stream, "\"\n");
executable. */
fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
+ /* There is no ELF header flag to distinguish long32 forms of the
+ EABI from long64 forms. Emit a special section to help tools
+ such as GDB. */
+ if (mips_abi == ABI_EABI)
+ fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
+ TARGET_LONG64 ? 64 : 32);
+
/* Restore the default section. */
fprintf (asm_out_file, "\t.previous\n");
#endif
name_tree = get_identifier (p->name);
/* Positively ensure only one .extern for any given symbol. */
- if (! TREE_ASM_WRITTEN (name_tree))
+ if (!TREE_ASM_WRITTEN (name_tree)
+ && TREE_SYMBOL_REFERENCED (name_tree))
{
TREE_ASM_WRITTEN (name_tree) = 1;
/* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
when it is unsafe. */
if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
{
- fputs ("\t.globl ", asm_out_file);
+ fputs ("\t.globl ", asm_out_file);
assemble_name (asm_out_file, p->name);
fputs (" .text\n", asm_out_file);
}
}
}
+/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
+ the elfos.h version, but we also need to handle -muninit-const-in-rodata
+ and the limitations of the SGI o32 assembler. */
+
+void
+mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
+ unsigned HOST_WIDE_INT size,
+ unsigned int align)
+{
+ /* If the target wants uninitialized const declarations in
+ .rdata then don't put them in .comm. */
+ if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
+ && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
+ && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
+ {
+ if (TREE_PUBLIC (decl) && DECL_NAME (decl))
+ targetm.asm_out.globalize_label (stream, name);
+
+ readonly_data_section ();
+ ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
+ mips_declare_object (stream, name, "",
+ ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
+ size);
+ }
+ else if (TARGET_SGI_O32_AS)
+ {
+ /* The SGI o32 assembler doesn't accept an alignment, so round up
+ the size instead. */
+ size += (align / BITS_PER_UNIT) - 1;
+ size -= size % (align / BITS_PER_UNIT);
+ mips_declare_object (stream, name, "\n\t.comm\t",
+ "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
+ }
+ else
+ mips_declare_object (stream, name, "\n\t.comm\t",
+ "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
+ size, align / BITS_PER_UNIT);
+}
+
/* Emit either a label, .comm, or .lcomm directive. When using assembler
macros, mark the symbol as written so that mips_file_end won't emit an
- .extern for it. */
+ .extern for it. STREAM is the output file, NAME is the name of the
+ symbol, INIT_STRING is the string that should be written before the
+ symbol and FINAL_STRING is the string that should be written after it.
+ FINAL_STRING is a printf() format that consumes the remaining arguments. */
void
mips_declare_object (FILE *stream, const char *name, const char *init_string,
- const char *final_string, int size)
+ const char *final_string, ...)
{
- fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
+ va_list ap;
+
+ fputs (init_string, stream);
assemble_name (stream, name);
- fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
+ va_start (ap, final_string);
+ vfprintf (stream, final_string, ap);
+ va_end (ap);
if (!TARGET_EXPLICIT_RELOCS)
{
if (current_function_profile)
return GLOBAL_POINTER_REGNUM;
+ /* If the function has a nonlocal goto, $gp must hold the correct
+ global pointer for the target function. */
+ if (current_function_has_nonlocal_goto)
+ return GLOBAL_POINTER_REGNUM;
+
/* If the gp is never referenced, there's no need to initialize it.
Note that reload can sometimes introduce constant pool references
into a function that otherwise didn't need them. For example,
/* Add in space reserved on the stack by the callee for storing arguments
passed in registers. */
- if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+ if (!TARGET_OLDABI)
total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
/* Save other computed information. */
case ARG_POINTER_REGNUM:
offset = cfun->machine->frame.total_size;
- if (mips_abi == ABI_N32 || mips_abi == ABI_64)
+ if (TARGET_NEWABI)
offset -= current_function_pretend_args_size;
break;
#undef BITSET_P
}
\f
+/* If we're generating n32 or n64 abicalls, and the current function
+ does not use $28 as its global pointer, emit a cplocal directive.
+ Use pic_offset_table_rtx as the argument to the directive. */
+
+static void
+mips_output_cplocal (void)
+{
+ if (!TARGET_EXPLICIT_RELOCS
+ && cfun->machine->global_pointer > 0
+ && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
+ output_asm_insn (".cplocal %+", 0);
+}
+
+/* If we're generating n32 or n64 abicalls, emit instructions
+ to set up the global pointer. */
+
+static void
+mips_emit_loadgp (void)
+{
+ if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
+ {
+ rtx addr, offset, incoming_address;
+
+ addr = XEXP (DECL_RTL (current_function_decl), 0);
+ offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
+ incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ emit_insn (gen_loadgp (offset, incoming_address));
+ if (!TARGET_EXPLICIT_RELOCS)
+ emit_insn (gen_loadgp_blockage ());
+ }
+}
+
/* Set up the stack and frame (if desired) for the function. */
static void
}
else if (cfun->machine->all_noreorder_p)
output_asm_insn ("%(%<", 0);
+
+ /* Tell the assembler which register we're using as the global
+ pointer. This is needed for thunks, since they can use either
+ explicit relocs or assembler macros. */
+ mips_output_cplocal ();
}
\f
/* Make the last instruction frame related and note that it performs
/* Set up the frame pointer, if we're using one. In mips16 code,
we point the frame pointer ahead of the outgoing argument area.
This should allow more variables & incoming arguments to be
- acceesed with unextended instructions. */
+ accessed with unextended instructions. */
if (frame_pointer_needed)
{
if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
- /* If generating n32/n64 abicalls, emit the instructions to load $gp. */
- if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
- {
- rtx addr, offset, incoming_address;
-
- addr = XEXP (DECL_RTL (current_function_decl), 0);
- offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
- incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
- emit_insn (gen_loadgp (offset, incoming_address));
- if (!TARGET_EXPLICIT_RELOCS)
- emit_insn (gen_loadgp_blockage ());
- }
+ mips_emit_loadgp ();
/* If we are profiling, make sure no instructions are scheduled before
the call to mcount. */
and regs. */
#define RA_MASK BITMASK_HIGH /* 1 << 31 */
-#define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
static void
mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
- rtx string;
+ /* Reinstate the normal $gp. */
+ REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
+ mips_output_cplocal ();
if (cfun->machine->all_noreorder_p)
{
assemble_name (file, fnname);
fputs ("\n", file);
}
-
- while (string_constants != NULL)
- {
- struct string_constant *next;
-
- next = string_constants->next;
- free (string_constants);
- string_constants = next;
- }
-
- /* If any following function uses the same strings as this one, force
- them to refer those strings indirectly. Nearby functions could
- refer them using pc-relative addressing, but it isn't safe in
- general. For instance, some functions may be placed in sections
- other than .text, and we don't know whether they be close enough
- to this one. In large files, even other .text functions can be
- too far away. */
- for (string = mips16_strings; string != 0; string = XEXP (string, 1))
- SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
- free_EXPR_LIST_list (&mips16_strings);
-
- /* Reinstate the normal $gp. */
- REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
}
\f
/* Emit instructions to restore register REG from slot MEM. */
emit_insn (gen_add3_insn (stack_pointer_rtx,
stack_pointer_rtx,
GEN_INT (step2)));
-
- /* Add in the __builtin_eh_return stack adjustment. We need to
+
+ /* Add in the __builtin_eh_return stack adjustment. We need to
use a temporary in mips16 code. */
if (current_function_calls_eh_return)
{
{
/* The mips16 loads the return address into $7, not $31. */
if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
- emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
- GP_REG_FIRST + 7)));
+ emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
+ GP_REG_FIRST + 7)));
else
- emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
- GP_REG_FIRST + 31)));
+ emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
+ GP_REG_FIRST + 31)));
}
}
\f
return compute_frame_size (get_frame_size ()) == 0;
}
\f
+/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
+ in order to avoid duplicating too much logic from elsewhere. */
+
+static void
+mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+ tree function)
+{
+ rtx this, temp1, temp2, insn, fnaddr;
+
+ /* Pretend to be a post-reload pass while generating rtl. */
+ no_new_pseudos = 1;
+ reload_completed = 1;
+ reset_block_changes ();
+
+ /* Pick a global pointer for -mabicalls. Use $15 rather than $28
+ for TARGET_NEWABI since the latter is a call-saved register. */
+ if (TARGET_ABICALLS)
+ cfun->machine->global_pointer
+ = REGNO (pic_offset_table_rtx)
+ = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
+
+ /* Set up the global pointer for n32 or n64 abicalls. */
+ mips_emit_loadgp ();
+
+ /* We need two temporary registers in some cases. */
+ temp1 = gen_rtx_REG (Pmode, 2);
+ temp2 = gen_rtx_REG (Pmode, 3);
+
+ /* Find out which register contains the "this" pointer. */
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
+ this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
+ else
+ this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
+
+ /* Add DELTA to THIS. */
+ if (delta != 0)
+ {
+ rtx offset = GEN_INT (delta);
+ if (!SMALL_OPERAND (delta))
+ {
+ emit_move_insn (temp1, offset);
+ offset = temp1;
+ }
+ emit_insn (gen_add3_insn (this, this, offset));
+ }
+
+ /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
+ if (vcall_offset != 0)
+ {
+ rtx addr;
+
+ /* Set TEMP1 to *THIS. */
+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
+
+ /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
+ if (SMALL_OPERAND (vcall_offset))
+ addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
+ else if (TARGET_MIPS16)
+ {
+ /* Load the full offset into a register so that we can use
+ an unextended instruction for the load itself. */
+ emit_move_insn (temp2, GEN_INT (vcall_offset));
+ emit_insn (gen_add3_insn (temp1, temp1, temp2));
+ addr = temp1;
+ }
+ else
+ {
+ /* Load the high part of the offset into a register and
+ leave the low part for the address. */
+ emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
+ emit_insn (gen_add3_insn (temp1, temp1, temp2));
+ addr = gen_rtx_PLUS (Pmode, temp1,
+ GEN_INT (CONST_LOW_PART (vcall_offset)));
+ }
+
+ /* Load the offset and add it to THIS. */
+ emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
+ emit_insn (gen_add3_insn (this, this, temp1));
+ }
+
+ /* Jump to the target function. Use a sibcall if direct jumps are
+ allowed, otherwise load the address into a register first. */
+ fnaddr = XEXP (DECL_RTL (function), 0);
+ if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
+ {
+ /* This is messy. gas treats "la $25,foo" as part of a call
+ sequence and may allow a global "foo" to be lazily bound.
+ The general move patterns therefore reject this combination.
+
+ In this context, lazy binding would actually be OK for o32 and o64,
+ but it's still wrong for n32 and n64; see mips_load_call_address.
+ We must therefore load the address via a temporary register if
+ mips_dangerous_for_la25_p.
+
+ If we jump to the temporary register rather than $25, the assembler
+ can use the move insn to fill the jump's delay slot. */
+ if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
+ temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
+ mips_load_call_address (temp1, fnaddr, true);
+
+ if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
+ emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
+ emit_jump_insn (gen_indirect_jump (temp1));
+ }
+ else
+ {
+ insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
+ SIBLING_CALL_P (insn) = 1;
+ }
+
+ /* Run just enough of rest_of_compilation. This sequence was
+ "borrowed" from alpha.c. */
+ insn = get_insns ();
+ insn_locators_initialize ();
+ split_all_insns_noflow ();
+ if (TARGET_MIPS16)
+ mips16_lay_out_constants ();
+ shorten_branches (insn);
+ final_start_function (insn, file, 1);
+ final (insn, file, 1, 0);
+ final_end_function ();
+
+ /* Clean up the vars set above. Note that final_end_function resets
+ the global pointer for us. */
+ reload_completed = 0;
+ no_new_pseudos = 0;
+}
+\f
/* Returns nonzero if X contains a SYMBOL_REF. */
static int
if (GET_CODE (x) == CONST)
return symbolic_expression_p (XEXP (x, 0));
- if (GET_RTX_CLASS (GET_CODE (x)) == '1')
+ if (UNARY_P (x))
return symbolic_expression_p (XEXP (x, 0));
- if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
- || GET_RTX_CLASS (GET_CODE (x)) == '2')
+ if (ARITHMETIC_P (x))
return (symbolic_expression_p (XEXP (x, 0))
|| symbolic_expression_p (XEXP (x, 1)));
mips_select_section (tree decl, int reloc,
unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
{
- if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
- && TREE_CODE (decl) == STRING_CST
- && !flag_writable_strings)
- /* For embedded position independent code, put constant strings in the
- text section, because the data section is limited to 64K in size.
- For mips16 code, put strings in the text section so that a PC
- relative load instruction can be used to get their address. */
- text_section ();
- else if (targetm.have_named_sections)
+ if (targetm.have_named_sections)
default_elf_select_section (decl, reloc, align);
else
/* The native irix o32 assembler doesn't support named sections. */
if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
return false;
+ /* We don't yet generate small-data references for -mabicalls. See related
+ -G handling in override_options. */
+ if (TARGET_ABICALLS)
+ return false;
+
if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
{
const char *name;
size = int_size_in_bytes (TREE_TYPE (decl));
return (size > 0 && size <= mips_section_threshold);
}
-
-
-/* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
- symbols which are not in the .text section.
-
- When generating mips16 code, SYMBOL_REF_FLAG is set for string
- constants which are put in the .text section. We also record the
- total length of all such strings; this total is used to decide
- whether we need to split the constant table, and need not be
- precisely correct.
-
- When generating -mabicalls code, SYMBOL_REF_FLAG is set if we
- should treat the symbol as SYMBOL_GOT_LOCAL. */
-
-static void
-mips_encode_section_info (tree decl, rtx rtl, int first)
-{
- rtx symbol;
-
- if (GET_CODE (rtl) != MEM)
- return;
-
- symbol = XEXP (rtl, 0);
-
- if (GET_CODE (symbol) != SYMBOL_REF)
- return;
-
- if (TARGET_MIPS16)
- {
- if (first && TREE_CODE (decl) == STRING_CST
- && ! flag_writable_strings
- /* If this string is from a function, and the function will
- go in a gnu linkonce section, then we can't directly
- access the string. This gets an assembler error
- "unsupported PC relative reference to different section".
- If we modify SELECT_SECTION to put it in function_section
- instead of text_section, it still fails because
- DECL_SECTION_NAME isn't set until assemble_start_function.
- If we fix that, it still fails because strings are shared
- among multiple functions, and we have cross section
- references again. We force it to work by putting string
- addresses in the constant pool and indirecting. */
- && (! current_function_decl
- || ! DECL_ONE_ONLY (current_function_decl)))
- {
- mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
- SYMBOL_REF_FLAG (symbol) = 1;
- mips_string_length += TREE_STRING_LENGTH (decl);
- }
- }
-
- if (TARGET_EMBEDDED_PIC)
- {
- if (TREE_CODE (decl) == VAR_DECL)
- SYMBOL_REF_FLAG (symbol) = 1;
- else if (TREE_CODE (decl) == FUNCTION_DECL)
- SYMBOL_REF_FLAG (symbol) = 0;
- else if (TREE_CODE (decl) == STRING_CST
- && ! flag_writable_strings)
- SYMBOL_REF_FLAG (symbol) = 0;
- else
- SYMBOL_REF_FLAG (symbol) = 1;
- }
-
- else if (TARGET_ABICALLS)
- {
- /* Mark the symbol if we should treat it as SYMBOL_GOT_LOCAL.
- There are three cases to consider:
-
- - o32 PIC (either with or without explicit relocs)
- - n32/n64 PIC without explicit relocs
- - n32/n64 PIC with explicit relocs
-
- In the first case, both local and global accesses will use an
- R_MIPS_GOT16 relocation. We must correctly predict which of
- the two semantics (local or global) the assembler and linker
- will apply. The choice doesn't depend on the symbol's
- visibility, so we deliberately ignore decl_visibility and
- binds_local_p here.
-
- In the second case, the assembler will not use R_MIPS_GOT16
- relocations, but it chooses between local and global accesses
- in the same way as for o32 PIC.
-
- In the third case we have more freedom since both forms of
- access will work for any kind of symbol. However, there seems
- little point in doing things differently. */
- if (DECL_P (decl) && TREE_PUBLIC (decl))
- SYMBOL_REF_FLAG (symbol) = 0;
- else
- SYMBOL_REF_FLAG (symbol) = 1;
- }
-
- default_encode_section_info (decl, rtl, first);
-}
\f
/* See whether VALTYPE is a record whose fields should be returned in
floating-point registers. If so, return the number of fields and
int unsignedp;
mode = TYPE_MODE (valtype);
- unsignedp = TREE_UNSIGNED (valtype);
+ unsignedp = TYPE_UNSIGNED (valtype);
- /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
- the mode just as PROMOTE_MODE does. */
+ /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
+ true, we must promote the mode just as PROMOTE_MODE does. */
mode = promote_mode (valtype, mode, &unsignedp, 1);
/* Handle structures whose fields are returned in $f0/$f2. */
return false;
}
+/* Return true if X should not be moved directly into register $25.
+ We need this because many versions of GAS will treat "la $25,foo" as
+ part of a call sequence and so allow a global "foo" to be lazily bound. */
+
+bool
+mips_dangerous_for_la25_p (rtx x)
+{
+ HOST_WIDE_INT offset;
+
+ if (TARGET_EXPLICIT_RELOCS)
+ return false;
+
+ mips_split_const (x, &x, &offset);
+ return global_got_operand (x, VOIDmode);
+}
+
+/* Implement PREFERRED_RELOAD_CLASS. */
+
+enum reg_class
+mips_preferred_reload_class (rtx x, enum reg_class class)
+{
+ if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
+ return LEA_REGS;
+
+ if (TARGET_HARD_FLOAT
+ && FLOAT_MODE_P (GET_MODE (x))
+ && reg_class_subset_p (FP_REGS, class))
+ return FP_REGS;
+
+ if (reg_class_subset_p (GR_REGS, class))
+ class = GR_REGS;
+
+ if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
+ class = M16_REGS;
+
+ return class;
+}
+
/* This function returns the register class required for a secondary
register when copying between one of the registers in CLASS, and X,
using MODE. If IN_P is nonzero, the copy is going from X to the
gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
- if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25)
- && DANGEROUS_FOR_LA25_P (x))
- return LEA_REGS;
+ if (mips_dangerous_for_la25_p (x))
+ {
+ gr_regs = LEA_REGS;
+ if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
+ return gr_regs;
+ }
/* Copying from HI or LO to anywhere other than a general register
requires a general register. */
{
if (in_p)
return FP_REGS;
- return GP_REG_P (regno) ? NO_REGS : GR_REGS;
+ return gp_reg_p ? NO_REGS : gr_regs;
}
if (ST_REG_P (regno))
{
if (! in_p)
return FP_REGS;
- return class == GR_REGS ? NO_REGS : GR_REGS;
+ return class == gr_regs ? NO_REGS : gr_regs;
}
if (class == FP_REGS)
{
if (GET_CODE (x) == MEM)
{
- /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
+ /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
return NO_REGS;
}
else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
code by returning GR_REGS here. */
return NO_REGS;
}
- else if (GP_REG_P (regno) || x == CONST0_RTX (mode))
+ else if (gp_reg_p || x == CONST0_RTX (mode))
{
/* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
return NO_REGS;
else
{
/* Otherwise, we need to reload through an integer register. */
- return GR_REGS;
+ return gr_regs;
}
}
{
if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
{
- rtx const_gp;
+ rtx unspec;
rtx insn, scan;
cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
/* We want to initialize this to a value which gcc will believe
is constant. */
- const_gp = gen_rtx_CONST (Pmode, pic_offset_table_rtx);
start_sequence ();
+ unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
- const_gp);
+ gen_rtx_CONST (Pmode, unspec));
insn = get_insns ();
end_sequence ();
unsigned int f;
/* This code only works for the original 32 bit ABI and the O64 ABI. */
- if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+ if (!TARGET_OLDABI)
abort ();
if (from_fp_p)
build_function_type (void_type_node, NULL_TREE));
DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
- fprintf (file, "\t# Stub function for %s (", current_function_name);
+ fprintf (file, "\t# Stub function for %s (", current_function_name ());
need_comma = 0;
for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
{
/* This code will only work for o32 and o64 abis. The other ABI's
require more sophisticated support. */
- if (mips_abi != ABI_32 && mips_abi != ABI_O64)
+ if (!TARGET_OLDABI)
abort ();
/* We can only handle SFmode and DFmode floating point return
: ""),
fp_code);
id = get_identifier (buf);
- stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
+ stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
- emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
+ emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
if (retval == NULL_RTX)
insn = gen_call_internal (stub_fn, arg_size);
if (GET_CODE (insn) != CALL_INSN)
abort ();
CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx (EXPR_LIST, VOIDmode,
- gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
+ CALL_INSN_FUNCTION_USAGE (insn));
/* If we are handling a floating point return value, we need to
save $18 in the function prologue. Putting a note on the
code. */
if (fpret)
CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx (EXPR_LIST, VOIDmode,
- gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode,
+ gen_rtx_REG (word_mode, 18)),
+ CALL_INSN_FUNCTION_USAGE (insn));
/* Return 1 to tell the caller that we've generated the call
insn. */
abort ();
CALL_INSN_FUNCTION_USAGE (insn) =
- gen_rtx (EXPR_LIST, VOIDmode,
- gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
- CALL_INSN_FUNCTION_USAGE (insn));
+ gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
+ CALL_INSN_FUNCTION_USAGE (insn));
/* Return 1 to tell the caller that we've generated the call
insn. */
return 0;
}
-/* This function looks through the code for a function, and tries to
- optimize the usage of the $gp register. We arrange to copy $gp
- into a pseudo-register, and then let gcc's normal reload handling
- deal with the pseudo-register. Unfortunately, if reload choose to
- put the pseudo-register into a call-clobbered register, it will
- emit saves and restores for that register around any function
- calls. We don't need the saves, and it's faster to copy $gp than
- to do an actual restore. ??? This still means that we waste a
- stack slot.
-
- This is an optimization, and the code which gcc has actually
- generated is correct, so we do not need to catch all cases. */
+/* An entry in the mips16 constant pool. VALUE is the pool constant,
+ MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
-static void
-mips16_optimize_gp (void)
-{
- rtx gpcopy, slot, insn;
+struct mips16_constant {
+ struct mips16_constant *next;
+ rtx value;
+ rtx label;
+ enum machine_mode mode;
+};
- /* Look through the instructions. Set GPCOPY to the register which
- holds a copy of $gp. Set SLOT to the stack slot where it is
- saved. If we find an instruction which sets GPCOPY to anything
- other than $gp or SLOT, then we can't use it. If we find an
- instruction which sets SLOT to anything other than GPCOPY, we
- can't use it. */
+/* Information about an incomplete mips16 constant pool. FIRST is the
+ first constant, HIGHEST_ADDRESS is the highest address that the first
+ byte of the pool can have, and INSN_ADDRESS is the current instruction
+ address. */
- gpcopy = NULL_RTX;
- slot = NULL_RTX;
- for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
- {
- rtx set;
+struct mips16_constant_pool {
+ struct mips16_constant *first;
+ int highest_address;
+ int insn_address;
+};
- if (! INSN_P (insn))
- continue;
+/* Add constant VALUE to POOL and return its label. MODE is the
+ value's mode (used for CONST_INTs, etc.). */
- set = PATTERN (insn);
+static rtx
+add_constant (struct mips16_constant_pool *pool,
+ rtx value, enum machine_mode mode)
+{
+ struct mips16_constant **p, *c;
+ bool first_of_size_p;
- /* We know that all references to memory will be inside a SET,
- because there is no other way to access memory on the mips16.
- We don't have to worry about a PARALLEL here, because the
- mips.md file will never generate them for memory references. */
- if (GET_CODE (set) != SET)
- continue;
+ /* See whether the constant is already in the pool. If so, return the
+ existing label, otherwise leave P pointing to the place where the
+ constant should be added.
- if (gpcopy == NULL_RTX
- && GET_CODE (SET_SRC (set)) == CONST
- && XEXP (SET_SRC (set), 0) == pic_offset_table_rtx
- && GET_CODE (SET_DEST (set)) == REG)
- gpcopy = SET_DEST (set);
- else if (slot == NULL_RTX
- && gpcopy != NULL_RTX
- && GET_CODE (SET_DEST (set)) == MEM
- && GET_CODE (SET_SRC (set)) == REG
- && REGNO (SET_SRC (set)) == REGNO (gpcopy))
- {
- rtx base, offset;
-
- offset = const0_rtx;
- base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
- if (GET_CODE (base) == REG
- && (REGNO (base) == STACK_POINTER_REGNUM
- || REGNO (base) == FRAME_POINTER_REGNUM))
- slot = SET_DEST (set);
- }
- else if (gpcopy != NULL_RTX
- && (GET_CODE (SET_DEST (set)) == REG
- || GET_CODE (SET_DEST (set)) == SUBREG)
- && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
- && (GET_CODE (SET_DEST (set)) != REG
- || REGNO (SET_DEST (set)) != REGNO (gpcopy)
- || ((GET_CODE (SET_SRC (set)) != CONST
- || XEXP (SET_SRC (set), 0) != pic_offset_table_rtx)
- && ! rtx_equal_p (SET_SRC (set), slot))))
- break;
- else if (slot != NULL_RTX
- && GET_CODE (SET_DEST (set)) == MEM
- && rtx_equal_p (SET_DEST (set), slot)
- && (GET_CODE (SET_SRC (set)) != REG
- || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
+ Keep the pool sorted in increasing order of mode size so that we can
+ reduce the number of alignments needed. */
+ first_of_size_p = true;
+ for (p = &pool->first; *p != 0; p = &(*p)->next)
+ {
+ if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
+ return (*p)->label;
+ if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
break;
- }
+ if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
+ first_of_size_p = false;
+ }
+
+ /* In the worst case, the constant needed by the earliest instruction
+ will end up at the end of the pool. The entire pool must then be
+ accessible from that instruction.
+
+ When adding the first constant, set the pool's highest address to
+ the address of the first out-of-range byte. Adjust this address
+ downwards each time a new constant is added. */
+ if (pool->first == 0)
+ /* For pc-relative lw, addiu and daddiu instructions, the base PC value
+ is the address of the instruction with the lowest two bits clear.
+ The base PC value for ld has the lowest three bits clear. Assume
+ the worst case here. */
+ pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
+ pool->highest_address -= GET_MODE_SIZE (mode);
+ if (first_of_size_p)
+ /* Take into account the worst possible padding due to alignment. */
+ pool->highest_address -= GET_MODE_SIZE (mode) - 1;
+
+ /* Create a new entry. */
+ c = (struct mips16_constant *) xmalloc (sizeof *c);
+ c->value = value;
+ c->mode = mode;
+ c->label = gen_label_rtx ();
+ c->next = *p;
+ *p = c;
- /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
- different optimization. Any time we find a copy of $28 into a
- register, followed by an add of a symbol_ref to that register, we
- convert it to load the value from the constant table instead.
- The copy and add will take six bytes, just as the load and
- constant table entry will take six bytes. However, it is
- possible that the constant table entry will be shared.
+ return c->label;
+}
- This could be a peephole optimization, but I don't know if the
- peephole code can call force_const_mem.
+/* Output constant VALUE after instruction INSN and return the last
+ instruction emitted. MODE is the mode of the constant. */
- Using the same register for the copy of $28 and the add of the
- symbol_ref is actually pretty likely, since the add instruction
- requires the destination and the first addend to be the same
- register. */
-
- if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
+static rtx
+dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
+{
+ switch (GET_MODE_CLASS (mode))
{
-#if 0
- /* Used below in #if 0 area. */
- rtx next;
-#endif
- /* This optimization is only reasonable if the constant table
- entries are only 4 bytes. */
- if (Pmode != SImode)
- return;
-
-#if 0
- /* ??? FIXME. Rewrite for new UNSPEC_RELOC stuff. */
- for (insn = get_insns (); insn != NULL_RTX; insn = next)
- {
- rtx set1, set2;
+ case MODE_INT:
+ {
+ rtx size = GEN_INT (GET_MODE_SIZE (mode));
+ return emit_insn_after (gen_consttable_int (value, size), insn);
+ }
- next = insn;
- do
- {
- next = NEXT_INSN (next);
- }
- while (next != NULL_RTX
- && (GET_CODE (next) == NOTE
- || (GET_CODE (next) == INSN
- && (GET_CODE (PATTERN (next)) == USE
- || GET_CODE (PATTERN (next)) == CLOBBER))));
+ case MODE_FLOAT:
+ return emit_insn_after (gen_consttable_float (value), insn);
- if (next == NULL_RTX)
- break;
+ case MODE_VECTOR_FLOAT:
+ case MODE_VECTOR_INT:
+ {
+ int i;
+ for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
+ insn = dump_constants_1 (GET_MODE_INNER (mode),
+ CONST_VECTOR_ELT (value, i), insn);
+ return insn;
+ }
- if (! INSN_P (insn))
- continue;
-
- if (! INSN_P (next))
- continue;
-
- set1 = PATTERN (insn);
- if (GET_CODE (set1) != SET)
- continue;
- set2 = PATTERN (next);
- if (GET_CODE (set2) != SET)
- continue;
-
- if (GET_CODE (SET_DEST (set1)) == REG
- && GET_CODE (SET_SRC (set1)) == CONST
- && XEXP (SET_SRC (set1), 0) == pic_offset_table_rtx
- && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
- && GET_CODE (SET_SRC (set2)) == PLUS
- && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
- && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
- && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
- {
- rtx sym;
+ default:
+ abort ();
+ }
+}
- /* We've found a case we can change to load from the
- constant table. */
- sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
- if (GET_CODE (sym) != SYMBOL_REF)
- abort ();
- emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
- force_const_mem (Pmode, sym)),
- next);
+/* Dump out the constants in CONSTANTS after INSN. */
- PUT_CODE (insn, NOTE);
- NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
- NOTE_SOURCE_FILE (insn) = 0;
+static void
+dump_constants (struct mips16_constant *constants, rtx insn)
+{
+ struct mips16_constant *c, *next;
+ int align;
- PUT_CODE (next, NOTE);
- NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
- NOTE_SOURCE_FILE (next) = 0;
- }
+ align = 0;
+ for (c = constants; c != NULL; c = next)
+ {
+ /* If necessary, increase the alignment of PC. */
+ if (align < GET_MODE_SIZE (c->mode))
+ {
+ int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
+ insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
}
-#endif
+ align = GET_MODE_SIZE (c->mode);
- return;
+ insn = emit_label_after (c->label, insn);
+ insn = dump_constants_1 (c->mode, c->value, insn);
+
+ next = c->next;
+ free (c);
}
- /* We can safely remove all assignments to SLOT from GPCOPY, and
- replace all assignments from SLOT to GPCOPY with assignments from
- $28. */
- for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
+ emit_barrier_after (insn);
+}
+
+/* Return the length of instruction INSN.
+
+ ??? MIPS16 switch tables go in .text, but we don't define
+ JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
+ compute their lengths correctly. */
+
+static int
+mips16_insn_length (rtx insn)
+{
+ if (GET_CODE (insn) == JUMP_INSN)
{
- rtx set;
+ rtx body = PATTERN (insn);
+ if (GET_CODE (body) == ADDR_VEC)
+ return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
+ if (GET_CODE (body) == ADDR_DIFF_VEC)
+ return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
+ }
+ return get_attr_length (insn);
+}
- if (! INSN_P (insn))
- continue;
+/* Rewrite *X so that constant pool references refer to the constant's
+ label instead. DATA points to the constant pool structure. */
- set = PATTERN (insn);
- if (GET_CODE (set) != SET)
- continue;
+static int
+mips16_rewrite_pool_refs (rtx *x, void *data)
+{
+ struct mips16_constant_pool *pool = data;
+ if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
+ *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
+ get_pool_constant (*x),
+ get_pool_mode (*x)));
+ return 0;
+}
- if (GET_CODE (SET_DEST (set)) == MEM
- && rtx_equal_p (SET_DEST (set), slot)
- && GET_CODE (SET_SRC (set)) == REG
- && REGNO (SET_SRC (set)) == REGNO (gpcopy))
- {
- PUT_CODE (insn, NOTE);
- NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
- NOTE_SOURCE_FILE (insn) = 0;
- }
- else if (GET_CODE (SET_DEST (set)) == REG
- && REGNO (SET_DEST (set)) == REGNO (gpcopy)
- && GET_CODE (SET_SRC (set)) == MEM
- && rtx_equal_p (SET_SRC (set), slot))
+/* Build MIPS16 constant pools. */
+
+static void
+mips16_lay_out_constants (void)
+{
+ struct mips16_constant_pool pool;
+ rtx insn, barrier;
+
+ barrier = 0;
+ memset (&pool, 0, sizeof (pool));
+ for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ {
+ /* Rewrite constant pool references in INSN. */
+ if (INSN_P (insn))
+ for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
+
+ pool.insn_address += mips16_insn_length (insn);
+
+ if (pool.first != NULL)
{
- enum machine_mode mode;
- rtx src;
-
- mode = GET_MODE (SET_DEST (set));
- src = gen_rtx_CONST (mode, pic_offset_table_rtx);
- emit_insn_after (gen_rtx_SET (VOIDmode, SET_DEST (set), src), insn);
- PUT_CODE (insn, NOTE);
- NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
- NOTE_SOURCE_FILE (insn) = 0;
+ /* If there are no natural barriers between the first user of
+ the pool and the highest acceptable address, we'll need to
+ create a new instruction to jump around the constant pool.
+ In the worst case, this instruction will be 4 bytes long.
+
+ If it's too late to do this transformation after INSN,
+ do it immediately before INSN. */
+ if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
+ {
+ rtx label, jump;
+
+ label = gen_label_rtx ();
+
+ jump = emit_jump_insn_before (gen_jump (label), insn);
+ JUMP_LABEL (jump) = label;
+ LABEL_NUSES (label) = 1;
+ barrier = emit_barrier_after (jump);
+
+ emit_label_after (label, barrier);
+ pool.insn_address += 4;
+ }
+
+ /* See whether the constant pool is now out of range of the first
+ user. If so, output the constants after the previous barrier.
+ Note that any instructions between BARRIER and INSN (inclusive)
+ will use negative offsets to refer to the pool. */
+ if (pool.insn_address > pool.highest_address)
+ {
+ dump_constants (pool.first, barrier);
+ pool.first = NULL;
+ barrier = 0;
+ }
+ else if (BARRIER_P (insn))
+ barrier = insn;
}
}
+ dump_constants (pool.first, get_last_insn ());
}
+\f
+/* A temporary variable used by for_each_rtx callbacks, etc. */
+static rtx mips_sim_insn;
+
+/* A structure representing the state of the processor pipeline.
+ Used by the mips_sim_* family of functions. */
+struct mips_sim {
+ /* The maximum number of instructions that can be issued in a cycle.
+ (Caches mips_issue_rate.) */
+ unsigned int issue_rate;
+
+ /* The current simulation time. */
+ unsigned int time;
+
+ /* How many more instructions can be issued in the current cycle. */
+ unsigned int insns_left;
+
+ /* LAST_SET[X].INSN is the last instruction to set register X.
+ LAST_SET[X].TIME is the time at which that instruction was issued.
+ INSN is null if no instruction has yet set register X. */
+ struct {
+ rtx insn;
+ unsigned int time;
+ } last_set[FIRST_PSEUDO_REGISTER];
+
+ /* The pipeline's current DFA state. */
+ state_t dfa_state;
+};
-/* We keep a list of constants we which we have to add to internal
- constant tables in the middle of large functions. */
+/* Reset STATE to the initial simulation state. */
-struct constant
+static void
+mips_sim_reset (struct mips_sim *state)
{
- struct constant *next;
- rtx value;
- rtx label;
- enum machine_mode mode;
-};
+ state->time = 0;
+ state->insns_left = state->issue_rate;
+ memset (&state->last_set, 0, sizeof (state->last_set));
+ state_reset (state->dfa_state);
+}
-/* Add a constant to the list in *PCONSTANTS. */
+/* Initialize STATE before its first use. DFA_STATE points to an
+ allocated but uninitialized DFA state. */
-static rtx
-add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
+static void
+mips_sim_init (struct mips_sim *state, state_t dfa_state)
{
- struct constant *c;
+ state->issue_rate = mips_issue_rate ();
+ state->dfa_state = dfa_state;
+ mips_sim_reset (state);
+}
- for (c = *pconstants; c != NULL; c = c->next)
- if (mode == c->mode && rtx_equal_p (val, c->value))
- return c->label;
+/* Advance STATE by one clock cycle. */
- c = (struct constant *) xmalloc (sizeof *c);
- c->value = val;
- c->mode = mode;
- c->label = gen_label_rtx ();
- c->next = *pconstants;
- *pconstants = c;
- return c->label;
+static void
+mips_sim_next_cycle (struct mips_sim *state)
+{
+ state->time++;
+ state->insns_left = state->issue_rate;
+ state_transition (state->dfa_state, 0);
}
-/* Dump out the constants in CONSTANTS after INSN. */
+/* Advance simulation state STATE until instruction INSN can read
+ register REG. */
static void
-dump_constants (struct constant *constants, rtx insn)
+mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
{
- struct constant *c;
- int align;
+ unsigned int i;
- c = constants;
- align = 0;
- while (c != NULL)
- {
- rtx r;
- struct constant *next;
+ for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
+ if (state->last_set[REGNO (reg) + i].insn != 0)
+ {
+ unsigned int t;
- switch (GET_MODE_SIZE (c->mode))
- {
- case 1:
- align = 0;
- break;
- case 2:
- if (align < 1)
- insn = emit_insn_after (gen_align_2 (), insn);
- align = 1;
- break;
- case 4:
- if (align < 2)
- insn = emit_insn_after (gen_align_4 (), insn);
- align = 2;
- break;
- default:
- if (align < 3)
- insn = emit_insn_after (gen_align_8 (), insn);
- align = 3;
- break;
- }
+ t = state->last_set[REGNO (reg) + i].time;
+ t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
+ while (state->time < t)
+ mips_sim_next_cycle (state);
+ }
+}
- insn = emit_label_after (c->label, insn);
+/* A for_each_rtx callback. If *X is a register, advance simulation state
+ DATA until mips_sim_insn can read the register's value. */
- switch (c->mode)
- {
- case QImode:
- r = gen_consttable_qi (c->value);
- break;
- case HImode:
- r = gen_consttable_hi (c->value);
- break;
- case SImode:
- r = gen_consttable_si (c->value);
- break;
- case SFmode:
- r = gen_consttable_sf (c->value);
- break;
- case DImode:
- r = gen_consttable_di (c->value);
- break;
- case DFmode:
- r = gen_consttable_df (c->value);
- break;
- default:
- abort ();
- }
+static int
+mips_sim_wait_regs_2 (rtx *x, void *data)
+{
+ if (REG_P (*x))
+ mips_sim_wait_reg (data, mips_sim_insn, *x);
+ return 0;
+}
- insn = emit_insn_after (r, insn);
+/* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
- next = c->next;
- free (c);
- c = next;
- }
+static void
+mips_sim_wait_regs_1 (rtx *x, void *data)
+{
+ for_each_rtx (x, mips_sim_wait_regs_2, data);
+}
- emit_barrier_after (insn);
+/* Advance simulation state STATE until all of INSN's register
+ dependencies are satisfied. */
+
+static void
+mips_sim_wait_regs (struct mips_sim *state, rtx insn)
+{
+ mips_sim_insn = insn;
+ note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
}
-/* Find the symbol in an address expression. */
+/* Advance simulation state STATE until the units required by
+ instruction INSN are available. */
-static rtx
-mips_find_symbol (rtx addr)
+static void
+mips_sim_wait_units (struct mips_sim *state, rtx insn)
{
- if (GET_CODE (addr) == MEM)
- addr = XEXP (addr, 0);
- while (GET_CODE (addr) == CONST)
- addr = XEXP (addr, 0);
- if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
- return addr;
- if (GET_CODE (addr) == PLUS)
- {
- rtx l1, l2;
+ state_t tmp_state;
- l1 = mips_find_symbol (XEXP (addr, 0));
- l2 = mips_find_symbol (XEXP (addr, 1));
- if (l1 != NULL_RTX && l2 == NULL_RTX)
- return l1;
- else if (l1 == NULL_RTX && l2 != NULL_RTX)
- return l2;
- }
- return NULL_RTX;
+ tmp_state = alloca (state_size ());
+ while (state->insns_left == 0
+ || (memcpy (tmp_state, state->dfa_state, state_size ()),
+ state_transition (tmp_state, insn) >= 0))
+ mips_sim_next_cycle (state);
}
-/* In mips16 mode, we need to look through the function to check for
- PC relative loads that are out of range. */
+/* Advance simulation state STATE until INSN is ready to issue. */
static void
-mips16_lay_out_constants (void)
+mips_sim_wait_insn (struct mips_sim *state, rtx insn)
{
- int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
- rtx first, insn;
- struct constant *constants;
+ mips_sim_wait_regs (state, insn);
+ mips_sim_wait_units (state, insn);
+}
- first = get_insns ();
+/* mips_sim_insn has just set X. Update the LAST_SET array
+ in simulation state DATA. */
- /* Scan the function looking for PC relative loads which may be out
- of range. All such loads will either be from the constant table,
- or be getting the address of a constant string. If the size of
- the function plus the size of the constant table is less than
- 0x8000, then all loads are in range. */
+static void
+mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
+{
+ struct mips_sim *state;
+ unsigned int i;
- insns_len = 0;
- for (insn = first; insn; insn = NEXT_INSN (insn))
- {
- insns_len += get_attr_length (insn);
+ state = data;
+ if (REG_P (x))
+ for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
+ {
+ state->last_set[REGNO (x) + i].insn = mips_sim_insn;
+ state->last_set[REGNO (x) + i].time = state->time;
+ }
+}
- /* ??? We put switch tables in .text, but we don't define
- JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
- compute their lengths correctly. */
- if (GET_CODE (insn) == JUMP_INSN)
- {
- rtx body;
+/* Issue instruction INSN in scheduler state STATE. Assume that INSN
+ can issue immediately (i.e., that mips_sim_wait_insn has already
+ been called). */
- body = PATTERN (insn);
- if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
- insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
- * GET_MODE_SIZE (GET_MODE (body)));
- insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
- }
- }
+static void
+mips_sim_issue_insn (struct mips_sim *state, rtx insn)
+{
+ state_transition (state->dfa_state, insn);
+ state->insns_left--;
- /* Store the original value of insns_len in cfun->machine, so
- that simple_memory_operand can look at it. */
- cfun->machine->insns_len = insns_len;
+ mips_sim_insn = insn;
+ note_stores (PATTERN (insn), mips_sim_record_set, state);
+}
- pool_size = get_pool_size ();
- if (insns_len + pool_size + mips_string_length < 0x8000)
- return;
+/* Simulate issuing a NOP in state STATE. */
- /* Loop over the insns and figure out what the maximum internal pool
- size could be. */
- max_internal_pool_size = 0;
- for (insn = first; insn; insn = NEXT_INSN (insn))
+static void
+mips_sim_issue_nop (struct mips_sim *state)
+{
+ if (state->insns_left == 0)
+ mips_sim_next_cycle (state);
+ state->insns_left--;
+}
+
+/* Update simulation state STATE so that it's ready to accept the instruction
+ after INSN. INSN should be part of the main rtl chain, not a member of a
+ SEQUENCE. */
+
+static void
+mips_sim_finish_insn (struct mips_sim *state, rtx insn)
+{
+ /* If INSN is a jump with an implicit delay slot, simulate a nop. */
+ if (JUMP_P (insn))
+ mips_sim_issue_nop (state);
+
+ switch (GET_CODE (SEQ_BEGIN (insn)))
{
- if (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SET)
+ case CODE_LABEL:
+ case CALL_INSN:
+ /* We can't predict the processor state after a call or label. */
+ mips_sim_reset (state);
+ break;
+
+ case JUMP_INSN:
+ /* The delay slots of branch likely instructions are only executed
+ when the branch is taken. Therefore, if the caller has simulated
+ the delay slot instruction, STATE does not really reflect the state
+ of the pipeline for the instruction after the delay slot. Also,
+ branch likely instructions tend to incur a penalty when not taken,
+ so there will probably be an extra delay between the branch and
+ the instruction after the delay slot. */
+ if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
+ mips_sim_reset (state);
+ break;
+
+ default:
+ break;
+ }
+}
+\f
+/* The VR4130 pipeline issues aligned pairs of instructions together,
+ but it stalls the second instruction if it depends on the first.
+ In order to cut down the amount of logic required, this dependence
+ check is not based on a full instruction decode. Instead, any non-SPECIAL
+ instruction is assumed to modify the register specified by bits 20-16
+ (which is usually the "rt" field).
+
+ In beq, beql, bne and bnel instructions, the rt field is actually an
+ input, so we can end up with a false dependence between the branch
+ and its delay slot. If this situation occurs in instruction INSN,
+ try to avoid it by swapping rs and rt. */
+
+static void
+vr4130_avoid_branch_rt_conflict (rtx insn)
+{
+ rtx first, second;
+
+ first = SEQ_BEGIN (insn);
+ second = SEQ_END (insn);
+ if (GET_CODE (first) == JUMP_INSN
+ && GET_CODE (second) == INSN
+ && GET_CODE (PATTERN (first)) == SET
+ && GET_CODE (SET_DEST (PATTERN (first))) == PC
+ && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
+ {
+ /* Check for the right kind of condition. */
+ rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
+ if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
+ && REG_P (XEXP (cond, 0))
+ && REG_P (XEXP (cond, 1))
+ && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
+ && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
{
- rtx src;
-
- src = mips_find_symbol (SET_SRC (PATTERN (insn)));
- if (src == NULL_RTX)
- continue;
- if (CONSTANT_POOL_ADDRESS_P (src))
- max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
- else if (SYMBOL_REF_FLAG (src))
- max_internal_pool_size += GET_MODE_SIZE (Pmode);
+ /* SECOND mentions the rt register but not the rs register. */
+ rtx tmp = XEXP (cond, 0);
+ XEXP (cond, 0) = XEXP (cond, 1);
+ XEXP (cond, 1) = tmp;
}
}
+}
- constants = NULL;
- addr = 0;
- first_constant_ref = -1;
+/* Implement -mvr4130-align. Go through each basic block and simulate the
+ processor pipeline. If we find that a pair of instructions could execute
+ in parallel, and the first of those instruction is not 8-byte aligned,
+ insert a nop to make it aligned. */
- for (insn = first; insn; insn = NEXT_INSN (insn))
- {
- if (GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SET)
- {
- rtx val, src;
- enum machine_mode mode = VOIDmode;
+static void
+vr4130_align_insns (void)
+{
+ struct mips_sim state;
+ rtx insn, subinsn, last, last2, next;
+ bool aligned_p;
- val = NULL_RTX;
- src = mips_find_symbol (SET_SRC (PATTERN (insn)));
- if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
- {
- /* ??? This is very conservative, which means that we
- will generate too many copies of the constant table.
- The only solution would seem to be some form of
- relaxing. */
- if (((insns_len - addr)
- + max_internal_pool_size
- + get_pool_offset (src))
- >= 0x8000)
- {
- val = get_pool_constant (src);
- mode = get_pool_mode (src);
- }
- max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
- }
- else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
- {
- /* Including all of mips_string_length is conservative,
- and so is including all of max_internal_pool_size. */
- if (((insns_len - addr)
- + max_internal_pool_size
- + pool_size
- + mips_string_length)
- >= 0x8000)
- {
- val = src;
- mode = Pmode;
- }
- max_internal_pool_size -= Pmode;
- }
+ dfa_start ();
- if (val != NULL_RTX)
- {
- rtx lab, newsrc;
-
- /* This PC relative load is out of range. ??? In the
- case of a string constant, we are only guessing that
- it is range, since we don't know the offset of a
- particular string constant. */
-
- lab = add_constant (&constants, val, mode);
- newsrc = gen_rtx (MEM, mode,
- gen_rtx (LABEL_REF, VOIDmode, lab));
- RTX_UNCHANGING_P (newsrc) = 1;
- PATTERN (insn) = gen_rtx (SET, VOIDmode,
- SET_DEST (PATTERN (insn)),
- newsrc);
- INSN_CODE (insn) = -1;
-
- if (first_constant_ref < 0)
- first_constant_ref = addr;
- }
- }
+ /* LAST is the last instruction before INSN to have a nonzero length.
+ LAST2 is the last such instruction before LAST. */
+ last = 0;
+ last2 = 0;
- addr += get_attr_length (insn);
+ /* ALIGNED_P is true if INSN is known to be at an aligned address. */
+ aligned_p = true;
- /* ??? We put switch tables in .text, but we don't define
- JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
- compute their lengths correctly. */
- if (GET_CODE (insn) == JUMP_INSN)
- {
- rtx body;
+ mips_sim_init (&state, alloca (state_size ()));
+ for (insn = get_insns (); insn != 0; insn = next)
+ {
+ unsigned int length;
- body = PATTERN (insn);
- if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
- addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
- * GET_MODE_SIZE (GET_MODE (body)));
- addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
- }
+ next = NEXT_INSN (insn);
- if (GET_CODE (insn) == BARRIER)
- {
- /* Output any constants we have accumulated. Note that we
- don't need to change ADDR, since its only use is
- subtraction from INSNS_LEN, and both would be changed by
- the same amount.
- ??? If the instructions up to the next barrier reuse a
- constant, it would often be better to continue
- accumulating. */
- if (constants != NULL)
- dump_constants (constants, insn);
- constants = NULL;
- first_constant_ref = -1;
- }
+ /* See the comment above vr4130_avoid_branch_rt_conflict for details.
+ This isn't really related to the alignment pass, but we do it on
+ the fly to avoid a separate instruction walk. */
+ vr4130_avoid_branch_rt_conflict (insn);
- if (constants != NULL
- && (NEXT_INSN (insn) == NULL
- || (first_constant_ref >= 0
- && (((addr - first_constant_ref)
- + 2 /* for alignment */
- + 2 /* for a short jump insn */
- + pool_size)
- >= 0x8000))))
+ if (USEFUL_INSN_P (insn))
+ FOR_EACH_SUBINSN (subinsn, insn)
+ {
+ mips_sim_wait_insn (&state, subinsn);
+
+ /* If we want this instruction to issue in parallel with the
+ previous one, make sure that the previous instruction is
+ aligned. There are several reasons why this isn't worthwhile
+ when the second instruction is a call:
+
+ - Calls are less likely to be performance critical,
+ - There's a good chance that the delay slot can execute
+ in parallel with the call.
+ - The return address would then be unaligned.
+
+ In general, if we're going to insert a nop between instructions
+ X and Y, it's better to insert it immediately after X. That
+ way, if the nop makes Y aligned, it will also align any labels
+ between X and Y. */
+ if (state.insns_left != state.issue_rate
+ && GET_CODE (subinsn) != CALL_INSN)
+ {
+ if (subinsn == SEQ_BEGIN (insn) && aligned_p)
+ {
+ /* SUBINSN is the first instruction in INSN and INSN is
+ aligned. We want to align the previous instruction
+ instead, so insert a nop between LAST2 and LAST.
+
+ Note that LAST could be either a single instruction
+ or a branch with a delay slot. In the latter case,
+ LAST, like INSN, is already aligned, but the delay
+ slot must have some extra delay that stops it from
+ issuing at the same time as the branch. We therefore
+ insert a nop before the branch in order to align its
+ delay slot. */
+ emit_insn_after (gen_nop (), last2);
+ aligned_p = false;
+ }
+ else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
+ {
+ /* SUBINSN is the delay slot of INSN, but INSN is
+ currently unaligned. Insert a nop between
+ LAST and INSN to align it. */
+ emit_insn_after (gen_nop (), last);
+ aligned_p = true;
+ }
+ }
+ mips_sim_issue_insn (&state, subinsn);
+ }
+ mips_sim_finish_insn (&state, insn);
+
+ /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
+ length = get_attr_length (insn);
+ if (length > 0)
{
- /* If we haven't had a barrier within 0x8000 bytes of a
- constant reference or we are at the end of the function,
- emit a barrier now. */
-
- rtx label, jump, barrier;
-
- label = gen_label_rtx ();
- jump = emit_jump_insn_after (gen_jump (label), insn);
- JUMP_LABEL (jump) = label;
- LABEL_NUSES (label) = 1;
- barrier = emit_barrier_after (jump);
- emit_label_after (label, barrier);
- first_constant_ref = -1;
+ /* If the instruction is an asm statement or multi-instruction
+ mips.md patern, the length is only an estimate. Insert an
+ 8 byte alignment after it so that the following instructions
+ can be handled correctly. */
+ if (GET_CODE (SEQ_BEGIN (insn)) == INSN
+ && (recog_memoized (insn) < 0 || length >= 8))
+ {
+ next = emit_insn_after (gen_align (GEN_INT (3)), insn);
+ next = NEXT_INSN (next);
+ mips_sim_next_cycle (&state);
+ aligned_p = true;
+ }
+ else if (length & 4)
+ aligned_p = !aligned_p;
+ last2 = last;
+ last = insn;
}
- }
- /* ??? If we output all references to a constant in internal
- constants table, we don't need to output the constant in the real
- constant table, but we have no way to prevent that. */
+ /* See whether INSN is an aligned label. */
+ if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
+ aligned_p = true;
+ }
+ dfa_finish ();
}
-
-
+\f
/* Subroutine of mips_reorg. If there is a hazard between INSN
and a previous instruction, avoid it by inserting nops after
instruction AFTER.
rtx insn, last_insn, lo_reg, delayed_reg;
int hilo_delay, i;
+ /* Force all instructions to be split into their final form. */
+ split_all_insns_noflow ();
+
/* Recalculate instruction lengths without taking nops into account. */
cfun->machine->ignore_hazard_length_p = true;
shorten_branches (get_insns ());
- /* The profiler code uses assembler macros. */
- cfun->machine->all_noreorder_p = !current_function_profile;
+ /* The profiler code uses assembler macros. -mfix-vr4120 relies on
+ assembler nop insertion. */
+ cfun->machine->all_noreorder_p = (!current_function_profile
+ && !TARGET_FIX_VR4120);
last_insn = 0;
hilo_delay = 2;
mips_reorg (void)
{
if (TARGET_MIPS16)
- {
- if (optimize)
- mips16_optimize_gp ();
- mips16_lay_out_constants ();
- }
+ mips16_lay_out_constants ();
else if (TARGET_EXPLICIT_RELOCS)
{
if (mips_flag_delayed_branch)
- dbr_schedule (get_insns (), rtl_dump_file);
+ dbr_schedule (get_insns (), dump_file);
mips_avoid_hazards ();
+ if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
+ vr4130_align_insns ();
}
}
-/* We need to use a special set of functions to handle hard floating
- point code in mips16 mode. Also, allow for --enable-gofast. */
+/* This function does three things:
+
+ - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
+ - Register the mips16 hardware floating point stubs.
+ - Register the gofast functions if selected using --enable-gofast. */
#include "config/gofast.h"
static void
mips_init_libfuncs (void)
{
+ if (TARGET_FIX_VR4120)
+ {
+ set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
+ set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
+ }
+
if (TARGET_MIPS16 && mips16_hard_float)
{
set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
- set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fixsfsi");
+ set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
if (TARGET_DOUBLE_FLOAT)
set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
- set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fixdfsi");
+ set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
}
}
else
return 6;
}
- } /* from == HI_REG, etc. */
+ } /* from == HI_REG, etc. */
else if (from == ST_REGS && GR_REG_CLASS_P (to))
return 4;
else if (COP_REG_CLASS_P (from))
return 5;
} /* COP_REG_CLASS_P (from) */
- /* fallthru */
+ /* Fall through. */
return 12;
}
.set macro
.set reorder
- When generating non-embedded PIC, instead of:
+ When generating PIC, instead of:
j target
/* Output delay slot instruction. */
rtx insn = final_sequence;
final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
- optimize, 0, 1);
+ optimize, 0, 1, NULL);
INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
}
else
/* Output delay slot instruction. */
rtx insn = final_sequence;
final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
- optimize, 0, 1);
+ optimize, 0, 1, NULL);
INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
}
else
return 0;
}
\f
-/* Used to output div or ddiv instruction DIVISION, which has the
- operands given by OPERANDS. If we need a divide-by-zero check,
- output the instruction and return an asm string that traps if
- operand 2 is zero. Otherwise just return DIVISION itself. */
+/* Used to output div or ddiv instruction DIVISION, which has the operands
+ given by OPERANDS. Add in a divide-by-zero check if needed.
+
+ When working around R4000 and R4400 errata, we need to make sure that
+ the division is not immediately followed by a shift[1][2]. We also
+ need to stop the division from being put into a branch delay slot[3].
+ The easiest way to avoid both problems is to add a nop after the
+ division. When a divide-by-zero check is needed, this nop can be
+ used to fill the branch delay slot.
+
+ [1] If a double-word or a variable shift executes immediately
+ after starting an integer division, the shift may give an
+ incorrect result. See quotations of errata #16 and #28 from
+ "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
+ in mips.md for details.
+
+ [2] A similar bug to [1] exists for all revisions of the
+ R4000 and the R4400 when run in an MC configuration.
+ From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
+
+ "19. In this following sequence:
+
+ ddiv (or ddivu or div or divu)
+ dsll32 (or dsrl32, dsra32)
+
+ if an MPT stall occurs, while the divide is slipping the cpu
+ pipeline, then the following double shift would end up with an
+ incorrect result.
+
+ Workaround: The compiler needs to avoid generating any
+ sequence with divide followed by extended double shift."
+
+ This erratum is also present in "MIPS R4400MC Errata, Processor
+ Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
+ & 3.0" as errata #10 and #4, respectively.
+
+ [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
+ (also valid for MIPS R4000MC processors):
+
+ "52. R4000SC: This bug does not apply for the R4000PC.
+
+ There are two flavors of this bug:
+
+ 1) If the instruction just after divide takes an RF exception
+ (tlb-refill, tlb-invalid) and gets an instruction cache
+ miss (both primary and secondary) and the line which is
+ currently in secondary cache at this index had the first
+ data word, where the bits 5..2 are set, then R4000 would
+ get a wrong result for the div.
+
+ ##1
+ nop
+ div r8, r9
+ ------------------- # end-of page. -tlb-refill
+ nop
+ ##2
+ nop
+ div r8, r9
+ ------------------- # end-of page. -tlb-invalid
+ nop
+
+ 2) If the divide is in the taken branch delay slot, where the
+ target takes RF exception and gets an I-cache miss for the
+ exception vector or where I-cache miss occurs for the
+ target address, under the above mentioned scenarios, the
+ div would get wrong results.
+
+ ##1
+ j r2 # to next page mapped or unmapped
+ div r8,r9 # this bug would be there as long
+ # as there is an ICache miss and
+ nop # the "data pattern" is present
+
+ ##2
+ beq r0, r0, NextPage # to Next page
+ div r8,r9
+ nop
+
+ This bug is present for div, divu, ddiv, and ddivu
+ instructions.
+
+ Workaround: For item 1), OS could make sure that the next page
+ after the divide instruction is also mapped. For item 2), the
+ compiler could make sure that the divide instruction is not in
+ the branch delay slot."
+
+ These processors have PRId values of 0x00004220 and 0x00004300 for
+ the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
const char *
mips_output_division (const char *division, rtx *operands)
{
+ const char *s;
+
+ s = division;
+ if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
+ {
+ output_asm_insn (s, operands);
+ s = "nop";
+ }
if (TARGET_CHECK_ZERO_DIV)
{
- output_asm_insn (division, operands);
-
if (TARGET_MIPS16)
- return "bnez\t%2,1f\n\tbreak\t7\n1:";
+ {
+ output_asm_insn (s, operands);
+ s = "bnez\t%2,1f\n\tbreak\t7\n1:";
+ }
else
- return "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
+ {
+ output_asm_insn ("%(bne\t%2,%.,1f", operands);
+ output_asm_insn (s, operands);
+ s = "break\t7%)\n1:";
+ }
}
- return division;
+ return s;
}
\f
/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
return 0;
}
\f
-/* Adjust the cost of INSN based on the relationship between INSN that
- is dependent on DEP_INSN through the dependence LINK. The default
- is to make no adjustment to COST.
-
- On the MIPS, ignore the cost of anti- and output-dependencies. */
-static int
-mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
- rtx dep ATTRIBUTE_UNUSED, int cost)
-{
- if (REG_NOTE_KIND (link) != 0)
- return 0; /* Anti or output dependence. */
- return cost;
-}
-
/* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
by UNITS_PER_FPREG. All other registers are word sized. */
return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
}
-/* Implement RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
+/* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
all BLKmode objects are returned in memory. Under the new (N32 and
64-bit MIPS ABIs) small structures are returned in a register.
Objects with varying size must still be returned in memory, of
course. */
-int
-mips_return_in_memory (tree type)
+static bool
+mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
{
- if (mips_abi == ABI_32 || mips_abi == ABI_O64)
+ if (TARGET_OLDABI)
return (TYPE_MODE (type) == BLKmode);
else
return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
|| (int_size_in_bytes (type) == -1));
}
+static bool
+mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
+{
+ return !TARGET_OLDABI;
+}
+\f
+/* Return true if INSN is a multiply-add or multiply-subtract
+ instruction and PREV assigns to the accumulator operand. */
+
+bool
+mips_linked_madd_p (rtx prev, rtx insn)
+{
+ rtx x;
+
+ x = single_set (insn);
+ if (x == 0)
+ return false;
+
+ x = SET_SRC (x);
+
+ if (GET_CODE (x) == PLUS
+ && GET_CODE (XEXP (x, 0)) == MULT
+ && reg_set_p (XEXP (x, 1), prev))
+ return true;
+
+ if (GET_CODE (x) == MINUS
+ && GET_CODE (XEXP (x, 1)) == MULT
+ && reg_set_p (XEXP (x, 0), prev))
+ return true;
+
+ return false;
+}
+\f
+/* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
+ that may clobber hi or lo. */
+
+static rtx mips_macc_chains_last_hilo;
+
+/* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
+ been scheduled, updating mips_macc_chains_last_hilo appropriately. */
+
+static void
+mips_macc_chains_record (rtx insn)
+{
+ if (get_attr_may_clobber_hilo (insn))
+ mips_macc_chains_last_hilo = insn;
+}
+
+/* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
+ has NREADY elements, looking for a multiply-add or multiply-subtract
+ instruction that is cumulative with mips_macc_chains_last_hilo.
+ If there is one, promote it ahead of anything else that might
+ clobber hi or lo. */
+
+static void
+mips_macc_chains_reorder (rtx *ready, int nready)
+{
+ int i, j;
+
+ if (mips_macc_chains_last_hilo != 0)
+ for (i = nready - 1; i >= 0; i--)
+ if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
+ {
+ for (j = nready - 1; j > i; j--)
+ if (recog_memoized (ready[j]) >= 0
+ && get_attr_may_clobber_hilo (ready[j]))
+ {
+ mips_promote_ready (ready, i, j);
+ break;
+ }
+ break;
+ }
+}
+\f
+/* The last instruction to be scheduled. */
+
+static rtx vr4130_last_insn;
+
+/* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
+ points to an rtx that is initially an instruction. Nullify the rtx
+ if the instruction uses the value of register X. */
+
+static void
+vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
+{
+ rtx *insn_ptr = data;
+ if (REG_P (x)
+ && *insn_ptr != 0
+ && reg_referenced_p (x, PATTERN (*insn_ptr)))
+ *insn_ptr = 0;
+}
+
+/* Return true if there is true register dependence between vr4130_last_insn
+ and INSN. */
+
+static bool
+vr4130_true_reg_dependence_p (rtx insn)
+{
+ note_stores (PATTERN (vr4130_last_insn),
+ vr4130_true_reg_dependence_p_1, &insn);
+ return insn == 0;
+}
+
+/* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
+ the ready queue and that INSN2 is the instruction after it, return
+ true if it is worth promoting INSN2 ahead of INSN1. Look for cases
+ in which INSN1 and INSN2 can probably issue in parallel, but for
+ which (INSN2, INSN1) should be less sensitive to instruction
+ alignment than (INSN1, INSN2). See 4130.md for more details. */
+
+static bool
+vr4130_swap_insns_p (rtx insn1, rtx insn2)
+{
+ rtx dep;
+
+ /* Check for the following case:
+
+ 1) there is some other instruction X with an anti dependence on INSN1;
+ 2) X has a higher priority than INSN2; and
+ 3) X is an arithmetic instruction (and thus has no unit restrictions).
+
+ If INSN1 is the last instruction blocking X, it would better to
+ choose (INSN1, X) over (INSN2, INSN1). */
+ for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
+ if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
+ && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
+ && recog_memoized (XEXP (dep, 0)) >= 0
+ && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
+ return false;
+
+ if (vr4130_last_insn != 0
+ && recog_memoized (insn1) >= 0
+ && recog_memoized (insn2) >= 0)
+ {
+ /* See whether INSN1 and INSN2 use different execution units,
+ or if they are both ALU-type instructions. If so, they can
+ probably execute in parallel. */
+ enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
+ enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
+ if (class1 != class2 || class1 == VR4130_CLASS_ALU)
+ {
+ /* If only one of the instructions has a dependence on
+ vr4130_last_insn, prefer to schedule the other one first. */
+ bool dep1 = vr4130_true_reg_dependence_p (insn1);
+ bool dep2 = vr4130_true_reg_dependence_p (insn2);
+ if (dep1 != dep2)
+ return dep1;
+
+ /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
+ is not an ALU-type instruction and if INSN1 uses the same
+ execution unit. (Note that if this condition holds, we already
+ know that INSN2 uses a different execution unit.) */
+ if (class1 != VR4130_CLASS_ALU
+ && recog_memoized (vr4130_last_insn) >= 0
+ && class1 == get_attr_vr4130_class (vr4130_last_insn))
+ return true;
+ }
+ }
+ return false;
+}
+
+/* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
+ queue with at least two instructions. Swap the first two if
+ vr4130_swap_insns_p says that it could be worthwhile. */
+
+static void
+vr4130_reorder (rtx *ready, int nready)
+{
+ if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
+ mips_promote_ready (ready, nready - 2, nready - 1);
+}
+\f
+/* Remove the instruction at index LOWER from ready queue READY and
+ reinsert it in front of the instruction at index HIGHER. LOWER must
+ be <= HIGHER. */
+
+static void
+mips_promote_ready (rtx *ready, int lower, int higher)
+{
+ rtx new_head;
+ int i;
+
+ new_head = ready[lower];
+ for (i = lower; i < higher; i++)
+ ready[i] = ready[i + 1];
+ ready[i] = new_head;
+}
+
+/* Implement TARGET_SCHED_REORDER. */
+
+static int
+mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
+ rtx *ready, int *nreadyp, int cycle)
+{
+ if (!reload_completed && TUNE_MACC_CHAINS)
+ {
+ if (cycle == 0)
+ mips_macc_chains_last_hilo = 0;
+ if (*nreadyp > 0)
+ mips_macc_chains_reorder (ready, *nreadyp);
+ }
+ if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
+ {
+ if (cycle == 0)
+ vr4130_last_insn = 0;
+ if (*nreadyp > 1)
+ vr4130_reorder (ready, *nreadyp);
+ }
+ return mips_issue_rate ();
+}
+
+/* Implement TARGET_SCHED_VARIABLE_ISSUE. */
+
+static int
+mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
+ rtx insn, int more)
+{
+ switch (GET_CODE (PATTERN (insn)))
+ {
+ case USE:
+ case CLOBBER:
+ /* Don't count USEs and CLOBBERs against the issue rate. */
+ break;
+
+ default:
+ more--;
+ if (!reload_completed && TUNE_MACC_CHAINS)
+ mips_macc_chains_record (insn);
+ vr4130_last_insn = insn;
+ break;
+ }
+ return more;
+}
+\f
+/* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
+ dependencies have no cost. */
+
+static int
+mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
+ rtx dep ATTRIBUTE_UNUSED, int cost)
+{
+ if (REG_NOTE_KIND (link) != 0)
+ return 0;
+ return cost;
+}
+
+/* Return the number of instructions that can be issued per cycle. */
+
static int
mips_issue_rate (void)
{
switch (mips_tune)
{
+ case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
return 2;
+ case PROCESSOR_SB1:
+ /* This is actually 4, but we get better performance if we claim 3.
+ This is partly because of unwanted speculative code motion with the
+ larger number, and partly because in most common cases we can't
+ reach the theoretical max of 4. */
+ return 3;
+
default:
return 1;
}
{
switch (mips_tune)
{
+ case PROCESSOR_R3000:
+ case PROCESSOR_R4130:
case PROCESSOR_R5400:
case PROCESSOR_R5500:
case PROCESSOR_R7000:
case PROCESSOR_R9000:
+ case PROCESSOR_SB1:
case PROCESSOR_SR71000:
return true;
}
}
+/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
+ be as wide as the scheduling freedom in the DFA. */
+
+static int
+mips_multipass_dfa_lookahead (void)
+{
+ /* Can schedule up to 4 of the 6 function units in any one cycle. */
+ if (mips_tune == PROCESSOR_SB1)
+ return 4;
+
+ return 0;
+}
+\f
const char *
mips_emit_prefetch (rtx *operands)
int indexed = GET_CODE (operands[3]) == REG;
int code;
char buffer[30];
-
+
if (locality <= 0)
code = (write ? 5 : 4); /* store_streamed / load_streamed. */
else if (locality <= 2)
/* In addition to emitting a .align directive, record the maximum
alignment requested for the current section. */
-struct GTY (()) irix_section_align_entry
+struct irix_section_align_entry GTY (())
{
const char *name;
unsigned int log;
OSDN Git Service
