1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
- 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
+ 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
Brendan Eich, brendan@microunity.com.
This file is part of GCC.
static bool mips_handle_option (size_t, const char *, int);
static struct machine_function *mips_init_machine_status (void);
static void print_operand_reloc (FILE *, rtx, const char **);
-#if TARGET_IRIX
-static void irix_output_external_libcall (rtx);
-#endif
static void mips_file_start (void);
-static void mips_file_end (void);
static bool mips_rewrite_small_data_p (rtx);
static int mips_small_data_pattern_1 (rtx *, void *);
static int mips_rewrite_small_data_1 (rtx *, void *);
tree, bool);
static bool mips_valid_pointer_mode (enum machine_mode);
static bool mips_vector_mode_supported_p (enum machine_mode);
-static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
+static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void mips_init_builtins (void);
/* Next label # for each statement for Silicon Graphics IRIS systems. */
int sym_lineno = 0;
-/* Linked list of all externals that are to be emitted when optimizing
- for the global pointer if they haven't been declared by the end of
- the program with an appropriate .comm or initialization. */
-
-struct extern_list GTY (())
-{
- struct extern_list *next; /* next external */
- const char *name; /* name of the external */
- int size; /* size in bytes */
-};
-
-static GTY (()) struct extern_list *extern_head = 0;
-
/* Name of the file containing the current function. */
const char *current_function_file = "";
/* MIPS32 Release 2 */
{ "m4k", PROCESSOR_M4K, 33 },
- { "24k", PROCESSOR_24K, 33 },
- { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
- { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
- { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
+ { "4kec", PROCESSOR_4KC, 33 },
+ { "4kem", PROCESSOR_4KC, 33 },
+ { "4kep", PROCESSOR_4KP, 33 },
+ { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
+ { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
+ { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
+ { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
+ { "24kef", PROCESSOR_24KF, 33 },
+ { "24kex", PROCESSOR_24KX, 33 },
+ { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
+ { "34kf", PROCESSOR_24KF, 33 },
+ { "34kx", PROCESSOR_24KX, 33 },
/* MIPS64 */
{ "5kc", PROCESSOR_5KC, 64 },
{ "5kf", PROCESSOR_5KF, 64 },
{ "20kc", PROCESSOR_20KC, 64 },
{ "sb1", PROCESSOR_SB1, 64 },
+ { "sb1a", PROCESSOR_SB1A, 64 },
{ "sr71000", PROCESSOR_SR71000, 64 },
/* End marker */
COSTS_N_INSNS (256), /* fp_div_sf */ \
COSTS_N_INSNS (256) /* fp_div_df */
+static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
+ {
+ COSTS_N_INSNS (1), /* fp_add */
+ COSTS_N_INSNS (1), /* fp_mult_sf */
+ COSTS_N_INSNS (1), /* fp_mult_df */
+ COSTS_N_INSNS (1), /* fp_div_sf */
+ COSTS_N_INSNS (1), /* fp_div_df */
+ COSTS_N_INSNS (1), /* int_mult_si */
+ COSTS_N_INSNS (1), /* int_mult_di */
+ COSTS_N_INSNS (1), /* int_div_si */
+ COSTS_N_INSNS (1), /* int_div_di */
+ 2, /* branch_cost */
+ 4 /* memory_latency */
+ };
+
static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
{
{ /* R3000 */
{ /* 20KC */
DEFAULT_COSTS
},
- { /* 24k */
+ { /* 24KC */
+ SOFT_FP_COSTS,
+ COSTS_N_INSNS (5), /* int_mult_si */
+ COSTS_N_INSNS (5), /* int_mult_di */
+ COSTS_N_INSNS (41), /* int_div_si */
+ COSTS_N_INSNS (41), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* 24KF */
COSTS_N_INSNS (8), /* fp_add */
COSTS_N_INSNS (8), /* fp_mult_sf */
COSTS_N_INSNS (10), /* fp_mult_df */
1, /* branch_cost */
4 /* memory_latency */
},
- { /* 24kx */
+ { /* 24KX */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (5), /* fp_mult_df */
4 /* memory_latency */
},
{ /* SB1 */
+ /* These costs are the same as the SB-1A below. */
+ COSTS_N_INSNS (4), /* fp_add */
+ COSTS_N_INSNS (4), /* fp_mult_sf */
+ COSTS_N_INSNS (4), /* fp_mult_df */
+ COSTS_N_INSNS (24), /* fp_div_sf */
+ COSTS_N_INSNS (32), /* fp_div_df */
+ COSTS_N_INSNS (3), /* int_mult_si */
+ COSTS_N_INSNS (4), /* int_mult_di */
+ COSTS_N_INSNS (36), /* int_div_si */
+ COSTS_N_INSNS (68), /* int_div_di */
+ 1, /* branch_cost */
+ 4 /* memory_latency */
+ },
+ { /* SB1-A */
+ /* These costs are the same as the SB-1 above. */
COSTS_N_INSNS (4), /* fp_add */
COSTS_N_INSNS (4), /* fp_mult_sf */
COSTS_N_INSNS (4), /* fp_mult_df */
#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
#undef TARGET_ASM_FILE_START
-#undef TARGET_ASM_FILE_END
#define TARGET_ASM_FILE_START mips_file_start
-#define TARGET_ASM_FILE_END mips_file_end
#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
static enum mips_symbol_type
mips_classify_symbol (rtx x)
{
+ tree decl;
+
if (GET_CODE (x) == LABEL_REF)
{
if (TARGET_MIPS16)
return SYMBOL_SMALL_DATA;
}
- if (SYMBOL_REF_SMALL_P (x))
+ /* Do not use small-data accesses for weak symbols; they may end up
+ being zero. */
+ if (SYMBOL_REF_SMALL_P (x)
+ && !SYMBOL_REF_WEAK (x))
return SYMBOL_SMALL_DATA;
if (TARGET_ABICALLS)
{
- if (SYMBOL_REF_DECL (x) == 0)
+ decl = SYMBOL_REF_DECL (x);
+ if (decl == 0)
{
if (!SYMBOL_REF_LOCAL_P (x))
return SYMBOL_GOT_GLOBAL;
In the third case we have more freedom since both forms of
access will work for any kind of symbol. However, there seems
- little point in doing things differently. */
- if (DECL_P (SYMBOL_REF_DECL (x))
- && TREE_PUBLIC (SYMBOL_REF_DECL (x))
- && !(TARGET_ABSOLUTE_ABICALLS
- && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
+ little point in doing things differently.
+
+ Note that weakref symbols are not TREE_PUBLIC, but their
+ targets are global or weak symbols. Relocations in the
+ object file will be against the target symbol, so it's
+ that symbol's binding that matters here. */
+ if (DECL_P (decl)
+ && (TREE_PUBLIC (decl) || DECL_WEAK (decl))
+ && !(TARGET_ABSOLUTE_ABICALLS && targetm.binds_local_p (decl)))
return SYMBOL_GOT_GLOBAL;
}
*offset = 0;
if (GET_CODE (x) == CONST)
- x = XEXP (x, 0);
-
- if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
{
- *offset += INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
+ if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ {
+ *offset += INTVAL (XEXP (x, 1));
+ x = XEXP (x, 0);
+ }
}
*base = x;
}
int
mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
{
- if (regno >= FIRST_PSEUDO_REGISTER)
+ if (!HARD_REGISTER_NUM_P (regno))
{
if (!strict)
return true;
/* The address will have to be loaded from the GOT first. */
return false;
- case SYMBOL_TLSGD:
- case SYMBOL_TLSLDM:
- case SYMBOL_DTPREL:
- case SYMBOL_TPREL:
- case SYMBOL_GOTTPREL:
- case SYMBOL_TLS:
- return false;
-
case SYMBOL_GOTOFF_PAGE:
case SYMBOL_GOTOFF_GLOBAL:
case SYMBOL_GOTOFF_CALL:
case SYMBOL_GOTOFF_LOADGP:
+ case SYMBOL_TLS:
+ case SYMBOL_TLSGD:
+ case SYMBOL_TLSLDM:
+ case SYMBOL_DTPREL:
+ case SYMBOL_GOTTPREL:
+ case SYMBOL_TPREL:
case SYMBOL_64_HIGH:
case SYMBOL_64_MID:
case SYMBOL_64_LOW:
v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
model = SYMBOL_REF_TLS_MODEL (loc);
+ /* Only TARGET_ABICALLS code can have more than one module; other
+ code must be be static and should not use a GOT. All TLS models
+ reduce to local exec in this situation. */
+ if (!TARGET_ABICALLS)
+ model = TLS_MODEL_LOCAL_EXEC;
switch (model)
{
break;
case TLS_MODEL_LOCAL_EXEC:
-
if (Pmode == DImode)
emit_insn (gen_tls_get_tp_di (v1));
else
return true;
}
- /* We can use cmpi for an xor with an unsigned 16 bit value. */
+ /* We can use cmpi for an xor with an unsigned 16-bit value. */
if ((outer_code) == XOR
&& INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
{
}
/* We may be able to use slt or sltu for a comparison with a
- signed 16 bit value. (The boundary conditions aren't quite
+ signed 16-bit value. (The boundary conditions aren't quite
right, but this is just a heuristic anyhow.) */
if (((outer_code) == LT || (outer_code) == LE
|| (outer_code) == GE || (outer_code) == GT
return true;
case SIGN_EXTEND:
- /* A sign extend from SImode to DImode in 64 bit mode is often
+ /* A sign extend from SImode to DImode in 64-bit mode is often
zero instructions, because the result can often be used
directly by another instruction; we'll call it one. */
if (TARGET_64BIT && mode == DImode
if (FP_REG_RTX_P (dest))
{
/* Loading an FPR from memory or from GPRs. */
- emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
- emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
- copy_rtx (dest)));
+ if (ISA_HAS_MXHC1)
+ {
+ dest = gen_lowpart (DFmode, dest);
+ emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
+ emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
+ copy_rtx (dest)));
+ }
+ else
+ {
+ emit_insn (gen_load_df_low (copy_rtx (dest),
+ mips_subword (src, 0)));
+ emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
+ copy_rtx (dest)));
+ }
}
else if (FP_REG_RTX_P (src))
{
/* Storing an FPR into memory or GPRs. */
- emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
- emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
+ if (ISA_HAS_MXHC1)
+ {
+ src = gen_lowpart (DFmode, src);
+ emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
+ emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
+ }
+ else
+ {
+ emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
+ emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
+ }
}
else
{
if (src_code == CONST_INT)
{
/* Don't use the X format, because that will give out of
- range numbers for 64 bit hosts and 32 bit targets. */
+ range numbers for 64-bit hosts and 32-bit targets. */
if (!TARGET_MIPS16)
return "li\t%0,%1\t\t\t# %X1";
comparison. */
static bool
-mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
+mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
enum machine_mode mode)
{
HOST_WIDE_INT original, plus_one;
if (GET_CODE (*cmp1) != CONST_INT)
return false;
-
+
original = INTVAL (*cmp1);
plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
-
+
switch (*code)
{
case LE:
return true;
}
break;
-
+
case LEU:
if (plus_one != 0)
{
return true;
}
break;
-
+
default:
return false;
}
-
+
return false;
}
cmp0, cmp1, 0, 0, OPTAB_DIRECT);
}
+/* Convert *CODE into a code that can be used in a floating-point
+ scc instruction (c.<cond>.<fmt>). Return true if the values of
+ the condition code registers will be inverted, with 0 indicating
+ that the condition holds. */
+
+static bool
+mips_reverse_fp_cond_p (enum rtx_code *code)
+{
+ switch (*code)
+ {
+ case NE:
+ case LTGT:
+ case ORDERED:
+ *code = reverse_condition_maybe_unordered (*code);
+ return true;
+
+ default:
+ return false;
+ }
+}
+
/* Convert a comparison into something that can be used in a branch or
conditional move. cmp_operands[0] and cmp_operands[1] are the values
being compared and *CODE is the code used to compare them.
Set CMP_CODE to the code of the comparison instruction and
*CODE to the code that the branch or move should use. */
- switch (*code)
- {
- case NE:
- case LTGT:
- case ORDERED:
- cmp_code = reverse_condition_maybe_unordered (*code);
- *code = EQ;
- break;
-
- default:
- cmp_code = *code;
- *code = NE;
- break;
- }
+ cmp_code = *code;
+ *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
*op0 = (ISA_HAS_8CC
? gen_reg_rtx (CCmode)
: gen_rtx_REG (CCmode, FPSW_REGNUM));
emit_jump_insn (gen_condjump (condition, operands[0]));
}
+/* Implement:
+
+ (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
+ (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
+
+void
+mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
+ enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
+{
+ rtx cmp_result;
+ bool reversed_p;
+
+ reversed_p = mips_reverse_fp_cond_p (&cond);
+ cmp_result = gen_reg_rtx (CCV2mode);
+ emit_insn (gen_scc_ps (cmp_result,
+ gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
+ if (reversed_p)
+ emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
+ cmp_result));
+ else
+ emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
+ cmp_result));
+}
+
/* Emit the common code for conditional moves. OPERANDS is the array
of operands passed to the conditional move define_expand. */
&& host_integerp (TYPE_SIZE_UNIT (type), 1)
&& named)
{
- /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
- structure contains a double in its entirety, then that 64 bit
+ /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
+ structure contains a double in its entirety, then that 64-bit
chunk is passed in a floating point register. */
tree field;
if (field != 0)
{
/* Now handle the special case by returning a PARALLEL
- indicating where each 64 bit chunk goes. INFO.REG_WORDS
+ indicating where each 64-bit chunk goes. INFO.REG_WORDS
chunks are passed in registers. */
unsigned int i;
HOST_WIDE_INT bitpos;
inner = GET_MODE_INNER (mode);
reg = FP_ARG_FIRST + info.reg_offset;
- real = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (inner, reg),
- const0_rtx);
- imag = gen_rtx_EXPR_LIST (VOIDmode,
- gen_rtx_REG (inner, reg + info.reg_words / 2),
- GEN_INT (GET_MODE_SIZE (inner)));
- return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
+ if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
+ {
+ /* Real part in registers, imaginary part on stack. */
+ gcc_assert (info.stack_words == info.reg_words);
+ return gen_rtx_REG (inner, reg);
+ }
+ else
+ {
+ gcc_assert (info.stack_words == 0);
+ real = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (inner, reg),
+ const0_rtx);
+ imag = gen_rtx_EXPR_LIST (VOIDmode,
+ gen_rtx_REG (inner,
+ reg + info.reg_words / 2),
+ GEN_INT (GET_MODE_SIZE (inner)));
+ return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
+ }
}
if (!info.fpr_p)
t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
build_int_cst (NULL_TREE,
cum->stack_words * UNITS_PER_WORD));
- t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
/* Emit code to initialize GTOP, the top of the GPR save area. */
t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
- t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
/* Emit code to initialize FTOP, the top of the FPR save area.
if (fpr_offset)
t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
build_int_cst (NULL_TREE, -fpr_offset));
- t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
/* Emit code to initialize GOFF, the offset from GTOP of the
next GPR argument. */
- t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
build_int_cst (NULL_TREE, gpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
/* Likewise emit code to initialize FOFF, the offset from FTOP
of the next FPR argument. */
- t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
build_int_cst (NULL_TREE, fpr_save_area_size));
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
/* [1] Emit code for: off &= -rsize. */
t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
build_int_cst (NULL_TREE, -rsize));
- t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
+ t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
gimplify_and_add (t, pre_p);
}
osize = rsize;
u = fold_convert (TREE_TYPE (ovfl),
build_int_cst (NULL_TREE, -osize));
t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
- align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
+ align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
}
else
align = NULL;
mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
{
rtx left, right;
+ enum machine_mode mode;
if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
return false;
- src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
+ mode = mode_for_size (width, MODE_INT, 0);
+ src = gen_lowpart (mode, src);
- if (GET_MODE (src) == DImode)
+ if (mode == DImode)
{
emit_insn (gen_mov_sdl (dest, src, left));
emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
return true;
}
+/* Return true if X is a MEM with the same size as MODE. */
+
+bool
+mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
+{
+ rtx size;
+
+ if (!MEM_P (x))
+ return false;
+
+ size = MEM_SIZE (x);
+ return size && INTVAL (size) == GET_MODE_SIZE (mode);
+}
+
/* Return true if (zero_extract OP SIZE POSITION) can be used as the
source of an "ext" instruction or the destination of an "ins"
instruction. OP must be a register operand and the following
len = INTVAL (size);
pos = INTVAL (position);
-
- if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
+
+ if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
|| pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
return false;
mips_set_tune (mips_arch_info);
/* Set cost structure for the processor. */
- mips_cost = &mips_rtx_cost_data[mips_tune];
+ if (optimize_size)
+ mips_cost = &mips_rtx_cost_optimize_size;
+ else
+ mips_cost = &mips_rtx_cost_data[mips_tune];
if ((target_flags_explicit & MASK_64BIT) != 0)
{
only one right answer here. */
if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
- else if (!TARGET_64BIT && TARGET_FLOAT64)
- error ("unsupported combination: %s", "-mgp32 -mfp64");
+ else if (!TARGET_64BIT && TARGET_FLOAT64
+ && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
+ error ("-mgp32 and -mfp64 can only be combined if the target"
+ " supports the mfhc1 and mthc1 instructions");
else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
error ("unsupported combination: %s", "-mfp64 -msingle-float");
}
the -G limit but declared by the user to be in a section other
than .sbss or .sdata. */
-int
-mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
-{
- register struct extern_list *p;
-
- if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
- {
- p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
- p->next = extern_head;
- p->name = name;
- p->size = int_size_in_bytes (TREE_TYPE (decl));
- extern_head = p;
- }
-
- if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
- {
- p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
- p->next = extern_head;
- p->name = name;
- p->size = -1;
- extern_head = p;
- }
-
- return 0;
-}
-
-#if TARGET_IRIX
-static void
-irix_output_external_libcall (rtx fun)
+void
+mips_output_external (FILE *file, tree decl, const char *name)
{
- register struct extern_list *p;
+ default_elf_asm_output_external (file, decl, name);
- if (mips_abi == ABI_32)
+ /* We output the name if and only if TREE_SYMBOL_REFERENCED is
+ set in order to avoid putting out names that are never really
+ used. */
+ if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
{
- p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
- p->next = extern_head;
- p->name = XSTR (fun, 0);
- p->size = -1;
- extern_head = p;
+ if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
+ {
+ fputs ("\t.extern\t", file);
+ assemble_name (file, name);
+ fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
+ int_size_in_bytes (TREE_TYPE (decl)));
+ }
+ else if (TARGET_IRIX
+ && mips_abi == ABI_32
+ && TREE_CODE (decl) == FUNCTION_DECL)
+ {
+ /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
+ `.global name .text' directive for every used but
+ undefined function. If we don't, the linker may perform
+ an optimization (skipping over the insns that set $gp)
+ when it is unsafe. */
+ fputs ("\t.globl ", file);
+ assemble_name (file, name);
+ fputs (" .text\n", file);
+ }
}
}
-#endif
\f
/* Emit a new filename to a stream. If we are smuggling stabs, try to
put out a MIPS ECOFF file and a stab. */
/* There is no ELF header flag to distinguish long32 forms of the
EABI from long64 forms. Emit a special section to help tools
- such as GDB. */
- if (mips_abi == ABI_EABI)
+ such as GDB. Do the same for o64, which is sometimes used with
+ -mlong64. */
+ if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
TARGET_LONG64 ? 64 : 32);
}
#endif
\f
-/* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
- .externs for any small-data variables that turned out to be external. */
-
-static void
-mips_file_end (void)
-{
- tree name_tree;
- struct extern_list *p;
-
- if (extern_head)
- {
- fputs ("\n", asm_out_file);
-
- for (p = extern_head; p != 0; p = p->next)
- {
- name_tree = get_identifier (p->name);
-
- /* Positively ensure only one .extern for any given symbol. */
- if (!TREE_ASM_WRITTEN (name_tree)
- && TREE_SYMBOL_REFERENCED (name_tree))
- {
- TREE_ASM_WRITTEN (name_tree) = 1;
- /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
- `.global name .text' directive for every used but
- undefined function. If we don't, the linker may perform
- an optimization (skipping over the insns that set $gp)
- when it is unsafe. */
- if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
- {
- fputs ("\t.globl ", asm_out_file);
- assemble_name (asm_out_file, p->name);
- fputs (" .text\n", asm_out_file);
- }
- else
- {
- fputs ("\t.extern\t", asm_out_file);
- assemble_name (asm_out_file, p->name);
- fprintf (asm_out_file, ", %d\n", p->size);
- }
- }
- }
- }
-}
-
/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
elfos.h version, but we also need to handle -muninit-const-in-rodata. */
{
rtx mem;
- mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
+ mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
fn (gen_rtx_REG (mode, regno), mem);
}
/* Save registers starting from high to low. The debuggers prefer at least
the return register be stored at func+4, and also it allows us not to
- need a nop in the epilog if at least one register is reloaded in
+ need a nop in the epilogue if at least one register is reloaded in
addition to return address. */
offset = cfun->machine->frame.gp_sp_offset - sp_offset;
for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
#endif
/* In mips16 mode, we may need to generate a 32 bit to handle
- floating point arguments. The linker will arrange for any 32 bit
- functions to call this stub, which will then jump to the 16 bit
+ floating point arguments. The linker will arrange for any 32-bit
+ functions to call this stub, which will then jump to the 16-bit
function proper. */
if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
&& current_function_args_info.fp_code != 0)
{
rtx offset = GEN_INT (cfun->machine->frame.args_size);
if (SMALL_OPERAND (cfun->machine->frame.args_size))
- RTX_FRAME_RELATED_P
+ RTX_FRAME_RELATED_P
(emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
stack_pointer_rtx,
offset))) = 1;
MIPS_PROLOGUE_TEMP (Pmode)));
mips_set_frame_expr
(gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
- plus_constant (stack_pointer_rtx,
+ plus_constant (stack_pointer_rtx,
cfun->machine->frame.args_size)));
}
}
return data_section;
}
-/* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
- access DECL using %gp_rel(...)($gp). */
+/* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
+ locally-defined objects go in a small data section. It also controls
+ the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
+ mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
static bool
mips_in_small_data_p (tree decl)
int size;
/* ??? How should SCmode be handled? */
- if (type == NULL_TREE || mode == DImode || mode == DFmode)
+ if (mode == DImode || mode == DFmode)
return 0;
- size = int_size_in_bytes (type);
+ size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
return size == -1 || size > UNITS_PER_WORD;
}
else
return true;
}
}
+
+ /* gcc assumes that each word of a multiword register can be accessed
+ individually using SUBREGs. This is not true for floating-point
+ registers if they are bigger than a word. */
+ if (UNITS_PER_FPREG > UNITS_PER_WORD
+ && GET_MODE_SIZE (from) > UNITS_PER_WORD
+ && GET_MODE_SIZE (to) < UNITS_PER_FPREG
+ && reg_classes_intersect_p (FP_REGS, class))
+ return true;
+
/* Loading a 32-bit value into a 64-bit floating-point register
will not sign-extend the value, despite what LOAD_EXTEND_OP says.
We can't allow 64-bit float registers to change from SImode to
to a wider mode. */
- if (TARGET_FLOAT64
+ if (TARGET_64BIT
+ && TARGET_FLOAT64
&& from == SImode
&& GET_MODE_SIZE (to) >= UNITS_PER_WORD
&& reg_classes_intersect_p (FP_REGS, class))
return true;
+
return false;
}
/* Implement CLASS_MAX_NREGS.
- Usually all registers are word-sized. The only supported exception
- is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
- registers. A word-based calculation is correct even in that case,
- since -msingle-float disallows multi-FPR values.
+ - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
- The FP status registers are an exception to this rule. They are always
- 4 bytes wide as they only hold condition code modes, and CCmode is always
- considered to be 4 bytes wide. */
+ - ST_REGS are always hold CCmode values, and CCmode values are
+ considered to be 4 bytes wide.
+
+ All other register classes are covered by UNITS_PER_WORD. Note that
+ this is true even for unions of integer and float registers when the
+ latter are smaller than the former. The only supported combination
+ in which case this occurs is -mgp64 -msingle-float, which has 64-bit
+ words but 32-bit float registers. A word-based calculation is correct
+ in that case since -msingle-float disallows multi-FPR values. */
int
mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
{
if (class == ST_REGS)
return (GET_MODE_SIZE (mode) + 3) / 4;
+ else if (class == FP_REGS)
+ return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
else
return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}
int gparg, fparg;
unsigned int f;
- /* This code only works for the original 32 bit ABI and the O64 ABI. */
+ /* This code only works for the original 32-bit ABI and the O64 ABI. */
gcc_assert (TARGET_OLDABI);
if (from_fp_p)
}
/* Build a mips16 function stub. This is used for functions which
- take arguments in the floating point registers. It is 32 bit code
+ take arguments in the floating point registers. It is 32-bit code
that moves the floating point args into the general registers, and
- then jumps to the 16 bit code. */
+ then jumps to the 16-bit code. */
static void
build_mips16_function_stub (FILE *file)
/* Build a call stub for a mips16 call. A stub is needed if we are
passing any floating point values which should go into the floating
- point registers. If we are, and the call turns out to be to a 32
- bit function, the stub will be used to move the values into the
- floating point registers before calling the 32 bit function. The
- linker will magically adjust the function call to either the 16 bit
- function or the 32 bit stub, depending upon where the function call
+ point registers. If we are, and the call turns out to be to a
+ 32-bit function, the stub will be used to move the values into the
+ floating point registers before calling the 32-bit function. The
+ linker will magically adjust the function call to either the 16-bit
+ function or the 32-bit stub, depending upon where the function call
is actually defined.
Similarly, we need a stub if the return value might come back in a
{
/* Build a special purpose stub. When the linker sees a
function call in mips16 code, it will check where the target
- is defined. If the target is a 32 bit call, the linker will
+ is defined. If the target is a 32-bit call, the linker will
search for the section defined here. It can tell which
symbol this section is associated with by looking at the
relocation information (the name is unreliable, since this
}
/* We build the stub code by hand. That's the only way we can
- do it, since we can't generate 32 bit code during a 16 bit
+ do it, since we can't generate 32-bit code during a 16-bit
compilation. */
/* We don't want the assembler to insert any nops here. */
static bool
vr4130_swap_insns_p (rtx insn1, rtx insn2)
{
- rtx dep;
+ dep_link_t dep;
/* Check for the following case:
If INSN1 is the last instruction blocking X, it would better to
choose (INSN1, X) over (INSN2, INSN1). */
- for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
- if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
- && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
- && recog_memoized (XEXP (dep, 0)) >= 0
- && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
+ FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
+ if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
+ && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
+ && recog_memoized (DEP_LINK_CON (dep)) >= 0
+ && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
return false;
if (vr4130_last_insn != 0
return 2;
case PROCESSOR_SB1:
+ case PROCESSOR_SB1A:
/* This is actually 4, but we get better performance if we claim 3.
This is partly because of unwanted speculative code motion with the
larger number, and partly because in most common cases we can't
mips_multipass_dfa_lookahead (void)
{
/* Can schedule up to 4 of the 6 function units in any one cycle. */
- if (mips_tune == PROCESSOR_SB1)
+ if (TUNE_SB1)
return 4;
return 0;
}
+
+/* Implements a store data bypass check. We need this because the cprestore
+ pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
+ default routine to abort. We just return false for that case. */
+/* ??? Should try to give a better result here than assuming false. */
+
+int
+mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
+{
+ if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
+ return false;
+
+ return ! store_data_bypass_p (out_insn, in_insn);
+}
\f
/* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
return the first operand of the associated "pref" or "prefx" insn. */
CMP_4S_BUILTINS (c, COND), \
CMP_4S_BUILTINS (cabs, COND)
-/* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
-#define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
-
static const struct builtin_description mips_bdesc[] =
{
DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
{ dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
};
-/* Take the head of argument list *ARGLIST and convert it into a form
- suitable for input operand OP of instruction ICODE. Return the value
- and point *ARGLIST at the next element of the list. */
+/* Take the argument ARGNUM of the arglist of EXP and convert it into a form
+ suitable for input operand OP of instruction ICODE. Return the value. */
static rtx
mips_prepare_builtin_arg (enum insn_code icode,
- unsigned int op, tree *arglist)
+ unsigned int op, tree exp, unsigned int argnum)
{
rtx value;
enum machine_mode mode;
- value = expand_normal (TREE_VALUE (*arglist));
+ value = expand_normal (CALL_EXPR_ARG (exp, argnum));
mode = insn_data[icode].operand[op].mode;
if (!insn_data[icode].operand[op].predicate (value, mode))
{
}
}
- *arglist = TREE_CHAIN (*arglist);
return value;
}
{
enum insn_code icode;
enum mips_builtin_type type;
- tree fndecl, arglist;
+ tree fndecl;
unsigned int fcode;
const struct builtin_description *bdesc;
const struct bdesc_map *m;
- fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
- arglist = TREE_OPERAND (exp, 1);
+ fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
fcode = DECL_FUNCTION_CODE (fndecl);
bdesc = NULL;
switch (type)
{
case MIPS_BUILTIN_DIRECT:
- return mips_expand_builtin_direct (icode, target, arglist, true);
+ return mips_expand_builtin_direct (icode, target, exp, true);
case MIPS_BUILTIN_DIRECT_NO_TARGET:
- return mips_expand_builtin_direct (icode, target, arglist, false);
+ return mips_expand_builtin_direct (icode, target, exp, false);
case MIPS_BUILTIN_MOVT:
case MIPS_BUILTIN_MOVF:
return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
- target, arglist);
+ target, exp);
case MIPS_BUILTIN_CMP_ANY:
case MIPS_BUILTIN_CMP_ALL:
case MIPS_BUILTIN_CMP_LOWER:
case MIPS_BUILTIN_CMP_SINGLE:
return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
- target, arglist);
+ target, exp);
case MIPS_BUILTIN_BPOSGE32:
return mips_expand_builtin_bposge (type, target);
if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
if ((d->target_flags & target_flags) == d->target_flags)
- lang_hooks.builtin_function (d->name, types[d->function_type],
- d - m->bdesc + offset,
- BUILT_IN_MD, NULL, NULL);
+ add_builtin_function (d->name, types[d->function_type],
+ d - m->bdesc + offset,
+ BUILT_IN_MD, NULL, NULL);
offset += m->size;
}
}
/* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
- .md pattern and ARGLIST is the list of function arguments. TARGET,
+ .md pattern and CALL is the function expr with arguments. TARGET,
if nonnull, suggests a good place to put the result.
HAS_TARGET indicates the function must return something. */
static rtx
-mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
+mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
bool has_target)
{
rtx ops[MAX_RECOG_OPERANDS];
int i = 0;
+ int j = 0;
if (has_target)
{
i = 1;
}
- /* We need to test if arglist is not zero. Some instructions have extra
+ /* We need to test if the arglist is not zero. Some instructions have extra
clobber registers. */
- for (; i < insn_data[icode].n_operands && arglist != 0; i++)
- ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
+ for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
+ ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
switch (i)
{
}
/* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
- function (TYPE says which). ARGLIST is the list of arguments to the
+ function (TYPE says which). EXP is the tree for the function
function, ICODE is the instruction that should be used to compare
the first two arguments, and COND is the condition it should test.
TARGET, if nonnull, suggests a good place to put the result. */
static rtx
mips_expand_builtin_movtf (enum mips_builtin_type type,
enum insn_code icode, enum mips_fp_condition cond,
- rtx target, tree arglist)
+ rtx target, tree exp)
{
rtx cmp_result, op0, op1;
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
- op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
icode = CODE_FOR_mips_cond_move_tf_ps;
target = mips_prepare_builtin_target (icode, 0, target);
if (type == MIPS_BUILTIN_MOVT)
{
- op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
- op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
}
else
{
- op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
- op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
+ op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
+ op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
}
emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
return target;
/* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
of the comparison instruction and COND is the condition it should test.
- ARGLIST is the list of function arguments and TARGET, if nonnull,
+ EXP is the function call and arguments and TARGET, if nonnull,
suggests a good place to put the boolean result. */
static rtx
mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
enum insn_code icode, enum mips_fp_condition cond,
- rtx target, tree arglist)
+ rtx target, tree exp)
{
rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
int i;
+ int j = 0;
if (target == 0 || GET_MODE (target) != SImode)
target = gen_reg_rtx (SImode);
/* Prepare the operands to the comparison. */
cmp_result = mips_prepare_builtin_target (icode, 0, 0);
- for (i = 1; i < insn_data[icode].n_operands - 1; i++)
- ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
+ for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
+ ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
switch (insn_data[icode].n_operands)
{
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