* doc/tm.texi (defmac SMALL_REGISTER_CLASSES): Remove.

[pf3gnuchains/gcc-fork.git] / gcc / config / mips / 5400.md

diff --git a/gcc/config/mips/5400.md b/gcc/config/mips/5400.md
index 70386fc..362999d 100644 (file)
--- a/gcc/config/mips/5400.md
+++ b/gcc/config/mips/5400.md
@@ -1,3 +1,21 @@
+;; Copyright (C) 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+;;
 ;; DFA-based pipeline description for 5400
 (define_automaton "vr54")
 (define_cpu_unit "vr54_dp0"     "vr54")
@@ -26,20 +44,17 @@
 
 (define_insn_reservation "ir_vr54_load" 2
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "load")
-            (eq_attr "mode" "!SF,DF,FPSW")))
+       (eq_attr "type" "load,fpload,fpidxload"))
   "vr54_mem")
 
 (define_insn_reservation "ir_vr54_store" 1
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "store")
-            (eq_attr "mode" "!SF,DF,FPSW")))
+       (eq_attr "type" "store"))
   "vr54_mem")
 
 (define_insn_reservation "ir_vr54_fstore" 1
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "store")
-            (eq_attr "mode" "SF,DF")))
+       (eq_attr "type" "fpstore,fpidxstore"))
   "vr54_mem")
 
 
@@ -53,34 +68,34 @@
 ;; Move to/from FPU registers
 (define_insn_reservation "ir_vr54_xfer" 2
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_hilo" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "hilo"))
+       (eq_attr "type" "mthilo,mfhilo"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_arith" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+       (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_si" 3
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "imul")
+       (and (eq_attr "type" "imul,imul3")
             (eq_attr "mode" "SI")))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_di" 4
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "imul")
+       (and (eq_attr "type" "imul,imul3")
             (eq_attr "mode" "DI")))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imadd_si" 3
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "imul"))
+       (eq_attr "type" "imul,imul3"))
   "vr54_mac")
 
 (define_insn_reservation "ir_vr54_idiv_si" 42
@@ -126,19 +141,19 @@
 
 (define_insn_reservation "ir_vr54_fdiv_sf" 42
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "fdiv,fsqrt")
+       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
             (eq_attr "mode" "SF")))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_fdiv_df" 72
   (and (eq_attr "cpu" "r5400")
-       (and (eq_attr "type" "fdiv,fsqrt")
+       (and (eq_attr "type" "fdiv,frdiv,fsqrt")
             (eq_attr "mode" "DF")))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_fabs" 2
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "fabs,fneg"))
+       (eq_attr "type" "fabs,fneg,fmove"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_fcmp" 2