-;; DFA based pipeline description for the r3000
-;; This is a special pipeline - this is also the default schedule and
-;; so we need to schedule instructions that may not exist on the r2k/r3k.
+;; R3000 and TX39 pipeline description.
+;; Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
-;; Generic processor description that assumes that the only latencies are for
-;; hazards or delay slots, otherwise everything is assumed to issue and execute
-;; in one cycle.
-(define_automaton "r3k")
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
-(define_cpu_unit "r3k_alu" "r3k")
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+;; License for more details.
-(define_insn_reservation "r3k_generic_alu" 1
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop"))
- "r3k_alu")
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING. If not, write to the
+;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
+;; MA 02110-1301, USA.
-(define_insn_reservation "r3k_load_alu" 2
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "load, fpload, fpidxload, xfer"))
- "r3k_alu*2")
-(define_insn_reservation "r3k_call_alu" 2
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "branch,jump,call"))
- "r3k_alu*2")
+;; This file overrides parts of generic.md. It is derived from the
+;; old define_function_unit description.
-(define_insn_reservation "r3k_hilo_alu" 3
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "mfhilo"))
- "r3k_alu*3")
+(define_insn_reservation "r3k_load" 2
+ (and (eq_attr "cpu" "r3000,r3900")
+ (eq_attr "type" "load,fpload,fpidxload"))
+ "alu")
-(define_insn_reservation "r3k_fcmp_alu" 2
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "fcmp, fadd"))
- "r3k_alu*2")
+(define_insn_reservation "r3k_imul" 12
+ (and (eq_attr "cpu" "r3000,r3900")
+ (eq_attr "type" "imul,imul3,imadd"))
+ "imuldiv*12")
-(define_insn_reservation "r3k_imul_alu" 12
- (and (eq_attr "cpu" "r3000")
- (eq_attr "type" "imul, imadd"))
- "r3k_alu*12")
-
-(define_insn_reservation "r3k_idiv_alu" 35
- (and (eq_attr "cpu" "r3000")
+(define_insn_reservation "r3k_idiv" 35
+ (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "idiv"))
- "r3k_alu*35")
+ "imuldiv*35")
+
+(define_insn_reservation "r3k_fmove" 1
+ (and (eq_attr "cpu" "r3000,r3900")
+ (eq_attr "type" "fabs,fneg,fmove"))
+ "alu")
+
+(define_insn_reservation "r3k_fadd" 2
+ (and (eq_attr "cpu" "r3000,r3900")
+ (eq_attr "type" "fcmp,fadd"))
+ "alu")
-(define_insn_reservation "r3k_fmul_single_alu" 4
- (and (eq_attr "cpu" "r3000")
- (and (eq_attr "type" "fmul")
+(define_insn_reservation "r3k_fmul_single" 4
+ (and (eq_attr "cpu" "r3000,r3900")
+ (and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
- "r3k_alu*4")
+ "alu")
-(define_insn_reservation "r3k_fmul_double_alu" 5
- (and (eq_attr "cpu" "r3000")
- (and (eq_attr "type" "fmul")
+(define_insn_reservation "r3k_fmul_double" 5
+ (and (eq_attr "cpu" "r3000,r3900")
+ (and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
- "r3k_alu*5")
+ "alu")
-(define_insn_reservation "r3k_fdiv_single_alu" 12
- (and (eq_attr "cpu" "r3000")
- (and (eq_attr "type" "fdiv")
+(define_insn_reservation "r3k_fdiv_single" 12
+ (and (eq_attr "cpu" "r3000,r3900")
+ (and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "SF")))
- "r3k_alu*12")
+ "alu")
-(define_insn_reservation "r3k_fdiv_double_alu" 19
- (and (eq_attr "cpu" "r3000")
- (and (eq_attr "type" "fdiv")
+(define_insn_reservation "r3k_fdiv_double" 19
+ (and (eq_attr "cpu" "r3000,r3900")
+ (and (eq_attr "type" "fdiv,frdiv")
(eq_attr "mode" "DF")))
- "r3k_alu*19")
+ "alu")
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