;;- Machine description for the Motorola 88000 for GNU C compiler
-;; Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
+;;; Copyright (C) 1988, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
;; Contributed by Michael Tiemann (tiemann@mcc.com)
-;; Additional changes by Michael Meissner (meissner@osf.org)
-;; Currently supported by Tom Wood (wood@dg-rtp.dg.com)
+;; Currently maintained by (gcc@dg-rtp.dg.com)
;; This file is part of GNU CC.
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
-;; SCCS rev field. This is a NOP, just to get the SCCS id into the
+;; RCS rev field. This is a NOP, just to get the RCS id into the
;; program image.
-(define_expand "m88k_sccs_id"
+(define_expand "m88k_rcs_id"
[(match_operand:SI 0 "" "")]
""
- "{ static char sccs_id[] = \"@(#)m88k.md 2.3.2.2 11/05/92 09:03:51\";
+ "{ static char rcs_id[] = \"$What: <@(#) m88k.md,v 1.1.1.2.2.2> $\";
FAIL; }")
\f
-;; Attribute specifications
+;; Attribute describing the processor. This attribute must match exactly
+;; with the processor_type enumeration in m88k.h.
; Target CPU.
(define_attr "cpu" "m88100,m88110,m88000"
; Length in # of instructions of each insn. The values are not exact, but
; are safe.
(define_attr "length" ""
- (cond [(eq_attr "type" "marith")
+ (cond [(eq_attr "type" "marith,weird,branch")
(const_int 2)]
(const_int 1)))
;; (tege@sics.se). They've changed since then, so don't complain to him
;; if they don't work right.
-;; Regarding shifts, gen_lshlsi3 generates ASHIFT. LSHIFT opcodes are
-;; not produced and should not normally occur. Also, the gen functions
+;; Regarding shifts, gen_lshlsi3 generates ASHIFT. The gen functions
;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing
;; special needs to be done here.
;; We define all logical operations on CCmode values to preserve the pairwise
;; relationship of the compare bits. This allows a future branch prediction
;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt.
+;; THIS IS CURRENTLY FALSE!
;;
;; Opportunities arise when conditional expressions using && and || are made
;; unconditional. When these are used to branch, the sequence is
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
(ior:SI (neg:SI
- (match_operator 1 "relop"
- [(match_operand:CC 2 "register_operand" "%r")
+ (match_operator 1 "even_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "relop"
- [(match_operand:CC 4 "register_operand" "r")
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
- (ior:CC (match_dup 4)
+ (ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
- "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else if (GET_CODE (operands[1])
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
- (ior:SI (match_operator 1 "relop"
- [(match_operand:CC 2 "register_operand" "%r")
+ (ior:SI (neg:SI
+ (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)]))
+ (neg:SI
+ (match_operator 3 "odd_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)]))))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 5)
+ (and:CCEVEN (match_dup 4)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+ if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
+ ; /* The conditions match. */
+ else
+ {
+ /* Make the condition pairs line up by rotating the compare word. */
+ int cv1 = condition_value (operands[1]);
+ int cv2 = condition_value (operands[3]);
+
+ operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
+ gen_rtx (CONST_INT, VOIDmode,
+ (cv2 - cv1) & 0x1f));
+ }")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (neg:SI
+ (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)]))
+ (neg:SI
+ (match_operator 3 "even_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)]))))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 5)
+ (ior:CCEVEN (not:CC (match_dup 2))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+ if (GET_CODE (operands[1])
+ == reverse_condition (GET_CODE (operands[3])))
+ ;
+ else
+ {
+ /* Make the condition pairs line up by rotating the compare word. */
+ int cv1 = condition_value (operands[1]);
+ int cv2 = condition_value (operands[3]);
+
+ operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
+ gen_rtx (CONST_INT, VOIDmode,
+ ((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
+ }")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (match_operator 1 "even_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "relop"
- [(match_operand:CC 4 "register_operand" "r")
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])
|| GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
- (ior:CC (match_dup 4)
+ (ior:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
- "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
/* Reverse the condition by complimenting the compare word. */
if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)])
+ (match_operator 3 "odd_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+ [(set (match_dup 5)
+ (and:CCEVEN (match_dup 4)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)])
+ (match_operator 3 "even_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+ [(set (match_dup 5)
+ (ior:CCEVEN (not:CC (match_dup 4))
+ (match_dup 2)))
+ (set (match_dup 0)
+ (match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
(and:SI (neg:SI
- (match_operator 1 "relop"
- [(match_operand:CC 2 "register_operand" "%r")
+ (match_operator 1 "even_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)]))
(neg:SI
(match_operator 3 "relop"
- [(match_operand:CC 4 "register_operand" "r")
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)]))))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
""
[(set (match_dup 5)
- (and:CC (match_dup 4)
+ (and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
- "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
; /* The conditions match. */
else if (GET_CODE (operands[1])
/* Make the condition pairs line up by rotating the compare word. */
int cv1 = condition_value (operands[1]);
int cv2 = condition_value (operands[3]);
-
operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
gen_rtx (CONST_INT, VOIDmode,
((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
(define_split
[(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (match_operator 1 "relop"
- [(match_operand:CC 2 "register_operand" "%r")
+ (and:SI (neg:SI
+ (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)]))
+ (neg:SI
+ (match_operator 3 "odd_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)]))))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 5)
+ (ior:CCEVEN (match_dup 4)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+ if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
+ ; /* The conditions match. */
+ else
+ {
+ /* Make the condition pairs line up by rotating the compare word. */
+ int cv1 = condition_value (operands[1]);
+ int cv2 = condition_value (operands[3]);
+ operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
+ gen_rtx (CONST_INT, VOIDmode,
+ (cv2 - cv1) & 0x1f));
+ }")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (neg:SI
+ (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)]))
+ (neg:SI
+ (match_operator 3 "even_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)]))))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 5)
+ (and:CCEVEN (not:CC (match_dup 2))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+ if (GET_CODE (operands[1])
+ == reverse_condition (GET_CODE (operands[3])))
+ ;
+ else
+ {
+ /* Make the condition pairs line up by rotating the compare word. */
+ int cv1 = condition_value (operands[1]);
+ int cv2 = condition_value (operands[3]);
+ operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
+ gen_rtx (CONST_INT, VOIDmode,
+ ((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
+ }")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (match_operator 1 "even_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
(const_int 0)])
(match_operator 3 "relop"
- [(match_operand:CC 4 "register_operand" "r")
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
(const_int 0)])))
(clobber (match_operand:SI 5 "register_operand" "=r"))]
"GET_CODE (operands[1]) == GET_CODE (operands[3])
|| GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
[(set (match_dup 5)
- (and:CC (match_dup 4)
+ (and:CCEVEN (match_dup 4)
(match_dup 2)))
(set (match_dup 0)
(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
- "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
/* Reverse the condition by complimenting the compare word. */
if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)])
+ (match_operator 3 "odd_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+ [(set (match_dup 5)
+ (ior:CCEVEN (match_dup 4)
+ (match_dup 2)))
+ (set (match_dup 0)
+ (match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (and:SI (match_operator 1 "odd_relop"
+ [(match_operand 2 "partial_ccmode_register_operand" "%r")
+ (const_int 0)])
+ (match_operator 3 "even_relop"
+ [(match_operand 4 "partial_ccmode_register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_operand:SI 5 "register_operand" "=r"))]
+ "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+ [(set (match_dup 5)
+ (and:CCEVEN (not:CC (match_dup 2))
+ (match_dup 4)))
+ (set (match_dup 0)
+ (match_op_dup 3 [(match_dup 5) (const_int 0)]))]
+ "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
\f
;; Logical operations on compare words.
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
- (match_operand:CC 2 "register_operand" "r")))]
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
+ (match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"and.c %0,%2,%1")
-
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (match_operand:CC 1 "register_operand" "%r")
- (match_operand:CC 2 "register_operand" "r")))]
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
+ (match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"and %0,%1,%2")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
- (match_operand:CC 2 "register_operand" "r")))]
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
+ (match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"or.c %0,%2,%1")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (match_operand:CC 1 "register_operand" "%r")
- (match_operand:CC 2 "register_operand" "r")))]
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
+ (match_operand 2 "partial_ccmode_register_operand" "r")))]
""
"or %0,%1,%2")
"rot %0,%1,%2"
[(set_attr "type" "bit")])
+(define_insn ""
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+ (match_operand:CC 2 "int5_operand" "")))]
+ ""
+ "rot %0,%1,%2"
+ [(set_attr "type" "bit")])
+
;; rotate/and[.c] and rotate/ior[.c]
(define_split
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_operand:CC 4 "register_operand" "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (ior:CC (match_dup 4) (match_dup 3)))]
+ (ior:CCEVEN (match_dup 4) (match_dup 3)))]
"")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_scratch:CC 4 "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_operand:CC 4 "register_operand" "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (ior:CC (not:CC (match_dup 4)) (match_dup 3)))]
+ (ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
"")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_scratch:CC 4 "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_operand:CC 4 "register_operand" "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (and:CC (match_dup 4) (match_dup 3)))]
+ (and:CCEVEN (match_dup 4) (match_dup 3)))]
"")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" ""))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_scratch:CC 4 "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
(define_split
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_operand:CC 4 "register_operand" "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
""
[(set (match_dup 4)
(rotate:CC (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (and:CC (not:CC (match_dup 4)) (match_dup 3)))]
+ (and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
"")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+ [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+ (and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
(match_operand:CC 2 "int5_operand" "")))
- (match_operand:CC 3 "register_operand" "r")))
- (clobber (match_scratch:CC 4 "=r"))]
+ (match_operand 3 "partial_ccmode_register_operand" "r")))
+ (clobber (match_scratch:CCEVEN 4 "=r"))]
""
"#")
+
\f
;; Recognize bcnd instructions for integer values. This is distinguished
;; from a conditional branch instruction (below) with SImode instead of
operands[3] = op2;
}
if (GET_CODE (operands[3]) == LABEL_REF)
- return \"bcnd%. 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";
+ return \"bcnd 0x5,%1,%3\;bcnd %#ne0,%d1,%3\";
operands[3] = gen_label_rtx ();
label_num = XINT (operands[3], 3);
- output_asm_insn (\"bcnd%. 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
+ output_asm_insn (\"bcnd 0x5,%1,%3\;bcnd %#eq0,%d1,%2\", operands);
output_label (label_num);
return \"\";
}"
- [(set_attr "type" "branch")])
+ [(set_attr "type" "weird")
+ (set_attr "length" "3")])
\f
;; Recognize bb0 and bb1 instructions. These use two unusual template
;; patterns, %Lx and %Px. %Lx outputs a 1 if operand `x' is a LABEL_REF
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 1 "even_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)]))]
+ ""
+ "ext %0,%2,1<%C1>"
+ [(set_attr "type" "bit")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (not:SI (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)])))]
+ ""
+ "ext %0,%2,1<%!%C1>"
+ [(set_attr "type" "bit")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)]))
+ (clobber (match_operand:SI 3 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
+ (set (match_dup 0) (not:SI (match_dup 3)))]
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)]))
+ (clobber (match_scratch:SI 3 "=r"))]
+ ""
+ "#")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI
(match_operator:SI 1 "relop"
[(match_operand:CC 2 "register_operand" "r")
""
"extu %0,%2,1<%C1>"
[(set_attr "type" "bit")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI
+ (match_operator:SI 1 "even_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)])))]
+ ""
+ "extu %0,%2,1<%C1>"
+ [(set_attr "type" "bit")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI
+ (not:SI (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)]))))]
+ ""
+ "extu %0,%2,1<%!%C1>"
+ [(set_attr "type" "bit")])
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_operand:SI 3 "register_operand" "=r"))]
+ ""
+ [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
+ (const_int 0)]))))
+ (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
+ "")
+
+(define_insn
+ ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (neg:SI (match_operator:SI 1 "odd_relop"
+ [(match_operand:CCEVEN 2 "register_operand" "r")
+ (const_int 0)])))
+ (clobber (match_scratch:SI 3 "=r"))]
+ ""
+ "#")
+
+
+
\f
;; Conditional branch insns. The compare insns set a register
;; rather than cc0 and record that register for use here. See above
}"
[(set_attr "type" "branch")])
+;;
+;; Here branch prediction is sacrificed. To get it back, you need
+;; - CCODD (CC mode where the ODD bits are valid)
+;; - several define_split that can apply De Morgan's Law.
+;; - transformations between CCEVEN and CCODD modes.
+;;
+
+(define_insn ""
+ [(set (pc) (if_then_else
+ (match_operator 0 "even_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L2%. %C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
+(define_insn ""
+ [(set (pc) (if_then_else
+ (match_operator 0 "odd_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L3%. %!%C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
;; Branch conditional on scc values. These arise from manipulations on
;; compare words above.
+;; Are these really used ?
(define_insn ""
[(set (pc)
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
- "bb1%. %R3%C0,%1,%P2%P3"
+ "bb%L2 %C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else
+ (ne (match_operator 0 "even_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (const_int 0))
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L2 %C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else
+ (ne (match_operator 0 "odd_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (const_int 0))
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L3 %!%C0,%1,%P2%P3"
[(set_attr "type" "branch")])
(define_insn ""
(match_operand 2 "pc_or_label_ref" "")
(match_operand 3 "pc_or_label_ref" "")))]
""
- "bb0%. %R3%C0,%1,%P2%P3"
+ "bb%L3 %C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else
+ (eq (match_operator 0 "even_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (const_int 0))
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L3 %C0,%1,%P2%P3"
+ [(set_attr "type" "branch")])
+
+(define_insn ""
+ [(set (pc)
+ (if_then_else
+ (eq (match_operator 0 "odd_relop"
+ [(match_operand:CCEVEN 1 "register_operand" "r")
+ (const_int 0)])
+ (const_int 0))
+ (match_operand 2 "pc_or_label_ref" "")
+ (match_operand 3 "pc_or_label_ref" "")))]
+ ""
+ "bb%L2 %!%C0,%1,%P2%P3"
[(set_attr "type" "branch")])
\f
(define_insn "locate1"
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%1
- %V1ld %0,%1
- %v0st %r1,%0
+ %V1ld\\t %0,%1
+ %v0st\\t %r1,%0
subu %0,%#r0,%n1
set %0,%#r0,%s1
mov.s %0,%1
mov.s %0,%1
mov %0,%1
- %V1ld %0,%1
- %v0st %1,%0"
+ %V1ld\\t %0,%1
+ %v0st\\t %1,%0"
[(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")])
(define_insn ""
""
"or %0,%1,%#lo16(%g2)")
+;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
+;; confuse them with real addresses.
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+ (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
+ ""
+ "or %0,%1,%#lo16(%g2)"
+ ;; Need to set length for this arith insn because operand2
+ ;; is not an "arith_operand".
+ [(set_attr "length" "1")])
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(high:SI (match_operand 1 "" "")))]
""
"or.u %0,%#r0,%#hi16(%g1)")
+;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
+;; confuse them with real addresses.
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
+ ""
+ "or.u %0,%#r0,%#hi16(%g1)"
+ ;; Need to set length for this arith insn because operand2
+ ;; is not an arith_operand.
+ [(set_attr "length" "1")])
+
;; HImode move instructions
(define_expand "movhi"
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%h1
- %V1ld.hu %0,%1
- %v0st.h %r1,%0
+ %V1ld.hu\\t %0,%1
+ %v0st.h\\t %r1,%0
subu %0,%#r0,%H1"
[(set_attr "type" "arith,load,store,arith")])
|| operands[1] == const0_rtx)"
"@
or %0,%#r0,%q1
- %V1ld.bu %0,%1
- %v0st.b %r1,%0
+ %V1ld.bu\\t %0,%1
+ %v0st.b\\t %r1,%0
subu %r0,%#r0,%Q1"
[(set_attr "type" "arith,load,store,arith")])
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
- %V1ld.d %0,%1
- %v0st.d %1,%0
+ %V1ld.d\\t %0,%1
+ %v0st.d\\t %1,%0
mov.d %0,%1
mov.d %0,%1
mov %0,%1
- %V1ld.d %0,%1
- %v0st.d %1,%0"
+ %V1ld.d\\t %0,%1
+ %v0st.d\\t %1,%0"
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
DONE;
}")
+(define_split
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (match_operand:DF 1 "register_operand" "r"))]
+ "reload_completed
+ && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0]))
+ && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))"
+ [(set (match_dup 2) (match_dup 3))
+ (set (match_dup 4) (match_dup 5))]
+ "
+{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
+ operands[3] = operand_subword (operands[1], 0, 0, DFmode);
+ operands[4] = operand_subword (operands[0], 1, 0, DFmode);
+ operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
+
;; @@ This pattern is incomplete and doesn't appear necessary.
;;
;; This pattern forces (set (reg:DF ...) (const_double ...))
; return \"or %0,%#r0,0\;or %d0,%#r0,0\";
; case 1:
; operands[1] = adj_offsettable_operand (operands[0], 4);
-; return \"%v0st %#r0,%0\;st %#r0,%1\";
+; return \"%v0st\\t %#r0,%0\;st %#r0,%1\";
; }
;}")
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
- %V1ld.d %0,%1
- %v0st.d %1,%0
+ %V1ld.d\\t %0,%1
+ %v0st.d\\t %1,%0
mov.d %0,%1
mov.d %0,%1
mov %0,%1
- %V1ld.d %0,%1
- %v0st.d %1,%0"
+ %V1ld.d\\t %0,%1
+ %v0st.d\\t %1,%0"
[(set_attr "type" "marith,loadd,store,mov,mov,mov,loadd,store")])
(define_insn ""
""
"@
or %0,%#r0,%1
- %V1ld %0,%1
- %v0st %r1,%0
+ %V1ld\\t %0,%1
+ %v0st\\t %r1,%0
mov.s %0,%1
mov.s %0,%1
mov %0,%1
- %V1ld %0,%1
- %v0st %r1,%0"
+ %V1ld\\t %0,%1
+ %v0st\\t %r1,%0"
[(set_attr "type" "arith,load,store,mov,mov,mov,load,store")])
(define_insn ""
DONE;
}")
+(define_insn ""
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (match_operand:BLK 1 "memory_operand" "m"))]
+ ""
+ "%V1ld.bu\\t %0,%1"
+ [(set_attr "type" "load")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (match_operand:BLK 1 "memory_operand" "m"))]
+ ""
+ "%V1ld.hu\\t %0,%1"
+ [(set_attr "type" "load")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operand:BLK 1 "memory_operand" "m"))]
+ ""
+ "%V1ld\\t %0,%1"
+ [(set_attr "type" "load")])
+
+(define_insn ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (match_operand:BLK 1 "memory_operand" "m"))]
+ ""
+ "%V1ld.d\\t %0,%1"
+ [(set_attr "type" "loadd")])
+
+(define_insn ""
+ [(set (match_operand:BLK 0 "memory_operand" "=m")
+ (match_operand:QI 1 "register_operand" "r"))]
+ ""
+ "%v0st.b\\t %1,%0"
+ [(set_attr "type" "store")])
+
+(define_insn ""
+ [(set (match_operand:BLK 0 "memory_operand" "=m")
+ (match_operand:HI 1 "register_operand" "r"))]
+ ""
+ "%v0st.h\\t %1,%0"
+ [(set_attr "type" "store")])
+
+(define_insn ""
+ [(set (match_operand:BLK 0 "memory_operand" "=m")
+ (match_operand:SI 1 "register_operand" "r"))]
+ ""
+ "%v0st\\t %1,%0"
+ [(set_attr "type" "store")])
+
+(define_insn ""
+ [(set (match_operand:BLK 0 "memory_operand" "=m")
+ (match_operand:DI 1 "register_operand" "r"))]
+ ""
+ "%v0st.d\\t %1,%0"
+ [(set_attr "type" "store")])
+
;; Call a non-looping block move library function (e.g. __movstrSI96x64).
;; operand 0 is the function name
;; operand 1 is the destination pointer
[(set (reg:SI 3) (minus:SI (match_operand:SI 2 "register_operand" "")
(match_operand:SI 3 "immediate_operand" "")))
(set (match_operand:SI 5 "register_operand" "")
- (match_operand:SI 4 "memory_operand" ""))
+ (match_operand 4 "memory_operand" ""))
(set (reg:SI 2) (minus:SI (match_operand:SI 1 "register_operand" "")
(match_dup 3)))
(set (reg:SI 6) (match_operand:SI 6 "immediate_operand" ""))
"@
mask %0,%1,0xffff
or %0,%#r0,%h1
- %V1ld.hu %0,%1"
+ %V1ld.hu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
(define_expand "zero_extendqihi2"
"@
mask %0,%1,0xff
or %0,%#r0,%q1
- %V1ld.bu %0,%1"
+ %V1ld.bu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
(define_expand "zero_extendqisi2"
"@
mask %0,%1,0xff
or %0,%#r0,%q1
- %V1ld.bu %0,%1"
+ %V1ld.bu\\t %0,%1"
[(set_attr "type" "arith,arith,load")])
\f
;;- sign extension instructions
ext %0,%1,16<0>
or %0,%#r0,%h1
subu %0,%#r0,%H1
- %V1ld.h %0,%1"
+ %V1ld.h\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqihi2"
ext %0,%1,8<0>
or %0,%#r0,%q1
subu %0,%#r0,%Q1
- %V1ld.b %0,%1"
+ %V1ld.b\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqisi2"
ext %0,%1,8<0>
or %0,%#r0,%q1
subu %0,%#r0,%Q1
- %V1ld.b %0,%1"
+ %V1ld.b\\t %0,%1"
[(set_attr "type" "bit,arith,arith,load")])
\f
;; Conversions between float and double.
[(set_attr "type" "spadd,spadd")])
(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r,x")
- (fix:SI (match_operand:DF 1 "register_operand" "r,r")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (fix:SI (match_operand:DF 1 "register_operand" "r,x")))]
""
"trnc.sd %0,%1"
[(set_attr "type" "dpadd,dpadd")])
(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r,x")
- (fix:SI (match_operand:SF 1 "register_operand" "r,r")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+ (fix:SI (match_operand:SF 1 "register_operand" "r,x")))]
""
"trnc.ss %0,%1"
[(set_attr "type" "spadd,dpadd")])
\f
;;- multiply instructions
;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
;; immediate constant value in div/divu/mul instructions be less than
;; 0x800. This is no longer provided for.
;; for divide-by-zero or take your chances. If the div instruction is
;; used, the O/S must complete the operation if the operands are
;; negative. The O/S will signal an overflow condition if the most
-;; negative number (-214783648) is divided by negative 1.
+;; negative number (-2147483648) is divided by negative 1.
;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
;; immediate constant value in div/divu/mul instructions be less than
;; 0x800. This is no longer provided for.
(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 24)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
- "%V1ld.b %0,%1"
+ "%V1ld.b\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 24)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
- "%V1ld.bu %0,%1"
+ "%V1ld.bu\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 16)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
- "%V1ld.h %0,%1"
+ "%V1ld.h\\t %0,%1"
[(set_attr "type" "load")])
(define_insn ""
(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
(const_int 16)))]
"! SCALED_ADDRESS_P (XEXP (operands[1], 0))"
- "%V1ld.hu %0,%1"
+ "%V1ld.hu\\t %0,%1"
[(set_attr "type" "load")])
\f
;;- arithmetic shift instructions.
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ashift:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith5_operand" "r,n")))]
+ (match_operand:SI 2 "arith5_operand" "r,K")))]
""
"@
mak %0,%1,%2
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith5_operand" "r,n")))]
+ (match_operand:SI 2 "arith5_operand" "r,K")))]
""
"@
ext %0,%1,%2
[(set_attr "type" "bit")])
\f
;;- logical shift instructions. Logical shift left becomes arithmetic
-;; shift left. LSHIFT is not normally produced, but is supported.
-
-(define_expand "lshlsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (lshift:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "arith32_operand" "")))]
- ""
- "
-{
- emit_insn (gen_ashlsi3 (operands[0], operands[1], operands[2]));
- DONE;
-}")
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (lshift:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith5_operand" "r,n")))]
- ""
- "@
- mak %0,%1,%2
- mak %0,%1,0<%2>"
- [(set_attr "type" "bit")])
+;; shift left.
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "")
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "arith5_operand" "r,n")))]
+ (match_operand:SI 2 "arith5_operand" "r,K")))]
""
"@
extu %0,%1,%2
emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3]));
else
/* Load the table entry and jump to it. */
- emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff));
+ emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff, operands[3]));
/* Claim that flow drops into the table so it will be adjacent by not
emitting a barrier. */
(mem:SI (plus:SI (match_operand:SI 1 "" "")
(mult:SI (match_operand:SI 2 "" "")
(const_int 4)))))
- (set (pc) (match_dup 0))]
+ (parallel [(set (pc) (match_dup 0))
+ (use (label_ref (match_operand 3 "" "")))])]
""
"")
+(define_insn ""
+ [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+ (use (label_ref (match_operand 1 "" "")))]
+ ""
+ "jmp%. %0"
+ [(set_attr "type" "jump")])
+
;; The bsr.n instruction is directed to the END of the table. See
;; ASM_OUTPUT_CASE_END.
;; reloads, hence the `m' constraints. The `!' constraints direct reload
;; to not choose the register alternatives in the event a reload is needed.
-(define_insn "decrement_and_branch_until_zero"
+(define_expand "decrement_and_branch_until_zero"
+ [(parallel [(set (pc)
+ (if_then_else
+ (match_operator 0 "relop_no_unsigned"
+ [(match_operand:SI 1 "register_operand" "")
+ (const_int 0)])
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (set (match_dup 1)
+ (plus:SI (match_dup 1)
+ (match_operand:SI 3 "add_operand" "")))
+ (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 5 "=X,X,&r,&r"))])]
+ ""
+ "")
+
+(define_insn ""
[(set (pc)
(if_then_else
(match_operator 0 "relop_no_unsigned"
[(set (match_operand 0 "" "") (match_dup 0))]
""
"")
-\f
-;;- Local variables:
-;;- mode:emacs-lisp
-;;- comment-start: ";;- "
-;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
-;;- eval: (modify-syntax-entry ?[ "(]")
-;;- eval: (modify-syntax-entry ?] ")[")
-;;- eval: (modify-syntax-entry ?{ "(}")
-;;- eval: (modify-syntax-entry ?} "){")
-;;- End:
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