if-statements and ?: on it. This way we have compile-time error checking
for both the MOTOROLA and MIT code paths. We do rely on the host compiler
to optimize away all constant tests. */
-#ifdef MOTOROLA
-# undef MOTOROLA
-# define MOTOROLA 1 /* Use the Motorola assembly syntax. */
+#if MOTOROLA /* Use the Motorola assembly syntax. */
# define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
#else
-# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
# define MOTOROLA 0 /* Use the MIT assembly syntax. */
+# define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
#endif
/* Handle --with-cpu default option from configure script. */
%{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
%{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
"
+#define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
+ %{msep-data|mid-shared-library:--pcrel} \
+"
-#define ASM_SPEC "%(asm_cpu_spec)"
+#define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
#define EXTRA_SPECS \
{ "asm_cpu_spec", ASM_CPU_SPEC }, \
+ { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
if (TARGET_CF_HWDIV) \
builtin_define ("__mcfhwdiv__"); \
\
+ if (TARGET_FIDOA) \
+ builtin_define ("__mfido__"); \
+ \
builtin_assert ("cpu=m68k"); \
builtin_assert ("machine=m68k"); \
} \
#define FL_ISA_APLUS (1 << 14)
#define FL_ISA_B (1 << 15)
#define FL_ISA_C (1 << 16)
+#define FL_FIDOA (1 << 17)
#define FL_MMU 0 /* Used by multilib machinery. */
#define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
#define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
#define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
#define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
+#define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
/* Size (in bytes) of FPU registers. */
#define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
\f
/* target machine storage layout */
-/* "long double" is the same as "double" on ColdFire targets. */
+/* "long double" is the same as "double" on ColdFire and fido
+ targets. */
-#define LONG_DOUBLE_TYPE_SIZE (TARGET_COLDFIRE ? 64 : 80)
+#define LONG_DOUBLE_TYPE_SIZE \
+ ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
/* We need to know the size of long double at compile-time in libgcc2. */
-#ifdef __mcoldfire__
+#if defined(__mcoldfire__) || defined(__mfido__)
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#else
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
#define STACK_BOUNDARY 16
#define FUNCTION_BOUNDARY 16
#define EMPTY_FIELD_BOUNDARY 16
+/* ColdFire and fido strongly prefer a 32-bit aligned stack. */
+#define PREFERRED_STACK_BOUNDARY \
+ ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
/* No data type wants to be aligned rounder than this.
- Most published ABIs say that ints should be aligned on 16 bit
+ Most published ABIs say that ints should be aligned on 16-bit
boundaries, but CPUs with 32-bit busses get better performance
aligned on 32-bit boundaries. ColdFires without a misalignment
module require 32-bit alignment. */
/* For the m68k, we give the data registers numbers 0-7,
the address registers numbers 010-017 (8-15),
- and the 68881 floating point registers numbers 020-027 (16-24).
- We also have a fake `arg-pointer' register 030 (25) used for
+ and the 68881 floating point registers numbers 020-027 (16-23).
+ We also have a fake `arg-pointer' register 030 (24) used for
register elimination. */
#define FIRST_PSEUDO_REGISTER 25
/* All m68k targets (except AmigaOS) use %a5 as the PIC register */
-#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
+#define PIC_OFFSET_TABLE_REGNUM \
+ (!flag_pic ? INVALID_REGNUM \
+ : reload_completed ? REGNO (pic_offset_table_rtx) \
+ : PIC_REG)
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
if (TEST_HARD_REG_BIT (x, i)) \
fixed_regs[i] = call_used_regs[i] = 1; \
} \
- if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
- = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ if (flag_pic) \
+ fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \
}
/* On the m68k, ordinary registers hold 32 bits worth;
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
-/* Value is true if hard register REGNO can hold a value of machine-mode MODE.
- On the 68000, the cpu registers can hold any mode except bytes in
- address registers, the 68881 registers can hold only SFmode or DFmode. */
-
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
m68k_regno_mode_ok ((REGNO), (MODE))
+#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
+ m68k_secondary_reload_class (CLASS, MODE, X)
+
#define MODES_TIEABLE_P(MODE1, MODE2) \
(! TARGET_HARD_FLOAT \
|| ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
-#define STACK_POINTER_REGNUM 15
+#define STACK_POINTER_REGNUM SP_REG
/* Most m68k targets use %a6 as a frame pointer. The AmigaOS
ABI uses %a6 for shared library calls, therefore the frame
pointer is shifted to %a5 on this target. */
-#define FRAME_POINTER_REGNUM 14
+#define FRAME_POINTER_REGNUM A6_REG
#define FRAME_POINTER_REQUIRED 0
*/
#define ARG_POINTER_REGNUM 24
-#define STATIC_CHAIN_REGNUM 8
+#define STATIC_CHAIN_REGNUM A0_REG
+#define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
/* Register in which address to store a structure value
is passed to a function. */
-#define M68K_STRUCT_VALUE_REGNUM 9
+#define M68K_STRUCT_VALUE_REGNUM A1_REG
\f
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS ADDR_REGS
-/* We do a trick here to modify the effective constraints on the
- machine description; we zorch the constraint letters that aren't
- appropriate for a specific target. This allows us to guarantee
- that a specific kind of register will not be used for a given target
- without fiddling with the register classes above. */
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'a' ? ADDR_REGS : \
- ((C) == 'd' ? DATA_REGS : \
- ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
- FP_REGS : NO_REGS) : \
- NO_REGS)))
-
-/* For the m68k, `I' is used for the range 1 to 8
- allowed as immediate shift counts and in addq.
- `J' is used for the range of signed numbers that fit in 16 bits.
- `K' is for numbers that moveq can't handle.
- `L' is for range -8 to -1, range of values that can be added with subq.
- `M' is for numbers that moveq+notb can't handle.
- 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
- 'O' is for 16 (for rotate using swap).
- 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
- (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
- (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
- (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
- (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
- (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
- (C) == 'O' ? (VALUE) == 16 : \
- (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
-
-/* "G" defines all of the floating constants that are *NOT* 68881
- constants. This is so 68881 constants get reloaded and the
- fpmovecr is used. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
-
-/* `Q' means address register indirect addressing mode.
- `S' is for operands that satisfy 'm' when -mpcrel is in effect.
- `T' is for operands that satisfy 's' when -mpcrel is not in effect.
- `U' is for register offset addressing. */
-#define EXTRA_CONSTRAINT(OP,CODE) \
- (((CODE) == 'S') \
- ? (TARGET_PCREL \
- && GET_CODE (OP) == MEM \
- && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
- || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
- || GET_CODE (XEXP (OP, 0)) == CONST)) \
- : \
- (((CODE) == 'T') \
- ? ( !TARGET_PCREL \
- && (GET_CODE (OP) == SYMBOL_REF \
- || GET_CODE (OP) == LABEL_REF \
- || GET_CODE (OP) == CONST)) \
- : \
- (((CODE) == 'Q') \
- ? (GET_CODE (OP) == MEM \
- && GET_CODE (XEXP (OP, 0)) == REG) \
- : \
- (((CODE) == 'U') \
- ? (GET_CODE (OP) == MEM \
- && GET_CODE (XEXP (OP, 0)) == PLUS \
- && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
- && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
- : \
- 0))))
-
-/* On the m68k, use a data reg if possible when the
- value is a constant in the range where moveq could be used
- and we ensure that QImodes are reloaded into data regs. */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) \
- ((GET_CODE (X) == CONST_INT \
- && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
- && (CLASS) != ADDR_REGS) \
- ? DATA_REGS \
- : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
- ? DATA_REGS \
- : (GET_CODE (X) == CONST_DOUBLE \
- && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
- ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
- ? FP_REGS : NO_REGS) \
- : (TARGET_PCREL \
- && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
- || GET_CODE (X) == LABEL_REF)) \
- ? ADDR_REGS \
- : (CLASS))
-
-/* Force QImode output reloads from subregs to be allocated to data regs,
- since QImode stores from address regs are not supported. We make the
- assumption that if the class is not ADDR_REGS, then it must be a superset
- of DATA_REGS. */
-#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
- (((MODE) == QImode && (CLASS) != ADDR_REGS) \
- ? DATA_REGS \
- : (CLASS))
+#define PREFERRED_RELOAD_CLASS(X,CLASS) \
+ m68k_preferred_reload_class (X, CLASS)
/* On the m68k, this is the size of MODE in words,
except in the FP regs, where a single reg is always enough. */
/* Moves between fp regs and other regs are two insns. */
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
- || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
- ? 4 : 2)
+ ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
\f
/* Stack layout; function entry, exit and calling. */
-#define STACK_GROWS_DOWNWARD
+#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
#define STARTING_FRAME_OFFSET 0
== void_type_node))) \
? (SIZE) : 0)
-/* On the m68k the return value is always in D0. */
+/* On the m68k the return value defaults to D0. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
+ gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
-/* On the m68k the return value is always in D0. */
-#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
+/* On the m68k the return value defaults to D0. */
+#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
-/* On the m68k, D0 is the only register used. */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
+/* On the m68k, D0 is usually the only register used. */
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
/* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
more than one register.
XXX This macro is m68k specific and used only for m68kemb.h. */
#define NEEDS_UNTYPED_CALL 0
-#define PCC_STATIC_STRUCT_RETURN
-
/* On the m68k, all arguments are usually pushed on the stack. */
#define FUNCTION_ARG_REGNO_P(N) 0
\f
#define EXIT_IGNORE_STACK 1
-/* Determine if the epilogue should be output as RTL.
- You should override this if you define FUNCTION_EXTRA_EPILOGUE.
-
- XXX This macro is m68k-specific and only used in m68k.md. */
-#define USE_RETURN_INSN use_return_insn ()
-
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
jmp FNADDR */
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
- emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
+ emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
+ GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
GEN_INT(0x4EF9)); \
void \
__transfer_from_trampoline () \
{ \
- register char *a0 asm ("%a0"); \
+ register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
asm (GLOBAL_ASM_OP "___trampoline"); \
asm ("___trampoline:"); \
asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
/* Macros to check register numbers against specific register classes. */
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
-((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-(((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
-#define REGNO_OK_FOR_DATA_P(REGNO) \
-((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
-#define REGNO_OK_FOR_FP_P(REGNO) \
-(((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
+/* True for data registers, D0 through D7. */
+#define DATA_REGNO_P(REGNO) ((unsigned int) (REGNO) < 8)
+
+/* True for address registers, A0 through A7. */
+#define ADDRESS_REGNO_P(REGNO) (((unsigned int) (REGNO) - 8) < 8)
+
+/* True for integer registers, D0 through D7 and A0 through A7. */
+#define INT_REGNO_P(REGNO) ((unsigned int) (REGNO) < 16)
+
+/* True for floating point registers, FP0 through FP7. */
+#define FP_REGNO_P(REGNO) (((unsigned int) (REGNO) - 16) < 8)
+
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+ (INT_REGNO_P (REGNO) \
+ || INT_REGNO_P (reg_renumber[REGNO]))
+
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+ (ADDRESS_REGNO_P (REGNO) \
+ || ADDRESS_REGNO_P (reg_renumber[REGNO]))
+
+#define REGNO_OK_FOR_DATA_P(REGNO) \
+ (DATA_REGNO_P (REGNO) \
+ || DATA_REGNO_P (reg_renumber[REGNO]))
+
+#define REGNO_OK_FOR_FP_P(REGNO) \
+ (FP_REGNO_P (REGNO) \
+ || FP_REGNO_P (reg_renumber[REGNO]))
/* Now macros that check whether X is a register and also,
strictly, whether it is in a specified class.
/* 1 if X is an address register */
#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
\f
+/* True if SYMBOL + OFFSET constants must refer to something within
+ SYMBOL's section. */
+#ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
+#define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
+#endif
#define MAX_REGS_PER_ADDRESS 2
-#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
+#define CONSTANT_ADDRESS_P(X) \
+ ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
+ || GET_CODE (X) == HIGH) \
+ && LEGITIMATE_CONSTANT_P (X))
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
-#define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
+#define LEGITIMATE_CONSTANT_P(X) \
+ (GET_MODE (X) != XFmode \
+ && !m68k_illegitimate_symbolic_constant_p (X))
#ifndef REG_OK_STRICT
-#define PCREL_GENERAL_OPERAND_OK 0
+#define REG_STRICT_P 0
#else
-#define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
+#define REG_STRICT_P 1
#endif
-#define LEGITIMATE_PIC_OPERAND_P(X) \
- (! symbolic_operand (X, VOIDmode) \
- || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
- || PCREL_GENERAL_OPERAND_OK)
+#define LEGITIMATE_PIC_OPERAND_P(X) \
+ (!symbolic_operand (X, VOIDmode) \
+ || (TARGET_PCREL && REG_STRICT_P))
-#ifndef REG_OK_STRICT
-
-/* Nonzero if X is a hard reg that can be used as an index
- or if it is a pseudo reg. */
-#define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
-/* Nonzero if X is a hard reg that can be used as a base reg
- or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
+#define REG_OK_FOR_BASE_P(X) \
+ m68k_legitimate_base_reg_p (X, REG_STRICT_P)
-#else
+#define REG_OK_FOR_INDEX_P(X) \
+ m68k_legitimate_index_reg_p (X, REG_STRICT_P)
-/* Nonzero if X is a hard reg that can be used as an index. */
-#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
-/* Nonzero if X is a hard reg that can be used as a base reg. */
-#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
-
-#endif
-\f
-/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
- that is a valid memory address for an instruction.
- The MODE argument is the machine mode for the MEM expression
- that wants to use this address.
-
- When generating PIC, an address involving a SYMBOL_REF is legitimate
- if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
- We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
- and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
-
- Likewise for a LABEL_REF when generating PIC.
-
- The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
-
-/* Allow SUBREG everywhere we allow REG. This results in better code. It
- also makes function inlining work when inline functions are called with
- arguments that are SUBREGs. */
-
-#define LEGITIMATE_BASE_REG_P(X) \
- ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
- || (GET_CODE (X) == SUBREG \
- && GET_CODE (SUBREG_REG (X)) == REG \
- && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
-
-#define INDIRECTABLE_1_ADDRESS_P(X) \
- ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
- || LEGITIMATE_BASE_REG_P (X) \
- || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
- && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
- || (GET_CODE (X) == PLUS \
- && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
- && (TARGET_68020 \
- || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
- || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
- && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
- || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
- && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
-
-#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
-{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
-
-/* Only labels on dispatch tables are valid for indexing from. */
-#define GO_IF_INDEXABLE_BASE(X, ADDR) \
-{ rtx temp; \
- if (GET_CODE (X) == LABEL_REF \
- && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
- && GET_CODE (temp) == JUMP_INSN \
- && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
- || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
- goto ADDR; \
- if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
-
-#define GO_IF_INDEXING(X, ADDR) \
-{ if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
- { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
- if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
- { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
-
-#define GO_IF_INDEXED_ADDRESS(X, ADDR) \
-{ GO_IF_INDEXING (X, ADDR); \
- if (GET_CODE (X) == PLUS) \
- { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
- && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
- { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
- if (GET_CODE (XEXP (X, 0)) == CONST_INT \
- && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
- { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
-
-/* ColdFire/5200 does not allow HImode index registers. */
-#define LEGITIMATE_INDEX_REG_P(X) \
- ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
- || (! TARGET_COLDFIRE \
- && GET_CODE (X) == SIGN_EXTEND \
- && GET_CODE (XEXP (X, 0)) == REG \
- && GET_MODE (XEXP (X, 0)) == HImode \
- && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
- || (GET_CODE (X) == SUBREG \
- && GET_CODE (SUBREG_REG (X)) == REG \
- && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
-
-#define LEGITIMATE_INDEX_P(X) \
- (LEGITIMATE_INDEX_REG_P (X) \
- || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
- && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
- && (INTVAL (XEXP (X, 1)) == 2 \
- || INTVAL (XEXP (X, 1)) == 4 \
- || (INTVAL (XEXP (X, 1)) == 8 \
- && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
-
-/* Coldfire FPU only accepts addressing modes 2-5 */
-#define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ if (LEGITIMATE_BASE_REG_P (X) \
- || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
- && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
- || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
- && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
- && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
- goto ADDR;}
-
-/* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
+ do \
{ \
- GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
+ if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \
+ goto ADDR; \
} \
- else \
- { \
- GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
- GO_IF_INDEXED_ADDRESS (X, ADDR); \
- if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
- && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
- && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
- goto ADDR; \
- }}
+ while (0)
/* Don't call memory_address_noforce for the address to fetch
- the switch offset. This address is ok as it stands (see above),
+ the switch offset. This address is ok as it stands,
but memory_address_noforce would alter it. */
#define PIC_CASE_VECTOR_ADDRESS(index) index
\f
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+/* The ColdFire FF1 instruction returns 32 for zero. */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
+
#define STORE_FLAG_VALUE (-1)
#define Pmode SImode
We don't replace %fp for targets that don't map it to %a6
since it may confuse GAS. */
#define M68K_REGNAME(r) ( \
- ((FRAME_POINTER_REGNUM == 14) \
+ ((FRAME_POINTER_REGNUM == A6_REG) \
&& ((r) == FRAME_POINTER_REGNUM) \
&& frame_pointer_needed) ? \
M68K_FP_REG_NAME : reg_names[(r)])
/* We must not use the DBX register numbers for the DWARF 2 CFA column
numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
Instead use the identity mapping. */
-#define DWARF_FRAME_REGNUM(REG) REG
+#define DWARF_FRAME_REGNUM(REG) \
+ (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
+
+/* The return column was originally 24, but gcc used 25 for a while too.
+ Define both registers 24 and 25 as Pmode ones and use 24 in our own
+ unwind information. */
+#define DWARF_FRAME_REGISTERS 25
+#define DWARF_FRAME_RETURN_COLUMN 24
+#define DWARF_ALT_FRAME_RETURN_COLUMN 25
/* Before the prologue, the top of the frame is at 4(%sp). */
#define INCOMING_FRAME_SP_OFFSET 4
+/* All registers are live on exit from an interrupt routine. */
+#define EPILOGUE_USES(REGNO) \
+ (reload_completed \
+ && (m68k_get_function_kind (current_function_decl) \
+ == m68k_fk_interrupt_handler))
+
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) \
((N) < 2 ? (N) : INVALID_REGNUM)
-#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
#define EH_RETURN_HANDLER_RTX \
gen_rtx_MEM (Pmode, \
gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
#define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
-#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
- asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
-#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
- asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
+#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
+ asm_fprintf (FILE, (MOTOROLA \
+ ? "\tmove.l %s,-(%Rsp)\n" \
+ : "\tmovel %s,%Rsp@-\n"), \
+ reg_names[REGNO])
+
+#define ASM_OUTPUT_REG_POP(FILE,REGNO) \
+ asm_fprintf (FILE, (MOTOROLA \
+ ? "\tmove.l (%Rsp)+,%s\n" \
+ : "\tmovel %Rsp@+,%s\n"), \
+ reg_names[REGNO])
/* The m68k does not use absolute case-vectors, but we must define this macro
anyway. */
'$' for the letter `s' in an op code, but only on the 68040.
'&' for the letter `d' in an op code, but only on the 68040.
'/' for register prefix needed by longlong.h.
+ '?' for m68k_library_id_string
'b' for byte insn (no effect, on the Sun; this is for the ISI).
'd' to force memory addressing to be absolute, not relative.
'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
- 'o' for operands to go directly to output_operand_address (bypassing
- print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
or print pair of registers as rx:ry. */
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
|| (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
- || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
+ || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?')
/* See m68k.c for the m68k specific codes. */
FPUTYPE_COLDFIRE
};
+enum m68k_function_kind
+{
+ m68k_fk_normal_function,
+ m68k_fk_interrupt_handler,
+ m68k_fk_interrupt_thread
+};
+
/* Variables in m68k.c; see there for details. */
extern const char *m68k_library_id_string;
extern int m68k_last_compare_had_fp_operands;
extern enum uarch_type m68k_tune;
extern enum fpu_type m68k_fpu;
extern unsigned int m68k_cpu_flags;
+extern const char *m68k_symbolic_call;
+extern const char *m68k_symbolic_jump;