Replace no_new_pseudos in backends.

[pf3gnuchains/gcc-fork.git] / gcc / config / m32c / bitops.md

diff --git a/gcc/config/m32c/bitops.md b/gcc/config/m32c/bitops.md
index e7823b9..33a7058 100644 (file)
--- a/gcc/config/m32c/bitops.md
+++ b/gcc/config/m32c/bitops.md
@@ -31,7 +31,7 @@
 ; On the M32C, "address" for bit instructions is a regular address,
 ; and the bit number is stored in a separate field.  Thus, we can let
 ; gcc do more interesting things.  However, the M32C cannot set all
-; the bits in a 16 bit register, which the R8C/M16C can do.
+; the bits in a 16-bit register, which the R8C/M16C can do.
 
 ; However, it all means that we end up with two sets of patterns, one
 ; for each chip.
@@ -47,7 +47,7 @@
                (match_operand:QI 2 "" "0")))]
   "TARGET_A16"
   "bset\t%0[%1]"
-  [(set_attr "flags" "sz")]
+  [(set_attr "flags" "n")]
   )  
 
 (define_insn "bset_hi"
@@ -57,7 +57,7 @@
        (const_int 1))]
   "TARGET_A16"
   "bset\t%0[%1]"
-  [(set_attr "flags" "sz")]
+  [(set_attr "flags" "n")]
   )  
 
 ;;----------------------------------------------------------------------
@@ -73,7 +73,7 @@
        (const_int 0))]
   "TARGET_A16"
   "bclr\t%0[%1]"
-  [(set_attr "flags" "sz")]
+  [(set_attr "flags" "n")]
   )  
 
 
@@ -113,6 +113,33 @@
   [(set_attr "flags" "n,n,n,sz,sz,sz,sz")]
   )
 
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (and:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"and.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"and.w %X2,%H0\";
+    case 1:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"and.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"and.w %X2,%H0\";
+    case 3:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 4:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    case 5:
+      return \"and.w %h2,%h0\;and.w %H2,%H0\";
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
 
 
 (define_insn "iorqi3_16"
@@ -183,18 +210,17 @@
 
 
 (define_insn "iorqi3_24"
-  [(set (match_operand:QI 0 "mra_operand" "=Sd,Rqi,RqiSd,??Rmm,RqiSd,??Rmm")
-       (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0,0")
-               (match_operand:QI 2 "mrai_operand" "Ilb,Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
+  [(set (match_operand:QI 0 "mra_operand" "=RqiSd,RqiSd,??Rmm,RqiSd,??Rmm")
+       (ior:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0,0")
+               (match_operand:QI 2 "mrai_operand" "Ilb,iRhlSd,iRhlSd,?Rmm,?Rmm")))]
   "TARGET_A24"
   "@
    bset\t%B2,%0
-   bset\t%B2,%0
    or.b\t%x2,%0
    or.b\t%x2,%0
    or.b\t%x2,%0
    or.b\t%x2,%0"
-  [(set_attr "flags" "n,n,sz,sz,sz,sz")]
+  [(set_attr "flags" "n,sz,sz,sz,sz")]
   )
 
 (define_insn "iorhi3_24"
@@ -265,6 +291,34 @@
    DONE;"
   )
 
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (ior:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"or.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"or.w %X2,%H0\";
+    case 1:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"or.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"or.w %X2,%H0\";
+    case 3:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 4:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    case 5:
+      return \"or.w %h2,%h0\;or.w %H2,%H0\";
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
 (define_insn "xorqi3"
   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,RhlSd,??Rmm,??Rmm")
        (xor:QI (match_operand:QI 1 "mra_operand" "%0,0,0,0")
@@ -283,6 +337,34 @@
   [(set_attr "flags" "sz,sz,sz,sz")]
   )
 
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd")
+        (xor:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0")
+                (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))]
+  ""
+  "*
+  switch (which_alternative)
+    {
+    case 0:
+      output_asm_insn (\"xor.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"xor.w %X2,%H0\";
+    case 1:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 2:
+      output_asm_insn (\"xor.w %X2,%h0\",operands);
+      operands[2]= GEN_INT (INTVAL (operands[2]) >> 16);
+      return \"xor.w %X2,%H0\";
+    case 3:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 4:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    case 5:
+      return \"xor.w %h2,%h0\;xor.w %H2,%H0\";
+    }"
+  [(set_attr "flags" "x,x,x,x,x,x")]
+)
+
 (define_insn "one_cmplqi2"
   [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm")
        (not:QI (match_operand:QI 1 "mra_operand" "0,0")))]