* target.h (globalize_decl_name): New.

[pf3gnuchains/gcc-fork.git] / gcc / config / ia64 / vect.md

diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index 3d4669b..94380bf 100644 (file)
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -318,7 +318,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (ashift:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshl<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -327,7 +327,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (ashiftrt:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -336,7 +336,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (lshiftrt:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize>.u %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])