/* Definitions of target machine GNU compiler. IA-64 version.
- Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+ Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
+ Free Software Foundation, Inc.
Contributed by James E. Wilson <wilson@cygnus.com> and
David Mosberger <davidm@hpl.hp.com>.
-This file is part of GNU CC.
+This file is part of GCC.
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
+along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
\f
/* Run-time target specifications */
-/* Define this to be a string constant containing `-D' options to define the
- predefined macros that identify this machine and system. These macros will
- be predefined unless the `-ansi' option is specified. */
-/* ??? This is undefed in svr4.h. */
-#define CPP_PREDEFINES "-Dia64 -Amachine=ia64"
+/* Target CPU builtins. */
+#define TARGET_CPU_CPP_BUILTINS() \
+do { \
+ builtin_assert("cpu=ia64"); \
+ builtin_assert("machine=ia64"); \
+ builtin_define("__ia64"); \
+ builtin_define("__ia64__"); \
+ builtin_define("__itanium__"); \
+ if (TARGET_BIG_ENDIAN) \
+ builtin_define("__BIG_ENDIAN__"); \
+} while (0)
+
+#define EXTRA_SPECS \
+ { "asm_extra", ASM_EXTRA_SPEC },
+
+#define CC1_SPEC "%(cc1_cpu) "
+
+#define ASM_EXTRA_SPEC ""
+
/* This declaration should be present. */
extern int target_flags;
#define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
-#define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
+#define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
#define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
-#define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
+#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
+
+#define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
+
+#define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
-#define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
+#define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
+
+#define MASK_INLINE_SQRT_LAT 0x00002000 /* inline sqrt, min latency. */
+
+#define MASK_INLINE_SQRT_THR 0x00004000 /* inline sqrt, max throughput. */
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
+#define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */
+
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
-#define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
+#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
+
+#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
+
+#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
+
+#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
+
+#define TARGET_INLINE_FLOAT_DIV \
+ (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
-#define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
+#define TARGET_INLINE_INT_DIV \
+ (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
-#define TARGET_INLINE_DIV \
- (target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
+#define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
+
+#define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
+
+#define TARGET_INLINE_SQRT \
+ (target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
+/* If the assembler supports thread-local storage, assume that the
+ system does as well. If a particular target system has an
+ assembler that supports TLS -- but the rest of the system does not
+ support TLS -- that system should explicit define TARGET_HAVE_TLS
+ to false in its own configuration file. */
+#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS)
+#define TARGET_HAVE_TLS true
+#endif
+
+extern int ia64_tls_size;
+#define TARGET_TLS14 (ia64_tls_size == 14)
+#define TARGET_TLS22 (ia64_tls_size == 22)
+#define TARGET_TLS64 (ia64_tls_size == 64)
+#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
+
+#define TARGET_HPUX 0
+#define TARGET_HPUX_LD 0
+
+#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
+#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
+#endif
+
/* This macro defines names of command options to set and clear bits in
`target_flags'. Its definition is an initializer with a subgrouping for
each command option. */
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
- { "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
- N_("Generate inline division, optimize for latency") }, \
- { "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
- N_("Generate inline division, optimize for throughput") }, \
+ { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
+ N_("Generate inline floating point division, optimize for latency") },\
+ { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
+ N_("Generate inline floating point division, optimize for throughput") },\
+ { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
+ N_("Generate inline integer division, optimize for latency") }, \
+ { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
+ N_("Generate inline integer division, optimize for throughput") },\
+ { "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
+ N_("Generate inline square root, optimize for latency") }, \
+ { "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
+ N_("Generate inline square root, optimize for throughput") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
+ { "early-stop-bits", MASK_EARLY_STOP_BITS, \
+ N_("Enable earlier placing stop bits for better scheduling")}, \
+ { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
+ N_("Disable earlier placing stop bits")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
subgrouping for each command option. */
extern const char *ia64_fixed_range_string;
+extern const char *ia64_tls_size_string;
+
+/* Which processor to schedule for. The cpu attribute defines a list
+ that mirrors this list, so changes to i64.md must be made at the
+ same time. */
+
+enum processor_type
+{
+ PROCESSOR_ITANIUM, /* Original Itanium. */
+ PROCESSOR_ITANIUM2,
+ PROCESSOR_max
+};
+
+extern enum processor_type ia64_tune;
+
+extern const char *ia64_tune_string;
+
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
- N_("Specify range of registers to make fixed.")}, \
+ N_("Specify range of registers to make fixed"), 0}, \
+ { "tls-size=", &ia64_tls_size_string, \
+ N_("Specify bit size of immediate TLS offsets"), 0}, \
+ { "tune=", &ia64_tune_string, \
+ N_("Schedule code for given CPU"), 0}, \
}
-/* This macro is a C statement to print on `stderr' a string describing the
- particular machine description choice. */
-
-#define TARGET_VERSION fprintf (stderr, " (IA-64)");
-
/* Sometimes certain combinations of command options do not make sense on a
particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
take account of this. This macro, if defined, is executed once just after
\f
/* Driver configuration */
-/* A C string constant that tells the GNU CC driver program options to pass to
- CPP. It can also specify how to translate options you give to GNU CC into
- options for GNU CC to pass to the CPP. */
-
-/* ??? __LONG_MAX__ depends on LP64/ILP32 switch. */
-/* ??? An alternative is to modify glimits.h to check for __LP64__ instead
- of checked for CPU specific defines. We could also get rid of all LONG_MAX
- defines in other tm.h files. */
-#define CPP_SPEC \
- "%{mcpu=itanium:-D__itanium__} %{mbig-endian:-D__BIG_ENDIAN__} \
- -D__LONG_MAX__=9223372036854775807L"
-
-/* If this macro is defined, the preprocessor will not define the builtin macro
- `__SIZE_TYPE__'. The macro `__SIZE_TYPE__' must then be defined by
- `CPP_SPEC' instead.
-
- This should be defined if `SIZE_TYPE' depends on target dependent flags
- which are not accessible to the preprocessor. Otherwise, it should not be
- defined. */
-/* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
-/* #define NO_BUILTIN_SIZE_TYPE */
-
-/* If this macro is defined, the preprocessor will not define the builtin macro
- `__PTRDIFF_TYPE__'. The macro `__PTRDIFF_TYPE__' must then be defined by
- `CPP_SPEC' instead.
-
- This should be defined if `PTRDIFF_TYPE' depends on target dependent flags
- which are not accessible to the preprocessor. Otherwise, it should not be
- defined. */
-/* This is always "long" so it doesn't "change" in ILP32 vs. LP64. */
-/* #define NO_BUILTIN_PTRDIFF_TYPE */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
- `cc1'. It can also specify how to translate options you give to GNU CC into
- options for GNU CC to pass to the `cc1'. */
+/* A C string constant that tells the GCC driver program options to pass to
+ `cc1'. It can also specify how to translate options you give to GCC into
+ options for GCC to pass to the `cc1'. */
#undef CC1_SPEC
#define CC1_SPEC "%{G*}"
-/* A C string constant that tells the GNU CC driver program options to pass to
- `cc1plus'. It can also specify how to translate options you give to GNU CC
- into options for GNU CC to pass to the `cc1plus'. */
+/* A C string constant that tells the GCC driver program options to pass to
+ `cc1plus'. It can also specify how to translate options you give to GCC
+ into options for GCC to pass to the `cc1plus'. */
/* #define CC1PLUS_SPEC "" */
-
-/* A C string constant that tells the GNU CC driver program options to pass to
- the assembler. It can also specify how to translate options you give to GNU
- CC into options for GNU CC to pass to the assembler. */
-
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GNU_AS) != 0
-/* GNU AS. */
-#define ASM_SPEC \
- "%{mno-gnu-as:-N so} %{!mno-gnu-as:-x} %{mconstant-gp} %{mauto-pic}"
-#else
-/* Intel ias. */
-#define ASM_SPEC \
- "%{!mgnu-as:-N so} %{mgnu-as:-x} %{mconstant-gp:-M const_gp}\
- %{mauto-pic:-M no_plabel}"
-#endif
-
-/* A C string constant that tells the GNU CC driver program options to pass to
- the linker. It can also specify how to translate options you give to GNU CC
- into options for GNU CC to pass to the linker. */
-
-/* The Intel linker does not support dynamic linking, so we need -dn.
- The Intel linker gives annoying messages unless -N so is used. */
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GNU_LD) != 0
-/* GNU LD. */
-#define LINK_SPEC "%{mno-gnu-ld:-dn -N so}"
-#else
-/* Intel ild. */
-#define LINK_SPEC "%{!mgnu-ld:-dn -N so}"
-#endif
-
\f
/* Storage Layout */
#define BITS_BIG_ENDIAN 0
-/* Define this macro to have the value 1 if the most significant byte in a word
- has the lowest number. This macro need not be a constant. */
-
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
/* Define this macro to have the value 1 if, in a multiword object, the most
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-/* Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a
- constant value with the same meaning as WORDS_BIG_ENDIAN, which will be used
- only when compiling libgcc2.c. Typically the value will be set based on
- preprocessor defines. */
#if defined(__BIG_ENDIAN__)
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#endif
-/* Define this macro to be the number of bits in an addressable storage unit
- (byte); normally 8. */
-#define BITS_PER_UNIT 8
-
-/* Number of bits in a word; normally 32. */
-#define BITS_PER_WORD 64
-
-/* Number of storage units in a word; normally 4. */
#define UNITS_PER_WORD 8
-/* Width of a pointer, in bits. You must specify a value no wider than the
- width of `Pmode'. If it is not equal to the width of `Pmode', you must
- define `POINTERS_EXTEND_UNSIGNED'. */
#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64)
/* A C expression whose value is zero if pointers that need to be extended
from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if
- they are zero-extended and negative one if there is an ptr_extend operation.
+ they are zero-extended and negative one if there is a ptr_extend operation.
You need not define this macro if the `POINTER_SIZE' is equal to the width
of `Pmode'. */
} \
while (0)
-/* Define this macro if the promotion described by `PROMOTE_MODE' should also
- be done for outgoing function arguments. */
-/* ??? ABI doesn't allow us to define this. */
-/* #define PROMOTE_FUNCTION_ARGS */
-
-/* Define this macro if the promotion described by `PROMOTE_MODE' should also
- be done for the return value of functions.
-
- If this macro is defined, `FUNCTION_VALUE' must perform the same promotions
- done by `PROMOTE_MODE'. */
-/* ??? ABI doesn't allow us to define this. */
-/* #define PROMOTE_FUNCTION_RETURN */
-
-/* Normal alignment required for function parameters on the stack, in bits.
- All stack parameters receive at least this much alignment regardless of data
- type. On most machines, this is the same as the size of an integer. */
#define PARM_BOUNDARY 64
/* Define this macro if you wish to preserve a certain alignment for the stack
#define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15)
#endif
-/* Alignment required for a function entry point, in bits. */
#define FUNCTION_BOUNDARY 128
-/* Biggest alignment that any data type can require on this machine,
- in bits. */
/* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word
128 bit integers all require 128 bit alignment. */
#define BIGGEST_ALIGNMENT 128
(TREE_CODE (EXP) == STRING_CST \
&& (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-/* Define this macro to be the value 1 if instructions will fail to work if
- given data not on the nominal alignment. If instructions will merely go
- slower in that case, define this macro as 0. */
#define STRICT_ALIGNMENT 1
/* Define this if you wish to imitate the way many other C compilers handle
alignment of bitfields and the structures that contain them.
- The behavior is that the type written for a bitfield (`int', `short', or
+ The behavior is that the type written for a bit-field (`int', `short', or
other integer type) imposes an alignment for the entire structure, as if the
structure really did contain an ordinary field of that type. In addition,
- the bitfield is placed within the structure so that it would fit within such
+ the bit-field is placed within the structure so that it would fit within such
a field, not crossing a boundary for it. */
#define PCC_BITFIELD_TYPE_MATTERS 1
/* Allow pairs of registers to be used, which is the intent of the default. */
#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
-/* A code distinguishing the floating point format of the target machine. */
-#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
-
+/* By default, the C++ compiler will use function addresses in the
+ vtable entries. Setting this nonzero tells the compiler to use
+ function descriptors instead. The value of this macro says how
+ many words wide the descriptor is (normally 2). It is assumed
+ that the address of a function descriptor may be treated as a
+ pointer to a function.
+
+ For reasons known only to HP, the vtable entries (as opposed to
+ normal function descriptors) are 16 bytes wide in 32-bit mode as
+ well, even though the 3rd and 4th words are unused. */
+#define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2)
+
+/* Due to silliness in the HPUX linker, vtable entries must be
+ 8-byte aligned even in 32-bit mode. Rather than create multiple
+ ABIs, force this restriction on everyone else too. */
+#define TARGET_VTABLE_ENTRY_ALIGN 64
+
+/* Due to the above, we need extra padding for the data entries below 0
+ to retain the alignment of the descriptors. */
+#define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1)
\f
/* Layout of Source Language Data Types */
-/* A C expression for the size in bits of the type `int' on the target machine.
- If you don't define this, the default is one word. */
#define INT_TYPE_SIZE 32
-/* A C expression for the size in bits of the type `short' on the target
- machine. If you don't define this, the default is half a word. (If this
- would be less than one storage unit, it is rounded up to one unit.) */
#define SHORT_TYPE_SIZE 16
-/* A C expression for the size in bits of the type `long' on the target
- machine. If you don't define this, the default is one word. */
#define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64)
-/* Maximum number for the size in bits of the type `long' on the target
- machine. If this is undefined, the default is `LONG_TYPE_SIZE'. Otherwise,
- it is the constant value that is the largest value that `LONG_TYPE_SIZE' can
- have at run-time. This is used in `cpp'. */
#define MAX_LONG_TYPE_SIZE 64
-/* A C expression for the size in bits of the type `long long' on the target
- machine. If you don't define this, the default is two words. If you want
- to support GNU Ada on your machine, the value of macro must be at least 64. */
#define LONG_LONG_TYPE_SIZE 64
-/* A C expression for the size in bits of the type `char' on the target
- machine. If you don't define this, the default is one quarter of a word.
- (If this would be less than one storage unit, it is rounded up to one unit.) */
-#define CHAR_TYPE_SIZE 8
-
-/* A C expression for the size in bits of the type `float' on the target
- machine. If you don't define this, the default is one word. */
#define FLOAT_TYPE_SIZE 32
-/* A C expression for the size in bits of the type `double' on the target
- machine. If you don't define this, the default is two words. */
#define DOUBLE_TYPE_SIZE 64
-/* A C expression for the size in bits of the type `long double' on the target
- machine. If you don't define this, the default is two words. */
-#define LONG_DOUBLE_TYPE_SIZE 128
-
-/* Tell real.c that this is the 80-bit Intel extended float format
- packaged in a 128-bit entity. */
+/* long double is XFmode normally, TFmode for HPUX. */
+#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96)
-#define INTEL_EXTENDED_IEEE_FORMAT 1
+/* We always want the XFmode operations from libgcc2.c. */
+#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
-/* An expression whose value is 1 or 0, according to whether the type `char'
- should be signed or unsigned by default. The user can always override this
- default with the options `-fsigned-char' and `-funsigned-char'. */
#define DEFAULT_SIGNED_CHAR 1
/* A C expression for a string describing the name of the data type to use for
This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */
/* #define WCHAR_TYPE_SIZE */
-/* Maximum number for the size in bits of the data type for wide characters.
- If this is undefined, the default is `WCHAR_TYPE_SIZE'. Otherwise, it is
- the constant value that is the largest value that `WCHAR_TYPE_SIZE' can have
- at run-time. This is used in `cpp'. */
-/* #define MAX_WCHAR_TYPE_SIZE */
-
\f
/* Register Basics */
-/* Number of hardware registers known to the compiler.
+/* Number of hardware registers known to the compiler.
We have 128 general registers, 128 floating point registers,
64 predicate registers, 8 branch registers, one frame pointer,
and several "application" registers. */
-#define FIRST_PSEUDO_REGISTER 335
+#define FIRST_PSEUDO_REGISTER 334
/* Ranges for the various kinds of registers. */
#define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
#define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
#define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
#define GENERAL_REGNO_P(REGNO) \
- (GR_REGNO_P (REGNO) \
- || (REGNO) == FRAME_POINTER_REGNUM \
- || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
+ (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
#define GR_REG(REGNO) ((REGNO) + 0)
#define FR_REG(REGNO) ((REGNO) + 128)
#define IN_REG(REGNO) ((REGNO) + 112)
#define LOC_REG(REGNO) ((REGNO) + 32)
-#define AR_CCV_REGNUM 330
-#define AR_UNAT_REGNUM 331
-#define AR_PFS_REGNUM 332
-#define AR_LC_REGNUM 333
-#define AR_EC_REGNUM 334
+#define AR_CCV_REGNUM 329
+#define AR_UNAT_REGNUM 330
+#define AR_PFS_REGNUM 331
+#define AR_LC_REGNUM 332
+#define AR_EC_REGNUM 333
#define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
#define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
f0: constant 0.0
f1: constant 1.0
p0: constant true
- fp: eliminable frame pointer */
+ fp: eliminable frame pointer */
/* The last 16 stacked regs are reserved for the 8 input and 8 output
registers. */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, \
- /*FP RA CCV UNAT PFS LC EC */ \
- 1, 1, 1, 1, 1, 0, 1 \
+ /*FP CCV UNAT PFS LC EC */ \
+ 1, 1, 1, 1, 0, 1 \
}
/* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, \
- /*FP RA CCV UNAT PFS LC EC */ \
- 1, 1, 1, 1, 1, 0, 1 \
+ /*FP CCV UNAT PFS LC EC */ \
+ 1, 1, 1, 1, 0, 1 \
}
-/* Like `CALL_USED_REGISTERS' but used to overcome a historical
+/* Like `CALL_USED_REGISTERS' but used to overcome a historical
problem which makes CALL_USED_REGISTERS *always* include
- all the FIXED_REGISTERS. Until this problem has been
+ all the FIXED_REGISTERS. Until this problem has been
resolved this macro can be used to overcome this situation.
- In particular, block_propagate() requires this list
- be acurate, or we can remove registers which should be live.
+ In particular, block_propagate() requires this list
+ be accurate, or we can remove registers which should be live.
This macro is used in regs_invalidated_by_call. */
#define CALL_REALLY_USED_REGISTERS \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Branch registers. */ \
1, 0, 0, 0, 0, 0, 1, 1, \
- /*FP RA CCV UNAT PFS LC EC */ \
- 0, 0, 1, 0, 1, 0, 0 \
+ /*FP CCV UNAT PFS LC EC */ \
+ 0, 1, 0, 1, 0, 0 \
}
#define LOCAL_REGNO(REGNO) \
(IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO))
-/* Add any extra modes needed to represent the condition code.
-
- CCImode is used to mark a single predicate register instead
- of a register pair. This is currently only used in reg_raw_mode
- so that flow doesn't do something stupid. */
-
-#define EXTRA_CC_MODES CC(CCImode, "CCI")
-
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison. Must be defined if
EXTRA_CC_MODES is defined. */
/* Order of allocation of registers */
/* If defined, an initializer for a vector of integers, containing the numbers
- of hard registers in the order in which GNU CC should prefer to use them
+ of hard registers in the order in which GCC should prefer to use them
(from most preferred to least).
If this macro is not defined, registers are used lowest numbered first (all
/* Special branch registers. */ \
R_BR (0), \
/* Other fixed registers. */ \
- FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM, \
+ FRAME_POINTER_REGNUM, \
AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \
AR_EC_REGNUM \
}
((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \
: PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \
: PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \
- : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \
+ : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* A C expression that is nonzero if it is permissible to store a value of mode
GET_MODE_CLASS (MODE) != MODE_CC && \
(MODE) != TImode && \
(MODE) != BImode && \
- ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \
+ (MODE) != TFmode \
: PR_REGNO_P (REGNO) ? \
(MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \
- : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \
+ : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \
: AR_REGNO_P (REGNO) ? (MODE) == DImode \
: BR_REGNO_P (REGNO) ? (MODE) == DImode \
: 0)
ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be
zero. */
/* Don't tie integer and FP modes, as that causes us to get integer registers
- allocated for FP instructions. TFmode only supported in FP registers so
+ allocated for FP instructions. XFmode only supported in FP registers so
we can't tie it with any other modes. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
(GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
- && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \
+ && (((MODE1) == XFmode) == ((MODE2) == XFmode)) \
&& (((MODE1) == BImode) == ((MODE2) == BImode)))
\f
/* Handling Leaf Functions */
NO_REGS,
PR_REGS,
BR_REGS,
+ AR_M_REGS,
+ AR_I_REGS,
ADDL_REGS,
GR_REGS,
FR_REGS,
+ GR_AND_BR_REGS,
GR_AND_FR_REGS,
- AR_M_REGS,
- AR_I_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
/* An initializer containing the names of the register classes as C string
constants. These names are used in writing some of the debugging dumps. */
#define REG_CLASS_NAMES \
-{ "NO_REGS", "PR_REGS", "BR_REGS", "ADDL_REGS", "GR_REGS", "FR_REGS", \
- "GR_AND_FR_REGS", "AR_M_REGS", "AR_I_REGS", "ALL_REGS" }
+{ "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \
+ "ADDL_REGS", "GR_REGS", "FR_REGS", \
+ "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" }
/* An initializer containing the contents of the register classes, as integers
which are bit masks. The Nth integer specifies the contents of class N.
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00FF }, \
+ /* AR_M_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
+ 0x00000000, 0x00000000, 0x0600 }, \
+ /* AR_I_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
+ 0x00000000, 0x00000000, 0x3800 }, \
/* ADDL_REGS. */ \
{ 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
/* GR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00000000, 0x00000000, 0x0300 }, \
+ 0x00000000, 0x00000000, 0x0100 }, \
/* FR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x00000000, 0x00000000, 0x0000 }, \
+ /* GR_AND_BR_REGS. */ \
+ { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
+ 0x00000000, 0x00000000, 0x01FF }, \
/* GR_AND_FR_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
- 0x00000000, 0x00000000, 0x0300 }, \
- /* AR_M_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00000000, 0x00000000, 0x0C00 }, \
- /* AR_I_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
- 0x00000000, 0x00000000, 0x7000 }, \
+ 0x00000000, 0x00000000, 0x0100 }, \
/* ALL_REGS. */ \
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
- 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF }, \
+ 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \
}
/* A C expression whose value is a register class containing hard register
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
(CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \
: CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \
- : GET_RTX_CLASS (GET_CODE (X)) != 'o' && CLASS > GR_AND_FR_REGS ? NO_REGS \
+ : GET_RTX_CLASS (GET_CODE (X)) != 'o' \
+ && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \
: CLASS)
/* You should define this macro to indicate to the reload phase that it may
/* Certain machines have the property that some registers cannot be copied to
some other registers without using memory. Define this macro on those
- machines to be a C expression that is non-zero if objects of mode M in
+ machines to be a C expression that is nonzero if objects of mode M in
registers of CLASS1 can only be copied to registers of class CLASS2 by
storing a register of CLASS1 into memory and loading that memory location
into a register of CLASS2. */
#if 0
-/* ??? May need this, but since we've disallowed TFmode in GR_REGS,
+/* ??? May need this, but since we've disallowed XFmode in GR_REGS,
I'm not quite sure how it could be invoked. The normal problems
with unions should be solved with the addressof fiddling done by
- movtf and friends. */
+ movxf and friends. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
- ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
+ ((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \
|| ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS)))
#endif
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == BImode && (CLASS) == PR_REGS ? 2 \
- : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \
+ : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
-/* If defined, gives a class of registers that cannot be used as the
- operand of a SUBREG that changes the mode of the object illegally. */
-
-#define CLASS_CANNOT_CHANGE_MODE FR_REGS
-
-/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.
- In FP regs, we can't change FP values to integer values and vice
+/* In FP regs, we can't change FP values to integer values and vice
versa, but we can change e.g. DImode to SImode. */
-#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
- (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO))
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \
+ ? reg_classes_intersect_p (CLASS, FR_REGS) : 0)
/* A C expression that defines the machine-dependent operand constraint
letters (`I', `J', `K', .. 'P') that specify particular ranges of
(GET_CODE (VALUE) == MEM \
&& GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \
&& (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
+/* Symbol ref to small-address-area: */
+#define CONSTRAINT_OK_FOR_T(VALUE) \
+ (GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
#define EXTRA_CONSTRAINT(VALUE, C) \
((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \
: (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \
: (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \
+ : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \
: 0)
\f
/* Basic Stack Layout */
DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */
#define RETURN_ADDR_RTX(COUNT, FRAME) \
- ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
+ ia64_return_addr_rtx (COUNT, FRAME)
/* A C expression whose value is RTL representing the location of the incoming
return address at the beginning of any function, before the prologue. This
in it. */
#define ARG_POINTER_REGNUM R_GR(0)
-/* The register number for the return address register. For IA-64, this
- is not actually a pointer as the name suggests, but that's a name that
- gen_rtx_REG already takes care to keep unique. We modify
- return_address_pointer_rtx in ia64_expand_prologue to reference the
- final output regnum. */
-#define RETURN_ADDRESS_POINTER_REGNUM 329
+/* Due to the way varargs and argument spilling happens, the argument
+ pointer is not 16-byte aligned like the stack pointer. */
+#define INIT_EXPANDERS \
+ do { \
+ if (cfun && cfun->emit->regno_pointer_align) \
+ REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \
+ } while (0)
/* Register numbers used for passing a function's static chain pointer. */
/* ??? The ABI sez the static chain should be passed as a normal parameter. */
{ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
- {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)}, \
}
-/* A C expression that returns non-zero if the compiler is allowed to try to
+/* A C expression that returns nonzero if the compiler is allowed to try to
replace register number FROM with register number TO. The frame pointer
is automatically handled. */
\f
/* Passing Function Arguments on the Stack */
-/* Define this macro if an argument declared in a prototype as an integral type
- smaller than `int' should actually be passed as an `int'. In addition to
- avoiding errors in certain cases of mismatch, it also makes for better code
- on certain machines. */
-/* ??? Investigate. */
-/* #define PROMOTE_PROTOTYPES */
-
/* If defined, the maximum amount of space required for outgoing arguments will
be computed and placed into the variable
`current_function_outgoing_args_size'. */
pointer is passed in whatever way is appropriate for passing a pointer to
that type. */
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
+ ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
+
+/* Nonzero if we do not know how to pass TYPE solely in registers. */
+
+#define MUST_PASS_IN_STACK(MODE, TYPE) \
+ ((TYPE) != 0 \
+ && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
+ || TREE_ADDRESSABLE (TYPE)))
/* A C type for declaring a variable that is used as the first argument of
`FUNCTION_ARG' and other related values. For some target machines, the type
typedef struct ia64_args
{
int words; /* # words of arguments so far */
+ int int_regs; /* # GR registers used so far */
int fp_regs; /* # FR registers used so far */
int prototype; /* whether function prototyped */
} CUMULATIVE_ARGS;
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
do { \
(CUM).words = 0; \
+ (CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \
} while (0)
#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
do { \
(CUM).words = 0; \
+ (CUM).int_regs = 0; \
(CUM).fp_regs = 0; \
(CUM).prototype = 1; \
} while (0)
On many machines, no registers can be used for this purpose since all
function arguments are pushed on the stack. */
#define FUNCTION_ARG_REGNO_P(REGNO) \
-(((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
+(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \
|| ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS)))
\f
-/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
- ia64_va_start (stdarg, valist, nextarg)
-
/* Implement `va_arg'. */
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
ia64_va_arg (valist, type)
gen_rtx_REG (MODE, \
(((GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \
- ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \
+ (MODE) != TFmode) \
? FR_RET_FIRST : GR_RET_FIRST))
/* A C expression that is nonzero if REGNO is the number of a hard register in
#define FUNCTION_VALUE_REGNO_P(REGNO) \
(((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \
- || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
+ || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST))
\f
/* How Large Values are Returned */
-/* A nonzero value says to return the function value in memory, just as large
- structures are always returned. */
-
-#define RETURN_IN_MEMORY(TYPE) \
- ia64_return_in_memory (TYPE)
-
-/* If you define this macro to be 0, then the conventions used for structure
- and union return values are decided by the `RETURN_IN_MEMORY' macro. */
-
#define DEFAULT_PCC_STRUCT_RETURN 0
-/* If the structure value address is passed in a register, then
- `STRUCT_VALUE_REGNUM' should be the number of that register. */
-
-#define STRUCT_VALUE_REGNUM GR_REG (8)
-
\f
/* Caller-Saves Register Allocation */
#define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO)
-/* Output at beginning of assembler file. */
-
-#define ASM_FILE_START(FILE) \
- emit_safe_across_calls (FILE)
+/* Nonzero for registers used by the exception handling mechanism. */
-/* A C compound statement that outputs the assembler code for a thunk function,
- used to implement C++ virtual function calls with multiple inheritance. */
+#define EH_USES(REGNO) ia64_eh_uses (REGNO)
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
+/* Output part N of a function descriptor for DECL. For ia64, both
+ words are emitted with a single relocation, so ignore N > 0. */
+#define ASM_OUTPUT_FDESC(FILE, DECL, PART) \
do { \
- if (CONST_OK_FOR_I (DELTA)) \
- fprintf (FILE, "\tadds r32 = %d, r32\n", (DELTA)); \
- else \
+ if ((PART) == 0) \
{ \
- if (CONST_OK_FOR_J (DELTA)) \
- fprintf (FILE, "\taddl r2 = %d, r0\n", (DELTA)); \
+ if (TARGET_ILP32) \
+ fputs ("\tdata8.ua @iplt(", FILE); \
else \
- fprintf (FILE, "\tmovl r2 = %d\n", (DELTA)); \
- fprintf (FILE, "\t;;\n"); \
- fprintf (FILE, "\tadd r32 = r2, r32\n"); \
+ fputs ("\tdata16.ua @iplt(", FILE); \
+ assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \
+ fputs (")\n", FILE); \
+ if (TARGET_ILP32) \
+ fputs ("\tdata8.ua 0\n", FILE); \
} \
- fprintf (FILE, "\tbr "); \
- assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
- fprintf (FILE, "\n"); \
} while (0)
-
\f
/* Generating Code for Profiling. */
/* A C statement or compound statement to output to FILE some assembler code to
call the profiling subroutine `mcount'. */
-/* ??? Unclear if this will actually work. No way to test this currently. */
-
-#define FUNCTION_PROFILER(FILE, LABELNO) \
+#undef FUNCTION_PROFILER
+#define FUNCTION_PROFILER(FILE, LABELNO) \
do { \
char buf[20]; \
ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \
- fputs ("\taddl r16 = @ltoff(", FILE); \
+ fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \
+ if (TARGET_AUTO_PIC) \
+ fputs ("\tmovl out3 = @gprel(", FILE); \
+ else \
+ fputs ("\taddl out3 = @ltoff(", FILE); \
assemble_name (FILE, buf); \
- fputs ("), gp\n", FILE); \
- fputs ("\tmov r17 = r1;;\n", FILE); \
- fputs ("\tld8 out0 = [r16]\n", FILE); \
- fputs ("\tmov r18 = b0\n", FILE); \
- fputs ("\tbr.call.sptk.many rp = mcount;;\n", FILE); \
- fputs ("\tmov b0 = r18\n", FILE); \
- fputs ("\tmov r1 = r17;;\n", FILE); \
-} while (0)
-
-/* A C statement or compound statement to output to FILE some assembler code to
- initialize basic-block profiling for the current object module. */
-
-/* ??? Unclear if this will actually work. No way to test this currently. */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
-do { \
- int labelno = LABELNO; \
- switch (profile_block_flag) \
- { \
- case 2: \
- fputs ("\taddl r16 = @ltoff(LPBX0), gp\n", FILE); \
- fprintf (FILE, "\tmov out1 = %d;;\n", labelno); \
- fputs ("\tld8 out0 = [r16]\n", FILE); \
- fputs ("\tmov r17 = r1\n", FILE); \
- fputs ("\tmov r18 = b0\n", FILE); \
- fputs ("\tbr.call.sptk.many rp = __bb_init_trace_func;;\n", FILE);\
- fputs ("\tmov r1 = r17\n", FILE); \
- fputs ("\tmov b0 = r18;;\n", FILE); \
- break; \
- default: \
- fputs ("\taddl r16 = @ltoff(LPBX0), gp;;\n", FILE); \
- fputs ("\tld8 out0 = [r16];;\n", FILE); \
- fputs ("\tld8 r17 = [out0];;\n", FILE); \
- fputs ("\tcmp.eq p6, p0 = r0, r17;;\n", FILE); \
- fputs ("(p6)\tmov r16 = r1\n", FILE); \
- fputs ("(p6)\tmov r17 = b0\n", FILE); \
- fputs ("(p6)\tbr.call.sptk.many rp = __bb_init_func;;\n", FILE); \
- fputs ("(p6)\tmov r1 = r16\n", FILE); \
- fputs ("(p6)\tmov b0 = r17;;\n", FILE); \
- break; \
- } \
+ if (TARGET_AUTO_PIC) \
+ fputs (");;\n", FILE); \
+ else \
+ fputs ("), r1;;\n", FILE); \
+ fputs ("\tmov out1 = r1\n", FILE); \
+ fputs ("\tmov out2 = b0\n", FILE); \
+ fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \
} while (0)
-
-/* A C statement or compound statement to output to FILE some assembler code to
- increment the count associated with the basic block number BLOCKNO. */
-
-/* ??? This can't work unless we mark some registers as fixed, so that we
- can use them as temporaries in this macro. We need two registers for -a
- profiling and 4 registers for -ax profiling. */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO) \
-do { \
- int blockn = BLOCKNO; \
- switch (profile_block_flag) \
- { \
- case 2: \
- fputs ("\taddl r2 = @ltoff(__bb), gp\n", FILE); \
- fputs ("\taddl r3 = @ltoff(LPBX0), gp;;\n", FILE); \
- fprintf (FILE, "\tmov r9 = %d\n", blockn); \
- fputs ("\tld8 r2 = [r2]\n", FILE); \
- fputs ("\tld8 r3 = [r3];;\n", FILE); \
- fputs ("\tadd r8 = 8, r2\n", FILE); \
- fputs ("\tst8 [r2] = r9;;\n", FILE); \
- fputs ("\tst8 [r8] = r3\n", FILE); \
- fputs ("\tbr.call.sptk.many rp = __bb_trace_func\n", FILE); \
- break; \
- \
- default: \
- fputs ("\taddl r2 = @ltoff(LPBX2), gp;;\n", FILE); \
- fputs ("\tld8 r2 = [r2];;\n", FILE); \
- fprintf (FILE, "\taddl r2 = %d, r2;;\n", 8 * blockn); \
- fputs ("\tld8 r3 = [r2];;\n", FILE); \
- fputs ("\tadd r3 = 1, r3;;\n", FILE); \
- fputs ("\tst8 [r2] = r3;;\n", FILE); \
- break; \
- } \
-} while(0)
-
-/* A C statement or compound statement to output to FILE assembler
- code to call function `__bb_trace_ret'. */
-
-/* ??? Unclear if this will actually work. No way to test this currently. */
-
-/* ??? This needs to be emitted into the epilogue. Perhaps rewrite to emit
- rtl and call from ia64_expand_epilogue? */
-
-#define FUNCTION_BLOCK_PROFILER_EXIT(FILE) \
- fputs ("\tbr.call.sptk.many rp = __bb_trace_ret\n", FILE);
-#undef FUNCTION_BLOCK_PROFILER_EXIT
-
-/* A C statement or compound statement to save all registers, which may be
- clobbered by a function call, including condition codes. */
-
-/* ??? We would have to save 20 GRs, 106 FRs, 10 PRs, 2 BRs, and possibly
- other things. This is not practical. Perhaps leave this feature (-ax)
- unsupported by undefining above macros? */
-
-/* #define MACHINE_STATE_SAVE(ID) */
-
-/* A C statement or compound statement to restore all registers, including
- condition codes, saved by `MACHINE_STATE_SAVE'. */
-
-/* ??? We would have to restore 20 GRs, 106 FRs, 10 PRs, 2 BRs, and possibly
- other things. This is not practical. Perhaps leave this feature (-ax)
- unsupported by undefining above macros? */
-
-/* #define MACHINE_STATE_RESTORE(ID) */
-
-\f
-/* Implementing the Varargs Macros. */
-
-/* Define this macro to store the anonymous register arguments into the stack
- so that all the arguments appear to have been passed consecutively on the
- stack. */
-
-#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \
- ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME)
-
-/* Define this macro if the location where a function argument is passed
- depends on whether or not it is a named argument. */
-
-#define STRICT_ARGUMENT_NAMING 1
-
\f
/* Trampolines for Nested Functions. */
\f
/* Implicit Calls to Library Routines */
-/* Define this macro if GNU CC should generate calls to the System V (and ANSI
+/* Define this macro if GCC should generate calls to the System V (and ANSI
C) library functions `memcpy' and `memset' rather than the BSD functions
`bcopy' and `bzero'. */
\f
/* Describing Relative Costs of Operations */
-/* A part of a C `switch' statement that describes the relative costs of
- constant RTL expressions. */
-
-/* ??? This is incomplete. */
-
-#define CONST_COSTS(X, CODE, OUTER_CODE) \
- case CONST_INT: \
- if ((X) == const0_rtx) \
- return 0; \
- switch (OUTER_CODE) \
- { \
- case SET: \
- return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \
- case PLUS: \
- if (CONST_OK_FOR_I (INTVAL (X))) \
- return 0; \
- if (CONST_OK_FOR_J (INTVAL (X))) \
- return 1; \
- return COSTS_N_INSNS (1); \
- default: \
- if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \
- return 0; \
- return COSTS_N_INSNS (1); \
- } \
- case CONST_DOUBLE: \
- return COSTS_N_INSNS (1); \
- case CONST: \
- case SYMBOL_REF: \
- case LABEL_REF: \
- return COSTS_N_INSNS (3);
-
-/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */
-
-#define RTX_COSTS(X, CODE, OUTER_CODE) \
- case MULT: \
- /* For multiplies wider than HImode, we have to go to the FPU, \
- which normally involves copies. Plus there's the latency \
- of the multiply itself, and the latency of the instructions to \
- transfer integer regs to FP regs. */ \
- if (GET_MODE_SIZE (GET_MODE (X)) > 2) \
- return COSTS_N_INSNS (10); \
- return COSTS_N_INSNS (2); \
- case PLUS: \
- case MINUS: \
- case ASHIFT: \
- case ASHIFTRT: \
- case LSHIFTRT: \
- return COSTS_N_INSNS (1); \
- case DIV: \
- case UDIV: \
- case MOD: \
- case UMOD: \
- /* We make divide expensive, so that divide-by-constant will be \
- optimized to a multiply. */ \
- return COSTS_N_INSNS (60);
-
-/* An expression giving the cost of an addressing mode that contains ADDRESS.
- If not defined, the cost is computed from the ADDRESS expression and the
- `CONST_COSTS' values. */
-
-#define ADDRESS_COST(ADDRESS) 0
-
/* A C expression for the cost of moving data from a register in class FROM to
- one in class TO. */
+ one in class TO, using MODE. */
-#define REGISTER_MOVE_COST(MODE, FROM, TO) \
- ia64_register_move_cost((FROM), (TO))
+#define REGISTER_MOVE_COST ia64_register_move_cost
/* A C expression for the cost of moving data of mode M between a
register and memory. */
#define MEMORY_MOVE_COST(MODE,CLASS,IN) \
- ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS ? 4 : 10)
+ ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \
+ || (CLASS) == GR_AND_FR_REGS ? 4 : 10)
/* A C expression for the cost of a branch instruction. A value of 1 is the
- default; other values are interpreted relative to that. Used by the
+ default; other values are interpreted relative to that. Used by the
if-conversion code as max instruction count. */
/* ??? This requires investigation. The primary effect might be how
many additional insn groups we run into, vs how good the dynamic
#define BSS_SECTION_ASM_OP "\t.bss"
-/* Define this macro if references to a symbol must be treated differently
- depending on something about the variable or function named by the symbol
- (such as what section it is in). */
-
-#define ENCODE_SECTION_INFO(DECL) ia64_encode_section_info (DECL)
-
-/* If a variable is weakened, made one only or moved into a different
- section, it may be necessary to redo the section info to move the
- variable out of sdata. */
-
-#define REDO_SECTION_INFO_P(DECL) \
- ((TREE_CODE (DECL) == VAR_DECL) \
- && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \
- || DECL_SECTION_NAME (DECL) != 0))
-
-#define SDATA_NAME_FLAG_CHAR '@'
-
#define IA64_DEFAULT_GVALUE 8
-
-/* Decode SYM_NAME and store the real name part in VAR, sans the characters
- that encode section info. */
-
-#define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
-do { \
- (VAR) = (SYMBOL_NAME); \
- if ((VAR)[0] == SDATA_NAME_FLAG_CHAR) \
- (VAR)++; \
- if ((VAR)[0] == '*') \
- (VAR)++; \
-} while (0)
\f
/* Position Independent Code. */
/* A C string constant for text to be output before each `asm' statement or
group of consecutive ones. */
-/* ??? This won't work with the Intel assembler, because it does not accept
- # as a comment start character. However, //APP does not work in gas, so we
- can't use that either. Same problem for ASM_APP_OFF below. */
-
-#define ASM_APP_ON "#APP\n"
+#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n")
/* A C string constant for text to be output after each `asm' statement or
group of consecutive ones. */
-#define ASM_APP_OFF "#NO_APP\n"
-
-\f
-/* Output of Data. */
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
- to assemble a floating-point constant of `TFmode', `DFmode', `SFmode',
- respectively, whose value is VALUE. */
-
-/* ??? Must reverse the word order for big-endian code? */
-
-#define ASM_OUTPUT_LONG_DOUBLE(FILE, VALUE) \
-do { \
- long t[3]; \
- REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, t); \
- fprintf (FILE, "\tdata4 0x%08lx, 0x%08lx, 0x%08lx, 0x%08lx\n", \
- t[0] & 0xffffffff, t[1] & 0xffffffff, t[2] & 0xffffffff, 0L);\
-} while (0)
-
-/* ??? Must reverse the word order for big-endian code? */
-
-#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
-do { \
- long t[2]; \
- REAL_VALUE_TO_TARGET_DOUBLE (VALUE, t); \
- fprintf (FILE, "\tdata8 0x%08lx%08lx\n", \
- t[1] & 0xffffffff, t[0] & 0xffffffff); \
-} while (0)
-
-#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
- do { \
- long t; \
- REAL_VALUE_TO_TARGET_SINGLE (VALUE, t); \
- fprintf (FILE, "\tdata4 0x%lx\n", t & 0xffffffff); \
-} while (0)
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
- to assemble an integer of 1, 2, 4, or 8 bytes, respectively, whose value
- is VALUE. */
-
-/* This is how to output an assembler line defining a `char' constant. */
-
-#define ASM_OUTPUT_CHAR(FILE, VALUE) \
-do { \
- fprintf (FILE, "%s", ASM_BYTE_OP); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining a `short' constant. */
-
-#define ASM_OUTPUT_SHORT(FILE, VALUE) \
-do { \
- fprintf (FILE, "\tdata2\t"); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining an `int' constant.
- We also handle symbol output here. */
-
-/* ??? For ILP32, also need to handle function addresses here. */
-
-#define ASM_OUTPUT_INT(FILE, VALUE) \
-do { \
- fprintf (FILE, "\tdata4\t"); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining a `long' constant.
- We also handle symbol output here. */
-
-#define ASM_OUTPUT_DOUBLE_INT(FILE, VALUE) \
-do { \
- fprintf (FILE, "\tdata8\t"); \
- if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
- fprintf (FILE, "@fptr("); \
- output_addr_const (FILE, (VALUE)); \
- if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) && SYMBOL_REF_FLAG (VALUE)) \
- fprintf (FILE, ")"); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining a `char' constant
- to an xdata segment. */
-
-#define ASM_OUTPUT_XDATA_CHAR(FILE, SECTION, VALUE) \
-do { \
- fprintf (FILE, "\t.xdata1\t\"%s\", ", SECTION); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining a `short' constant
- to an xdata segment. */
-
-#define ASM_OUTPUT_XDATA_SHORT(FILE, SECTION, VALUE) \
-do { \
- fprintf (FILE, "\t.xdata2\t\"%s\", ", SECTION); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining an `int' constant
- to an xdata segment. We also handle symbol output here. */
-
-/* ??? For ILP32, also need to handle function addresses here. */
-
-#define ASM_OUTPUT_XDATA_INT(FILE, SECTION, VALUE) \
-do { \
- fprintf (FILE, "\t.xdata4\t\"%s\", ", SECTION); \
- output_addr_const (FILE, (VALUE)); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-/* This is how to output an assembler line defining a `long' constant
- to an xdata segment. We also handle symbol output here. */
-
-#define ASM_OUTPUT_XDATA_DOUBLE_INT(FILE, SECTION, VALUE) \
-do { \
- int need_closing_paren = 0; \
- fprintf (FILE, "\t.xdata8\t\"%s\", ", SECTION); \
- if (!(TARGET_NO_PIC || TARGET_AUTO_PIC) \
- && GET_CODE (VALUE) == SYMBOL_REF) \
- { \
- fprintf (FILE, SYMBOL_REF_FLAG (VALUE) ? "@fptr(" : "@segrel("); \
- need_closing_paren = 1; \
- } \
- output_addr_const (FILE, VALUE); \
- if (need_closing_paren) \
- fprintf (FILE, ")"); \
- fprintf (FILE, "\n"); \
-} while (0)
-
-
-/* A C statement to output to the stdio stream STREAM an assembler instruction
- to assemble a single byte containing the number VALUE. */
-
-#define ASM_OUTPUT_BYTE(STREAM, VALUE) \
- fprintf (STREAM, "%s0x%x\n", ASM_BYTE_OP, (int)(VALUE) & 0xff)
-
+#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n")
\f
/* Output of Uninitialized Variables. */
ia64_asm_output_label = 0; \
} while (0)
-/* A C statement (sans semicolon) to output to the stdio stream STREAM some
- commands that will make the label NAME global; that is, available for
- reference from other files. */
-
-#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
-do { \
- fputs ("\t.global ", STREAM); \
- assemble_name (STREAM, NAME); \
- fputs ("\n", STREAM); \
-} while (0)
+/* Globalizing directive for a label. */
+#define GLOBAL_ASM_OP "\t.global "
/* A C statement (sans semicolon) to output to the stdio stream STREAM any text
necessary for declaring the name of an external symbol named NAME which is
sprintf (LABEL, "*.%s%d", PREFIX, NUM); \
} while (0)
-/* A C expression to assign to OUTVAR (which is a variable of type `char *') a
- newly allocated string made from the string NAME and the number NUMBER, with
- some suitable punctuation added. */
-
/* ??? Not sure if using a ? in the name for Intel as is safe. */
-#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
-do { \
- (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \
- sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \
- (long)(NUMBER)); \
-} while (0)
+#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu")
/* A C statement to output to the stdio stream STREAM assembler code which
defines (equates) the symbol NAME to have the value VALUE. */
#define REGISTER_NAMES \
{ \
/* General registers. */ \
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
+ "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \
"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
"r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
"r30", "r31", \
"p60", "p61", "p62", "p63", \
/* Branch registers. */ \
"b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \
- /* Frame pointer. Return address. */ \
- "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
+ /* Frame pointer. Application registers. */ \
+ "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \
}
/* If defined, a C initializer for an array of structures containing a name and
{ "loc79", LOC_REG (79) }, \
}
+/* Emit a dtp-relative reference to a TLS variable. */
+
+#ifdef HAVE_AS_TLS
+#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
+ ia64_output_dwarf_dtprel (FILE, SIZE, X)
+#endif
+
/* A C compound statement to output to stdio stream STREAM the assembler syntax
for an instruction operand X. X is an RTL expression. */
/* ??? Depends on the pointer size. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
- fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE)
+#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
+ do { \
+ if (TARGET_ILP32) \
+ fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \
+ else \
+ fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \
+ } while (0)
/* This is how to output an element of a case-vector that is absolute.
(Ia64 does not use such vectors, but we must define this macro anyway.) */
true if the symbol may be affected by dynamic relocations. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
(((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \
- | ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_udata8)
+ | ((GLOBAL) ? DW_EH_PE_indirect : 0) \
+ | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8))
/* Handle special EH pointer encodings. Absolute, pc-relative, and
indirect are handled automatically. */
reltag = "@gprel("; \
if (reltag) \
{ \
- fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
- : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
- : (abort (), "")), FILE); \
+ fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs (reltag, FILE); \
assemble_name (FILE, XSTR (ADDR, 0)); \
fputc (')', FILE); \
\f
/* Macros for SDB and Dwarf Output. */
-/* Define this macro if GNU CC should produce dwarf version 2 format debugging
+/* Define this macro if GCC should produce dwarf version 2 format debugging
output in response to the `-g' option. */
-#define DWARF2_DEBUGGING_INFO
-
-/* C string constants giving the pseudo-op to use for a sequence of
- 2, 4, and 8 byte unaligned constants. dwarf2out.c needs these. */
-
-#define UNALIGNED_SHORT_ASM_OP "\tdata2.ua\t"
-#define UNALIGNED_INT_ASM_OP "\tdata4.ua\t"
-#define UNALIGNED_DOUBLE_INT_ASM_OP "\tdata8.ua\t"
+#define DWARF2_DEBUGGING_INFO 1
#define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM)
/* Use tags for debug info labels, so that they don't break instruction
bundles. This also avoids getting spurious DV warnings from the
- assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we
+ assembler. This is similar to (*targetm.asm_out.internal_label), except that we
add brackets around the label. */
#define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
- fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM)
+ fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM)
/* Use section-relative relocations for debugging offsets. Unlike other
- targets that fake this by putting the section VMA at 0, IA-64 has
+ targets that fake this by putting the section VMA at 0, IA-64 has
proper relocations for them. */
#define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \
do { \
- fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
- : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
- : (abort (), "")), FILE); \
+ fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@secrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
/* Emit a PC-relative relocation. */
#define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
do { \
- fputs (((SIZE) == 4 ? UNALIGNED_INT_ASM_OP \
- : (SIZE) == 8 ? UNALIGNED_DOUBLE_INT_ASM_OP \
- : (abort (), "")), FILE); \
+ fputs (integer_asm_op (SIZE, FALSE), FILE); \
fputs ("@pcrel(", FILE); \
assemble_name (FILE, LABEL); \
fputc (')', FILE); \
} while (0)
\f
-/* Cross Compilation and Floating Point. */
-
-/* Define to enable software floating point emulation. */
-#define REAL_ARITHMETIC
-
-\f
/* Register Renaming Parameters. */
/* A C expression that is nonzero if hard register number REGNO2 can be
#define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
ia64_hard_regno_rename_ok((REGNO1), (REGNO2))
-/* Define this macro if the compiler should use extended basic blocks
- when renaming registers. Define this macro if the target has predicate
- registers. */
-
-#define RENAME_EXTENDED_BLOCKS
-
\f
/* Miscellaneous Parameters. */
+/* Flag to mark data that is in the small address area (addressable
+ via "addl", that is, within a 2MByte offset of 0. */
+#define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
+#define SYMBOL_REF_SMALL_ADDR_P(X) \
+ ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
+
/* Define this if you have defined special-purpose predicates in the file
`MACHINE.c'. For each predicate, list all rtl codes that can be in
expressions matched by the predicate. */
{ "call_operand", {SUBREG, REG, SYMBOL_REF}}, \
{ "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \
+{ "small_addr_symbolic_operand", {SYMBOL_REF}}, \
{ "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
{ "function_operand", {SYMBOL_REF}}, \
{ "setjmp_operand", {SYMBOL_REF}}, \
{ "ar_lc_reg_operand", {REG}}, \
{ "ar_ccv_reg_operand", {REG}}, \
{ "ar_pfs_reg_operand", {REG}}, \
-{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
-{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
-{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
+{ "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
+{ "destination_xfmode_operand", {SUBREG, REG, MEM}}, \
+{ "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
+{ "basereg_operand", {SUBREG, REG}},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */
-#define CASE_VECTOR_MODE Pmode
+#define CASE_VECTOR_MODE ptr_mode
/* Define as C expression which evaluates to nonzero if the tablejump
instruction expects the table to contain offsets from the address of the
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
-/* An alias for a tree code that should be used by default for conversion of
- floating point values to fixed point. */
-
-/* ??? Looks like this macro is obsolete and should be deleted everywhere. */
-
-#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
-
-/* An alias for a tree code that is the easiest kind of division to compile
- code for in the general case. */
-
-#define EASY_DIV_EXPR TRUNC_DIV_EXPR
-
/* The maximum number of bytes that a single instruction can move quickly from
memory to memory. */
#define MOVE_MAX 8
an integral mode and stored by a store-flag instruction (`sCOND') when the
condition is true. */
-/* ??? Investigate using -1 instead of 1. */
-
-#define STORE_FLAG_VALUE 1
+/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */
/* An alias for the machine mode for pointers. */
#pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is
defined. */
-#define HANDLE_SYSV_PRAGMA
+/* If this architecture supports prefetch, define this to be the number of
+ prefetch commands that can be executed in parallel.
+
+ ??? This number is bogus and needs to be replaced before the value is
+ actually used in optimizations. */
+
+#define SIMULTANEOUS_PREFETCHES 6
-/* In rare cases, correct code generation requires extra machine dependent
- processing between the second jump optimization pass and delayed branch
- scheduling. On those machines, define this macro as a C statement to act on
- the code starting at INSN. */
+/* If this architecture supports prefetch, define this to be the size of
+ the cache line that is prefetched. */
-#define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN)
+#define PREFETCH_BLOCK 32
+
+#define HANDLE_SYSV_PRAGMA 1
/* A C expression for the maximum number of instructions to execute via
conditional execution instructions instead of a branch. A value of
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM)
/* This function contains machine specific function data. */
-struct machine_function
+struct machine_function GTY(())
{
/* The new stack pointer when unwinding from EH. */
- struct rtx_def* ia64_eh_epilogue_sp;
+ rtx ia64_eh_epilogue_sp;
- /* The new bsp value when unwinding from EH. */
- struct rtx_def* ia64_eh_epilogue_bsp;
+ /* The new bsp value when unwinding from EH. */
+ rtx ia64_eh_epilogue_bsp;
/* The GP value save register. */
- struct rtx_def* ia64_gp_save;
+ rtx ia64_gp_save;
/* The number of varargs registers to save. */
int n_varargs;
IA64_BUILTIN_FLUSHRS
};
-/* Codes for expand_compare_and_swap and expand_swap_and_compare. */
+/* Codes for expand_compare_and_swap and expand_swap_and_compare. */
enum fetchop_code {
IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP
};
+#define DONT_USE_BUILTIN_SETJMP
+
+/* Output any profiling code before the prologue. */
+
+#undef PROFILE_BEFORE_PROLOGUE
+#define PROFILE_BEFORE_PROLOGUE 1
+
+\f
+
+/* Switch on code for querying unit reservations. */
+#define CPU_UNITS_QUERY 1
+
/* End of ia64.h */
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