/* Definitions of target machine for GNU compiler, for Intel 860.
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-
- Written by Richard Stallman (rms@ai.mit.edu).
-
- Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater to
+ Copyright (C) 1989, 1991, 1993, 1995, 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
+ Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
the whims of the System V Release 4 assembler.
This file is part of GNU CC.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
/* Note that some other tm.h files include this one and then override
/* Names to predefine in the preprocessor for this target machine. */
-#define CPP_PREDEFINES "-Di860 -Dunix"
+#define CPP_PREDEFINES "-Di860 -Dunix -Asystem=unix -Asystem=svr4 -Acpu=i860 -Amachine=i860"
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION fprintf (stderr, " (i860)");
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"xp", 1}, \
- {"noxp", -1}, \
- {"xr", -1}, \
- { "", TARGET_DEFAULT}}
+ { {"xp", 1, N_("Generate code which uses the FPU")}, \
+ {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
+ {"xr", -1, N_("Do not generate code which uses the FPU")}, \
+ { "", TARGET_DEFAULT, NULL}}
#define TARGET_DEFAULT 0
\f
/* Define this if most significant word of a multiword number is the lowest
numbered. */
/* For the i860 this goes with BYTES_BIG_ENDIAN. */
+/* NOTE: GCC probably cannot support a big-endian i860
+ because GCC fundamentally assumes that the order of words
+ in memory as the same as the order in registers.
+ That's not true for the big-endian i860.
+ The big-endian i860 isn't important enough to
+ justify the trouble of changing this assumption. */
#define WORDS_BIG_ENDIAN 0
/* number of bits in an addressable storage unit */
when given unaligned data. */
#define STRICT_ALIGNMENT 1
-/* If bit field type is int, dont let it cross an int,
+/* If bit field type is int, don't let it cross an int,
and give entire struct the alignment of an int. */
#define PCC_BITFIELD_TYPE_MATTERS 1
\f
returned. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
- ((CLASS) == FP_REGS && GET_CODE (IN) == CONST_INT ? GENERAL_REGS : NO_REGS)
+ ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
/* Value is the number of bytes of arguments automatically
popped when returning from a subroutine call.
+ FUNDECL is the declaration node of the function (as a tree),
FUNTYPE is the data type of the function (as a tree),
or for a library call it is an identifier node for the subroutine name.
SIZE is the number of bytes of arguments passed on the stack. */
-#define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
+#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
/* Define how to find the value returned by a function.
VALTYPE is the data type of the value (as a tree).
/* On the i860, the value register depends on the mode. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx (REG, TYPE_MODE (VALTYPE), \
- (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
- ? 40 : 16))
+ gen_rtx_REG (TYPE_MODE (VALTYPE), \
+ (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
+ ? 40 : 16))
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, MODE, \
- (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
- ? 40 : 16))
+ gen_rtx_REG (MODE, \
+ (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
+ ? 40 : 16))
/* 1 if N is a possible register number for a function value
as seen by the caller. */
when the function gets a structure-value-address as an
invisible first argument. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
- ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p ((FNTYPE)) \
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+ ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
? 4 : 0), \
(CUM).floats = 0)
? 0 \
: GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
- ? gen_rtx (REG, (MODE), \
- 40+(ROUNDUP ((CUM).floats, \
- GET_MODE_SIZE ((MODE))) \
- / 4)) \
+ ? gen_rtx_REG ((MODE), \
+ 40 + (ROUNDUP ((CUM).floats, \
+ GET_MODE_SIZE ((MODE))) \
+ / 4)) \
: 0) \
: GET_MODE_CLASS ((MODE)) == MODE_INT \
? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
- ? gen_rtx (REG, (MODE), \
- 16+(ROUNDUP ((CUM).ints, \
- GET_MODE_SIZE ((MODE))) \
- / 4)) \
+ ? gen_rtx_REG ((MODE), \
+ 16 + (ROUNDUP ((CUM).ints, \
+ GET_MODE_SIZE ((MODE))) \
+ / 4)) \
: 0) \
: 0)
? PARM_BOUNDARY \
: GET_MODE_ALIGNMENT(MODE)))
-/* This macro generates the assembly code for function entry.
-
- FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
-*/
-
-#define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue ((FILE), (SIZE))
-
/* Output a no-op just before the beginning of the function,
to ensure that there does not appear to be a delayed branch there.
Such a thing would confuse interrupt recovery. */
#define EXIT_IGNORE_STACK 1
-/* This macro generates the assembly code for function exit.
+/* Generate necessary RTL for __builtin_saveregs(). */
+#define EXPAND_BUILTIN_SAVEREGS() \
+ i860_saveregs()
- FILE is a stdio stream to output the code to.
- SIZE is an int: how many units of temporary storage to allocate.
+/* Define the `__builtin_va_list' type for the ABI. */
+#define BUILD_VA_LIST_TYPE(VALIST) \
+ (VALIST) = i860_build_va_list ()
- The function epilogue should not depend on the current stack pointer!
- It should use the frame pointer only. This is mandatory because
- of alloca; we also take advantage of it to omit stack adjustments
- before returning.
-*/
+/* Implement `va_start' for varargs and stdarg. */
+#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
+ i860_va_start (stdarg, valist, nextarg)
-#define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue ((FILE), (SIZE))
+/* Implement `va_arg'. */
+#define EXPAND_BUILTIN_VA_ARG(valist, type) \
+ i860_va_arg (valist, type)
/* Store in the variable DEPTH the initial difference between the
frame pointer reg contents and the stack pointer reg contents,
or #BOTTOM_OF_STATIC,r29,r29 */
#define TRAMPOLINE_TEMPLATE(FILE) \
{ \
- ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1f0000)); \
- ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7ff0000)); \
- ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xec1d0000)); \
- ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4000f800)); \
- ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0xe7bd0000)); \
+ ASM_OUTPUT_INT (FILE, GEN_INT (0xec1f0000)); \
+ ASM_OUTPUT_INT (FILE, GEN_INT (0xe7ff0000)); \
+ ASM_OUTPUT_INT (FILE, GEN_INT (0xec1d0000)); \
+ ASM_OUTPUT_INT (FILE, GEN_INT (0x4000f800)); \
+ ASM_OUTPUT_INT (FILE, GEN_INT (0xe7bd0000)); \
}
/* Length in units of the trampoline for entering a nested function. */
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
- rtx low_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
- size_int (16), 0, 0); \
- rtx low_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
+ rtx cxt = force_reg (Pmode, CXT); \
+ rtx fn = force_reg (Pmode, FNADDR); \
+ rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \
size_int (16), 0, 0); \
- emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 16)), \
- gen_rtx (SUBREG, HImode, CXT)); \
- emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 4)), \
- gen_rtx (SUBREG, HImode, FNADDR)); \
- emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 8)), \
- gen_rtx (SUBREG, HImode, low_cxt)); \
- emit_move_insn (gen_rtx (MEM, HImode, plus_constant (TRAMP, 0)), \
- gen_rtx (SUBREG, HImode, low_fn)); \
+ rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \
+ size_int (16), 0, 0); \
+ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 16)), \
+ gen_lowpart (HImode, cxt)); \
+ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 4)), \
+ gen_lowpart (HImode, fn)); \
+ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 8)), \
+ gen_lowpart (HImode, hi_cxt)); \
+ emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 0)), \
+ gen_lowpart (HImode, hi_fn)); \
}
\f
/* Addressing modes, and classification of registers for them. */
-/* #define HAVE_POST_INCREMENT */
-/* #define HAVE_POST_DECREMENT */
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
-/* #define HAVE_PRE_DECREMENT */
-/* #define HAVE_PRE_INCREMENT */
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
/* Macros to check register numbers against specific register classes. */
/* Recognize any constant value that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
+#define CONSTANT_ADDRESS_P(X) \
+ (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
+ || GET_CODE (X) == HIGH)
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
- force_operand (XEXP (X, 0), 0)); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
+ force_operand (XEXP (X, 0), 0)); \
if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
- force_operand (XEXP (X, 1), 0)); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
+ force_operand (XEXP (X, 1), 0)); \
if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
- force_operand (XEXP (X, 0), 0)); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
+ force_operand (XEXP (X, 0), 0)); \
if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
- force_operand (XEXP (X, 1), 0)); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
+ force_operand (XEXP (X, 1), 0)); \
if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
&& GET_CODE (XEXP (X, 0)) != CONST_INT) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 1), \
- copy_to_mode_reg (SImode, XEXP (X, 0))); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
+ copy_to_mode_reg (SImode, XEXP (X, 0))); \
if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
&& GET_CODE (XEXP (X, 1)) != CONST_INT) \
- (X) = gen_rtx (PLUS, SImode, XEXP (X, 0), \
- copy_to_mode_reg (SImode, XEXP (X, 1))); \
+ (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
+ copy_to_mode_reg (SImode, XEXP (X, 1))); \
if (GET_CODE (x) == SYMBOL_REF) \
(X) = copy_to_reg (X); \
if (GET_CODE (x) == CONST) \
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE SImode
-/* Define this if the tablejump instruction expects the table
- to contain offsets from the address of the table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE */
+/* Define as C expression which evaluates to nonzero if the tablejump
+ instruction expects the table to contain offsets from the address of the
+ table.
+ Do not define this if the table should contain absolute addresses. */
+/* #define CASE_VECTOR_PC_RELATIVE 1 */
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* Assembler pseudos to introduce constants of various size. */
-#define ASM_BYTE_OP "\t.byte"
+#define ASM_BYTE_OP "\t.byte\t"
#define ASM_SHORT "\t.short"
#define ASM_LONG "\t.long"
#define ASM_DOUBLE "\t.double"
/* Output before read-only data. */
-#define TEXT_SECTION_ASM_OP ".text"
+#define TEXT_SECTION_ASM_OP "\t.text"
/* Output before writable data. */
-#define DATA_SECTION_ASM_OP ".data"
+#define DATA_SECTION_ASM_OP "\t.data"
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
fputs ("\n", FILE); \
} while (0)
-/* This is how to output a reference to a user-level label named NAME.
- `assemble_name' uses this.
+/* The prefix to add to user-visible assembler symbols.
This definition is overridden in i860v4.h because under System V
Release 4, user-level symbols are *not* prefixed with underscores in
the generated assembly code. */
-#define ASM_OUTPUT_LABELREF(FILE,NAME) \
- fprintf (FILE, "_%s", NAME)
+#define USER_LABEL_PREFIX "_"
/* This is how to output an internal numbered label where
PREFIX is the class of label and NUM is the number within the class. */
(The i860 does not use such vectors,
but we must define this macro anyway.) */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
/* This is how to output an assembler line
( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
-/* Define the parentheses used to group arithmetic operations
- in assembler code. */
-
-#define ASM_OPEN_PAREN "("
-#define ASM_CLOSE_PAREN ")"
-
-/* Define results of standard character escape sequences. */
-#define TARGET_BELL 007
-#define TARGET_BS 010
-#define TARGET_TAB 011
-#define TARGET_NEWLINE 012
-#define TARGET_VT 013
-#define TARGET_FF 014
-#define TARGET_CR 015
-
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
For `%' followed by punctuation, CODE is the punctuation and X is null.
On the i860, the following target-specific special codes are recognized:
- `r' The operand can be anything, but if is is an immediate zero
+ `r' The operand can be anything, but if it is an immediate zero
value (either integer or floating point) then it will be
represented as `r0' or as `f0' (respectively).
"%" in i860.c.
*/
-extern char *i860_reg_prefix;
-extern unsigned long sfmode_constant_to_ulong ();
+extern const char *i860_reg_prefix;
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
else if ((CODE) == 'm') \
output_address (XEXP (X, 0)); \
else if ((CODE) == 'L') \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
+ { \
+ if (GET_CODE (X) == MEM) \
+ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
+ else \
+ PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
+ } \
else if ((CODE) == 'H') \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
+ { \
+ if (GET_CODE (X) == MEM) \
+ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
+ else \
+ PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
+ } \
else if ((CODE) == 'h') \
- if (GET_CODE (X) == MEM) \
- PRINT_OPERAND_PART (FILE, XEXP (X, 0), \
- const_int_operand (XEXP (X, 0)) \
- ? OPERAND_HIGH_PART \
- : OPERAND_HIGH_ADJ_PART); \
- else \
- PRINT_OPERAND_PART (FILE, X, \
- const_int_operand (X) \
- ? OPERAND_HIGH_PART \
- : OPERAND_HIGH_ADJ_PART); \
+ { \
+ if (GET_CODE (X) == MEM) \
+ PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \
+ else \
+ PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \
+ } \
else if (GET_CODE (X) == MEM) \
output_address (XEXP (X, 0)); \
else if ((CODE) == 'r' && (X) == const0_rtx) \
else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
fprintf (FILE, "%sf0", i860_reg_prefix); \
else if (GET_CODE (X) == CONST_DOUBLE) \
- fprintf (FILE, "0x%x", sfmode_constant_to_ulong (X)); \
+ fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (X)); \
else \
output_addr_const (FILE, X); }
\f
/* Print a memory address as an operand to reference that memory location. */
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
-{ register rtx base, index = 0; \
- int offset = 0; \
- register rtx addr = ADDR; \
+{ register rtx addr = ADDR; \
if (GET_CODE (addr) == REG) \
{ \
fprintf (FILE, "0(%s%s)", \
} \
else if (GET_CODE (addr) == CONST_DOUBLE \
&& GET_MODE (addr) == SFmode) \
- fprintf (FILE, "0x%x", sfmode_constant_to_ulong (addr)); \
+ fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (addr)); \
else if (GET_CODE (addr) == PLUS) \
{ \
if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
} \
}
-/* The following #defines are used when compiling the routines in
- libgcc1.c. Since the i860 calling conventions require single
- precision floats to be passed in the floating-point registers
- (rather than in the general registers) we have to build the
- libgcc1.c routines in such a way that they know the actual types
- of their formal arguments and the actual types of their return
- values. Otherwise, gcc will generate calls to the libgcc1.c
- routines, passing arguments in the floating-point registers,
- but the libgcc1.c routines will expect their arguments on the
- stack (where the i860 calling conventions require structs &
- unions to be passed). */
-
-#define FLOAT_TYPE_VALUE float
-#define INTIFY(FLOATVAL) (FLOATVAL)
-#define FLOATIFY(INTVAL) (INTVAL)
-#define FLOAT_ARG_TYPE float
-
-
/* Optionally define this if you have added predicates to
`MACHINE.c'. This macro is called within an initializer of an
array of structures. The first field in the structure is the
Instead, it allows the table built by `genrecog' to be more
compact and efficient, thus speeding up the compiler. The most
important predicates to include in the list specified by this
- macro are thoses used in the most insn patterns.
-
- Note that for the i860 we have one more predicate, i.e.
- `single_insn_src_operand', however this is used only
- infrequently, so we don't put in the PREDICATE_CODES list.
-*/
+ macro are thoses used in the most insn patterns. */
#define PREDICATE_CODES \
{"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
{"logic_const_operand", {CONST_INT}}, \
{"bte_operand", {REG, SUBREG, CONST_INT}}, \
{"indexed_operand", {MEM}}, \
- {"load_operand", {MEM}},
+ {"load_operand", {MEM}}, \
+ {"small_int", {CONST_INT}}, \
+ {"logic_int", {CONST_INT}}, \
+ {"call_insn_operand", {MEM}},
/* Define the information needed to generate branch insns. This is stored
from the compare operation. Note that we can't use "rtx" here since it
hasn't been defined! */
extern struct rtx_def *i860_compare_op0, *i860_compare_op1;
-
-/* Declare things which are defined in i860.c but called from
- insn-output.c. */
-
-extern unsigned long sfmode_constant_to_ulong ();
-extern char *output_load ();
-extern char *output_store ();
-extern char *output_move_double ();
-extern char *output_fp_move_double ();
-extern char *output_block_move ();
-extern char *output_delay_insn ();
-extern char *output_delayed_branch ();
-extern void output_load_address ();
OSDN Git Service
