;; Z -- likewise, with special suffixes for x87 instructions.
;; * -- print a star (in certain assembler syntax)
;; A -- print an absolute memory reference.
+;; E -- print address with DImode register names if TARGET_64BIT.
;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
;; s -- print a shift double count, followed by the assemblers argument
;; delimiter.
;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
+;; K -- print HLE lock prefix
;; Y -- print condition for XOP pcom* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
+;; ~ -- print "i" if TARGET_AVX2, "f" otherwise.
;; @ -- print a segment register of thread base pointer load
+;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
(define_c_enum "unspec" [
;; Relocation specifiers
;; Prologue support
UNSPEC_STACK_ALLOC
UNSPEC_SET_GOT
- UNSPEC_REG_SAVE
- UNSPEC_DEF_CFA
UNSPEC_SET_RIP
UNSPEC_SET_GOT_OFFSET
UNSPEC_MEMORY_BLOCKAGE
UNSPEC_MS_TO_SYSV_CALL
UNSPEC_CALL_NEEDS_VZEROUPPER
UNSPEC_PAUSE
+ UNSPEC_LEA_ADDR
+ UNSPEC_XBEGIN_ABORT
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
;; For CRC32 support
UNSPEC_CRC32
- ;; For RDRAND support
- UNSPEC_RDRAND
-
;; For BMI support
UNSPEC_BEXTR
UNSPECV_RDGSBASE
UNSPECV_WRFSBASE
UNSPECV_WRGSBASE
+
+ ;; For RDRAND support
+ UNSPECV_RDRAND
+
+ ;; For RTM support
+ UNSPECV_XBEGIN
+ UNSPECV_XEND
+ UNSPECV_XABORT
+ UNSPECV_XTEST
])
;; Constants to represent rounding modes in the ROUND instruction
(eq_attr "type" "imov,test")
(symbol_ref "ix86_attr_length_immediate_default (insn, false)")
(eq_attr "type" "call")
- (if_then_else (match_operand 0 "constant_call_address_operand" "")
+ (if_then_else (match_operand 0 "constant_call_address_operand")
(const_int 4)
(const_int 0))
(eq_attr "type" "callv")
- (if_then_else (match_operand 1 "constant_call_address_operand" "")
+ (if_then_else (match_operand 1 "constant_call_address_operand")
(const_int 4)
(const_int 0))
;; We don't know the size before shorten_branches. Expect
(cond [(eq_attr "type" "str,other,multi,fxch")
(const_int 0)
(and (eq_attr "type" "call")
- (match_operand 0 "constant_call_address_operand" ""))
+ (match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
- (match_operand 1 "constant_call_address_operand" ""))
+ (match_operand 1 "constant_call_address_operand"))
(const_int 0)
]
(symbol_ref "ix86_attr_length_address_default (insn)")))
(match_test "x86_extended_reg_mentioned_p (insn)")
(const_int 1)
(and (eq_attr "type" "imovx")
- (match_operand:QI 1 "ext_QIreg_operand" ""))
+ (match_operand:QI 1 "ext_QIreg_operand"))
(const_int 1)
]
(const_int 0)))
(const_int 0)
(and (eq_attr "type" "incdec")
(and (not (match_test "TARGET_64BIT"))
- (ior (match_operand:SI 1 "register_operand" "")
- (match_operand:HI 1 "register_operand" ""))))
+ (ior (match_operand:SI 1 "register_operand")
+ (match_operand:HI 1 "register_operand"))))
(const_int 0)
(and (eq_attr "type" "push")
- (not (match_operand 1 "memory_operand" "")))
+ (not (match_operand 1 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "pop")
- (not (match_operand 0 "memory_operand" "")))
+ (not (match_operand 0 "memory_operand")))
(const_int 0)
(and (eq_attr "type" "imov")
(and (not (eq_attr "mode" "DI"))
- (ior (and (match_operand 0 "register_operand" "")
- (match_operand 1 "immediate_operand" ""))
- (ior (and (match_operand 0 "ax_reg_operand" "")
- (match_operand 1 "memory_displacement_only_operand" ""))
- (and (match_operand 0 "memory_displacement_only_operand" "")
- (match_operand 1 "ax_reg_operand" ""))))))
+ (ior (and (match_operand 0 "register_operand")
+ (match_operand 1 "immediate_operand"))
+ (ior (and (match_operand 0 "ax_reg_operand")
+ (match_operand 1 "memory_displacement_only_operand"))
+ (and (match_operand 0 "memory_displacement_only_operand")
+ (match_operand 1 "ax_reg_operand"))))))
(const_int 0)
(and (eq_attr "type" "call")
- (match_operand 0 "constant_call_address_operand" ""))
+ (match_operand 0 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "callv")
- (match_operand 1 "constant_call_address_operand" ""))
+ (match_operand 1 "constant_call_address_operand"))
(const_int 0)
(and (eq_attr "type" "alu,alu1,icmp,test")
- (match_operand 0 "ax_reg_operand" ""))
+ (match_operand 0 "ax_reg_operand"))
(symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))")
]
(const_int 1)))
(eq_attr "type" "frndint")
(const_string "load")
(eq_attr "type" "push")
- (if_then_else (match_operand 1 "memory_operand" "")
+ (if_then_else (match_operand 1 "memory_operand")
(const_string "both")
(const_string "store"))
(eq_attr "type" "pop")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "both")
(const_string "load"))
(eq_attr "type" "setcc")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "store")
(const_string "none"))
(eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
- (if_then_else (ior (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))
+ (if_then_else (ior (match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand"))
(const_string "load")
(const_string "none"))
(eq_attr "type" "ibr")
- (if_then_else (match_operand 0 "memory_operand" "")
+ (if_then_else (match_operand 0 "memory_operand")
(const_string "load")
(const_string "none"))
(eq_attr "type" "call")
- (if_then_else (match_operand 0 "constant_call_address_operand" "")
+ (if_then_else (match_operand 0 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(eq_attr "type" "callv")
- (if_then_else (match_operand 1 "constant_call_address_operand" "")
+ (if_then_else (match_operand 1 "constant_call_address_operand")
(const_string "none")
(const_string "load"))
(and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "both")
- (and (match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" ""))
+ (and (match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand"))
(const_string "both")
- (match_operand 0 "memory_operand" "")
+ (match_operand 0 "memory_operand")
(const_string "store")
- (match_operand 1 "memory_operand" "")
+ (match_operand 1 "memory_operand")
(const_string "load")
(and (eq_attr "type"
"!alu1,negnot,ishift1,
fmov,fcmp,fsgn,
sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
- (match_operand 2 "memory_operand" ""))
+ (match_operand 2 "memory_operand"))
(const_string "load")
(and (eq_attr "type" "icmov,ssemuladd,sse4arg")
- (match_operand 3 "memory_operand" ""))
+ (match_operand 3 "memory_operand"))
(const_string "load")
]
(const_string "none")))
(cond [(eq_attr "type" "other,multi")
(const_string "unknown")
(and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
- (and (match_operand 0 "memory_displacement_operand" "")
- (match_operand 1 "immediate_operand" "")))
+ (and (match_operand 0 "memory_displacement_operand")
+ (match_operand 1 "immediate_operand")))
(const_string "true")
(and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv")
- (and (match_operand 0 "memory_displacement_operand" "")
- (match_operand 2 "immediate_operand" "")))
+ (and (match_operand 0 "memory_displacement_operand")
+ (match_operand 2 "immediate_operand")))
(const_string "true")
]
(const_string "false")))
(define_attr "movu" "0,1" (const_string "0"))
;; Used to control the "enabled" attribute on a per-instruction basis.
-(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2"
+(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,avx2,noavx2,bmi2"
(const_string "base"))
(define_attr "enabled" ""
(symbol_ref "TARGET_SSE4_1 && !TARGET_AVX")
(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
+ (eq_attr "isa" "avx2") (symbol_ref "TARGET_AVX2")
+ (eq_attr "isa" "noavx2") (symbol_ref "!TARGET_AVX2")
(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
]
(const_int 1)))
;; Mapping of shift-right operators
(define_code_iterator any_shiftrt [lshiftrt ashiftrt])
+;; Mapping of all shift operators
+(define_code_iterator any_shift [ashift lshiftrt ashiftrt])
+
;; Base name for define_insn
(define_code_attr shift_insn
[(ashift "ashl") (lshiftrt "lshr") (ashiftrt "ashr")])
;; Prefix for define_insn
(define_code_attr u [(sign_extend "") (zero_extend "u")])
(define_code_attr s [(sign_extend "s") (zero_extend "u")])
+(define_code_attr u_bool [(sign_extend "false") (zero_extend "true")])
;; All integer modes.
(define_mode_iterator SWI1248x [QI HI SI DI])
;; pointer-sized quantities. Exactly one of the two alternatives will match.
(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
+;; This mode iterator allows :W to be used for patterns that operate on
+;; word_mode sized quantities.
+(define_mode_iterator W
+ [(SI "word_mode == SImode") (DI "word_mode == DImode")])
+
;; This mode iterator allows :PTR to be used for patterns that operate on
;; ptr_mode sized quantities.
(define_mode_iterator PTR
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))
+ (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))
(set (pc) (if_then_else
(match_operator 0 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
""
{
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "")
- (match_operand:SWIM 3 "<general_operand>" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:SWIM 2 "nonimmediate_operand")
+ (match_operand:SWIM 3 "<general_operand>")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ordered_comparison_operator"
[(reg:CC FLAGS_REG) (const_int 0)]))]
""
(define_expand "cmp<mode>_1"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:SWI48 1 "<general_operand>" "")))])
+ (compare:CC (match_operand:SWI48 0 "nonimmediate_operand")
+ (match_operand:SWI48 1 "<general_operand>")))])
(define_insn "*cmp<mode>_ccno_1"
[(set (reg FLAGS_REG)
(compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>")
- (match_operand:SWI 1 "const0_operand" "")))]
+ (match_operand:SWI 1 "const0_operand")))]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{<imodesuffix>}\t%0, %0
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
- (match_operand:QI 1 "const0_operand" "")))]
+ (match_operand:QI 1 "const0_operand")))]
"ix86_match_ccmode (insn, CCNOmode)"
"test{b}\t%h0, %h0"
[(set_attr "type" "test")
(compare:CC
(subreg:QI
(zero_extract:SI
- (match_operand 0 "ext_register_operand" "")
+ (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8)) 0)
- (match_operand:QI 1 "immediate_operand" "")))])
+ (match_operand:QI 1 "immediate_operand")))])
(define_insn "*cmpqi_ext_3_insn"
[(set (reg FLAGS_REG)
(define_expand "cbranchxf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 1 "nonmemory_operand" "")
- (match_operand:XF 2 "nonmemory_operand" "")))
+ (compare:CC (match_operand:XF 1 "nonmemory_operand")
+ (match_operand:XF 2 "nonmemory_operand")))
(set (pc) (if_then_else
(match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
"TARGET_80387"
{
(define_expand "cstorexf4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:XF 2 "nonmemory_operand" "")
- (match_operand:XF 3 "nonmemory_operand" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:XF 2 "nonmemory_operand")
+ (match_operand:XF 3 "nonmemory_operand")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
+ (compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand")
+ (match_operand:MODEF 2 "cmp_fp_expander_operand")))
(set (pc) (if_then_else
(match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
- (match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
- (set (match_operand:QI 0 "register_operand" "")
+ (compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand")
+ (match_operand:MODEF 3 "cmp_fp_expander_operand")))
+ (set (match_operand:QI 0 "register_operand")
(match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "comparison_operator"
- [(match_operand 1 "flags_reg_operand" "")
- (match_operand 2 "const0_operand" "")])
- (label_ref (match_operand 3 "" ""))
+ [(match_operand 1 "flags_reg_operand")
+ (match_operand 2 "const0_operand")])
+ (label_ref (match_operand 3))
(pc)))]
""
{
})
(define_expand "cstorecc4"
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "register_operand")
(match_operator 1 "comparison_operator"
- [(match_operand 2 "flags_reg_operand" "")
- (match_operand 3 "const0_operand" "")]))]
+ [(match_operand 2 "flags_reg_operand")
+ (match_operand 3 "const0_operand")]))]
""
{
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
(unspec:HI
[(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" ""))]
+ (match_operand 2 "const0_operand"))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set (reg:CCFP FLAGS_REG)
(compare:CCFP
(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "")))
+ (match_operand 2 "const0_operand")))
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))])
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
"* return output_fp_compare (insn, operands, true, false);"
[(set_attr "type" "fcmp")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (if_then_else (match_operand:SF 1 "" "")
+ (if_then_else (match_operand:SF 1)
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
"* return output_fp_compare (insn, operands, true, true);"
[(set_attr "type" "fcmp")
(set (attr "mode")
- (cond [(match_operand:SF 1 "" "")
+ (cond [(match_operand:SF 1)
(const_string "SF")
- (match_operand:DF 1 "" "")
+ (match_operand:DF 1)
(const_string "DF")
]
(const_string "XF")))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:TI 0 "push_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "push_operand")
+ (match_operand:TI 1 "general_operand"))]
"TARGET_64BIT && reload_completed
&& !SSE_REG_P (operands[1])"
[(const_int 0)]
;; upper part by 32bit move.
(define_peephole2
[(match_scratch:DI 2 "r")
- (set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ (set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 1))
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
[(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && ((optimize > 0 && flag_peephole2)
? epilogue_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
})
(define_split
- [(set (match_operand:DI 0 "push_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "push_operand")
+ (match_operand:DI 1 "general_operand"))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
[(const_int 0)]
(set_attr "mode" "SI")])
(define_insn "*push<mode>2_prologue"
- [(set (match_operand:P 0 "push_operand" "=<")
- (match_operand:P 1 "general_no_elim_operand" "r<i>*m"))
+ [(set (match_operand:W 0 "push_operand" "=<")
+ (match_operand:W 1 "general_no_elim_operand" "r<i>*m"))
(clobber (mem:BLK (scratch)))]
""
"push{<imodesuffix>}\t%1"
(set_attr "mode" "<MODE>")])
(define_insn "*pop<mode>1"
- [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
- (match_operand:P 1 "pop_operand" ">"))]
+ [(set (match_operand:W 0 "nonimmediate_operand" "=r*m")
+ (match_operand:W 1 "pop_operand" ">"))]
""
"pop{<imodesuffix>}\t%0"
[(set_attr "type" "pop")
(set_attr "mode" "<MODE>")])
(define_insn "*pop<mode>1_epilogue"
- [(set (match_operand:P 0 "nonimmediate_operand" "=r*m")
- (match_operand:P 1 "pop_operand" ">"))
+ [(set (match_operand:W 0 "nonimmediate_operand" "=r*m")
+ (match_operand:W 1 "pop_operand" ">"))
(clobber (mem:BLK (scratch)))]
""
"pop{<imodesuffix>}\t%0"
;; Move instructions.
(define_expand "movoi"
- [(set (match_operand:OI 0 "nonimmediate_operand" "")
- (match_operand:OI 1 "general_operand" ""))]
+ [(set (match_operand:OI 0 "nonimmediate_operand")
+ (match_operand:OI 1 "general_operand"))]
"TARGET_AVX"
"ix86_expand_move (OImode, operands); DONE;")
(define_expand "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "nonimmediate_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "nonimmediate_operand"))]
"TARGET_64BIT || TARGET_SSE"
{
if (TARGET_64BIT)
;; 32-bit targets when SSE is present, but doesn't seem to be harmful
;; to have around all the time.
(define_expand "movcdi"
- [(set (match_operand:CDI 0 "nonimmediate_operand" "")
- (match_operand:CDI 1 "general_operand" ""))]
+ [(set (match_operand:CDI 0 "nonimmediate_operand")
+ (match_operand:CDI 1 "general_operand"))]
""
{
if (push_operand (operands[0], CDImode))
})
(define_expand "mov<mode>"
- [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
- (match_operand:SWI1248x 1 "general_operand" ""))]
+ [(set (match_operand:SWI1248x 0 "nonimmediate_operand")
+ (match_operand:SWI1248x 1 "general_operand"))]
""
"ix86_expand_move (<MODE>mode, operands); DONE;")
(define_insn "*mov<mode>_xor"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (match_operand:SWI48 1 "const0_operand" ""))
+ (match_operand:SWI48 1 "const0_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
"xor{l}\t%k0, %k0"
(define_insn "*mov<mode>_or"
[(set (match_operand:SWI48 0 "register_operand" "=r")
- (match_operand:SWI48 1 "const_int_operand" ""))
+ (match_operand:SWI48 1 "const_int_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& operands[1] == constm1_rtx"
(set_attr "length_immediate" "1")])
(define_insn "*movoi_internal_avx"
- [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:OI 1 "vector_move_operand" "C,xm,x"))]
+ [(set (match_operand:OI 0 "nonimmediate_operand" "=x,x ,m")
+ (match_operand:OI 1 "vector_move_operand" "C ,xm,x"))]
"TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
case 2:
if (misaligned_operand (operands[0], OImode)
|| misaligned_operand (operands[1], OImode))
- return "vmovdqu\t{%1, %0|%0, %1}";
+ {
+ if (get_attr_mode (insn) == MODE_V8SF)
+ return "vmovups\t{%1, %0|%0, %1}";
+ else
+ return "vmovdqu\t{%1, %0|%0, %1}";
+ }
else
- return "vmovdqa\t{%1, %0|%0, %1}";
+ {
+ if (get_attr_mode (insn) == MODE_V8SF)
+ return "vmovaps\t{%1, %0|%0, %1}";
+ else
+ return "vmovdqa\t{%1, %0|%0, %1}";
+ }
default:
gcc_unreachable ();
}
}
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "vex")
- (set_attr "mode" "OI")])
+ (set (attr "mode")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V8SF")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V8SF")
+ ]
+ (const_string "OI")))])
(define_insn "*movti_internal_rex64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=!r,o,x,x,xm")
- (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,x,x ,m")
+ (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (which_alternative)
[(set_attr "type" "*,*,sselog1,ssemov,ssemov")
(set_attr "prefix" "*,*,maybe_vex,maybe_vex,maybe_vex")
(set (attr "mode")
- (cond [(eq_attr "alternative" "2,3")
- (if_then_else
- (match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "4")
- (if_then_else
- (ior (match_test "TARGET_SSE_TYPELESS_STORES")
- (match_test "optimize_function_for_size_p (cfun)"))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
+ (cond [(eq_attr "alternative" "0,1")
+ (const_string "DI")
+ (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (and (eq_attr "alternative" "4")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "general_operand"))]
"reload_completed
&& !SSE_REG_P (operands[0]) && !SSE_REG_P (operands[1])"
[(const_int 0)]
"ix86_split_long_move (operands); DONE;")
(define_insn "*movti_internal_sse"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x ,m")
+ (match_operand:TI 1 "vector_move_operand" "C ,xm,x"))]
"TARGET_SSE && !TARGET_64BIT
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
[(set_attr "type" "sselog1,ssemov,ssemov")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
- (cond [(ior (not (match_test "TARGET_SSE2"))
- (match_test "optimize_function_for_size_p (cfun)"))
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
(const_string "V4SF")
(and (eq_attr "alternative" "2")
(match_test "TARGET_SSE_TYPELESS_STORES"))
- (const_string "V4SF")]
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
(const_string "TI")))])
(define_insn "*movdi_internal_rex64"
return "movdq2q\t{%1, %0|%0, %1}";
case TYPE_SSEMOV:
- if (get_attr_mode (insn) == MODE_TI)
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "%vmovaps\t{%1, %0|%0, %1}";
+ else if (get_attr_mode (insn) == MODE_TI)
return "%vmovdqa\t{%1, %0|%0, %1}";
+
/* Handle broken assemblers that require movd instead of movq. */
if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
return "%vmovd\t{%1, %0|%0, %1}";
return "#";
case TYPE_LEA:
- return "lea{q}\t{%a1, %0|%0, %a1}";
+ return "lea{q}\t{%E1, %0|%0, %E1}";
default:
gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
else if (which_alternative == 2)
return "movabs{q}\t{%1, %0|%0, %1}";
else if (ix86_use_lea_for_mov (insn, operands))
- return "lea{q}\t{%a1, %0|%0, %a1}";
+ return "lea{q}\t{%E1, %0|%0, %E1}";
else
return "mov{q}\t{%1, %0|%0, %1}";
}
(const_string "ssemov")
(eq_attr "alternative" "16,17")
(const_string "ssecvt")
- (match_operand 1 "pic_32bit_operand" "")
+ (match_operand 1 "pic_32bit_operand")
(const_string "lea")
]
(const_string "imov")))
(if_then_else (eq_attr "alternative" "10,11,12,13,14,15")
(const_string "maybe_vex")
(const_string "orig")))
- (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,TI,DI,TI,DI,DI,DI,DI,DI")])
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "0,4")
+ (const_string "SI")
+ (eq_attr "alternative" "10,12")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "TI"))
+ ]
+ (const_string "DI")))])
;; Reload patterns to support multi-word load/store
;; with non-offsetable address.
;; fails, move by 32bit parts.
(define_peephole2
[(match_scratch:DI 2 "r")
- (set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ (set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode)"
[(set (match_dup 2) (match_dup 1))
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
&& !x86_64_immediate_operand (operands[1], DImode) && 1"
[(set (match_dup 2) (match_dup 3))
"split_double_mode (DImode, &operands[0], 2, &operands[2], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand"))]
"TARGET_64BIT && ((optimize > 0 && flag_peephole2)
? epilogue_completed : reload_completed)
&& !symbolic_operand (operands[1], DImode)
case MODE_DI:
return "%vmovq\t{%1, %0|%0, %1}";
case MODE_V4SF:
- return "movaps\t{%1, %0|%0, %1}";
+ return "%vmovaps\t{%1, %0|%0, %1}";
case MODE_V2SF:
return "movlps\t{%1, %0|%0, %1}";
default:
(if_then_else (eq_attr "alternative" "5,6,7,8")
(const_string "maybe_vex")
(const_string "orig")))
- (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF,DI,DI")])
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "9,11")
+ (const_string "V4SF")
+ (eq_attr "alternative" "10,12")
+ (const_string "V2SF")
+ (eq_attr "alternative" "5,7")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
+ ]
+ (const_string "TI"))
+ ]
+ (const_string "DI")))])
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "general_operand"))]
"!TARGET_64BIT && reload_completed
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
&& !(MMX_REG_P (operands[1]) || SSE_REG_P (operands[1]))"
return "movd\t{%1, %0|%0, %1}";
case TYPE_LEA:
- return "lea{l}\t{%a1, %0|%0, %a1}";
+ return "lea{l}\t{%E1, %0|%0, %E1}";
default:
gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
if (ix86_use_lea_for_mov (insn, operands))
- return "lea{l}\t{%a1, %0|%0, %a1}";
+ return "lea{l}\t{%E1, %0|%0, %E1}";
else
return "mov{l}\t{%1, %0|%0, %1}";
}
(const_string "sselog1")
(eq_attr "alternative" "7,8,9,10,11")
(const_string "ssemov")
- (match_operand 1 "pic_32bit_operand" "")
+ (match_operand 1 "pic_32bit_operand")
(const_string "lea")
]
(const_string "imov")))
(cond [(eq_attr "alternative" "2,3")
(const_string "DI")
(eq_attr "alternative" "6,7")
- (if_then_else
- (not (match_test "TARGET_SSE2"))
- (const_string "V4SF")
- (const_string "TI"))
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI"))
(and (eq_attr "alternative" "8,9,10,11")
(not (match_test "TARGET_SSE2")))
(const_string "SF")
(not (match_test "TARGET_HIMODE_MATH"))))
(const_string "imov")
(and (eq_attr "alternative" "1,2")
- (match_operand:HI 1 "aligned_operand" ""))
+ (match_operand:HI 1 "aligned_operand"))
(const_string "imov")
(and (match_test "TARGET_MOVX")
(eq_attr "alternative" "0,2"))
(cond [(eq_attr "type" "imovx")
(const_string "SI")
(and (eq_attr "alternative" "1,2")
- (match_operand:HI 1 "aligned_operand" ""))
+ (match_operand:HI 1 "aligned_operand"))
(const_string "SI")
(and (eq_attr "alternative" "0")
(ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "5")
- (not (match_operand:QI 1 "aligned_operand" "")))
+ (not (match_operand:QI 1 "aligned_operand")))
(const_string "imovx")
(match_test "optimize_function_for_size_p (cfun)")
(const_string "imov")
(set_attr "memory" "load")
(set_attr "mode" "<MODE>")])
-(define_insn "*swap<mode>"
+(define_insn "swap<mode>"
[(set (match_operand:SWI48 0 "register_operand" "+r")
(match_operand:SWI48 1 "register_operand" "+r"))
(set (match_dup 1)
(set_attr "athlon_decode" "vector")])
(define_expand "movstrict<mode>"
- [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand" ""))
- (match_operand:SWI12 1 "general_operand" ""))]
+ [(set (strict_low_part (match_operand:SWI12 0 "nonimmediate_operand"))
+ (match_operand:SWI12 1 "general_operand"))]
""
{
if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
(define_insn "*movstrict<mode>_xor"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
- (match_operand:SWI12 1 "const0_operand" ""))
+ (match_operand:SWI12 1 "const0_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
"xor{<imodesuffix>}\t%0, %0"
}
}
[(set (attr "type")
- (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (and (match_operand:QI 0 "register_operand" "")
- (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (and (match_operand:QI 0 "register_operand")
+ (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX"))
(const_string "imovx")
(const_string "imov")))
}
}
[(set (attr "type")
- (if_then_else (and (match_operand:QI 0 "register_operand" "")
- (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+ (if_then_else (and (match_operand:QI 0 "register_operand")
+ (ior (not (match_operand:QI 0 "QIreg_operand"))
(match_test "TARGET_MOVX")))
(const_string "imovx")
(const_string "imov")))
(const_string "QI")))])
(define_expand "mov<mode>_insv_1"
- [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "")
+ [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand:SWI48 1 "nonmemory_operand" ""))])
+ (match_operand:SWI48 1 "nonmemory_operand"))])
(define_insn "*mov<mode>_insv_1_rex64"
[(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q")
(define_insn "*pushtf"
[(set (match_operand:TF 0 "push_operand" "=<,<,<")
(match_operand:TF 1 "general_no_elim_operand" "x,Fo,*r"))]
- "TARGET_SSE2"
+ "TARGET_SSE"
{
/* This insn should be already split before reg-stack. */
gcc_unreachable ();
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:TF 0 "push_operand" "")
- (match_operand:TF 1 "sse_reg_operand" ""))]
- "TARGET_SSE2 && reload_completed"
+ [(set (match_operand:TF 0 "push_operand")
+ (match_operand:TF 1 "sse_reg_operand"))]
+ "TARGET_SSE && reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
(set (mem:TF (reg:P SP_REG)) (match_dup 1))])
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (match_operand:XF 1 "fp_register_operand" ""))]
+ [(set (match_operand:XF 0 "push_operand")
+ (match_operand:XF 1 "fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:XF (reg:P SP_REG)) (match_dup 1))]
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (match_operand:DF 1 "any_fp_register_operand" ""))]
+ [(set (match_operand:DF 0 "push_operand")
+ (match_operand:DF 1 "any_fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
(set (mem:DF (reg:P SP_REG)) (match_dup 1))])
;; %%% Kill this when call knows how to work this out.
(define_split
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "any_fp_register_operand" ""))]
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "any_fp_register_operand"))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:SF (reg:P SP_REG)) (match_dup 1))]
"operands[2] = GEN_INT (-GET_MODE_SIZE (<P:MODE>mode));")
(define_split
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "memory_operand" ""))]
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "memory_operand"))]
"reload_completed
&& (operands[2] = find_constant_src (insn))"
[(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand 0 "push_operand" "")
- (match_operand 1 "general_operand" ""))]
+ [(set (match_operand 0 "push_operand")
+ (match_operand 1 "general_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Floating point move instructions.
(define_expand "movtf"
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "nonimmediate_operand" ""))]
- "TARGET_SSE2"
+ [(set (match_operand:TF 0 "nonimmediate_operand")
+ (match_operand:TF 1 "nonimmediate_operand"))]
+ "TARGET_SSE"
{
ix86_expand_move (TFmode, operands);
DONE;
})
(define_expand "mov<mode>"
- [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
- (match_operand:X87MODEF 1 "general_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "nonimmediate_operand")
+ (match_operand:X87MODEF 1 "general_operand"))]
""
"ix86_expand_move (<MODE>mode, operands); DONE;")
(define_insn "*movtf_internal"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?*r ,!o")
- (match_operand:TF 1 "general_operand" "xm,x,C,*roF,F*r"))]
- "TARGET_SSE2
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=x,x ,m,?*r ,!o")
+ (match_operand:TF 1 "general_operand" "C ,xm,x,*roF,F*r"))]
+ "TARGET_SSE
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (!can_create_pseudo_p ()
|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
switch (which_alternative)
{
case 0:
+ return standard_sse_constant_opcode (insn, operands[1]);
case 1:
+ case 2:
/* Handle misaligned load/store since we
don't have movmisaligntf pattern. */
if (misaligned_operand (operands[0], TFmode)
return "%vmovdqa\t{%1, %0|%0, %1}";
}
- case 2:
- return standard_sse_constant_opcode (insn, operands[1]);
-
case 3:
case 4:
return "#";
gcc_unreachable ();
}
}
- [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
+ [(set_attr "type" "sselog1,ssemov,ssemov,*,*")
(set_attr "prefix" "maybe_vex,maybe_vex,maybe_vex,*,*")
(set (attr "mode")
- (cond [(eq_attr "alternative" "0,2")
- (if_then_else
- (match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "1")
- (if_then_else
- (ior (match_test "TARGET_SSE_TYPELESS_STORES")
- (match_test "optimize_function_for_size_p (cfun)"))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
+ (cond [(eq_attr "alternative" "3,4")
+ (const_string "DI")
+ (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (and (eq_attr "alternative" "2")
+ (match_test "TARGET_SSE_TYPELESS_STORES"))
+ (const_string "V4SF")
+ (match_test "TARGET_AVX")
+ (const_string "TI")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ ]
+ (const_string "TI")))])
;; Possible store forwarding (partial memory) stall in alternative 4.
(define_insn "*movxf_internal"
switch (get_attr_mode (insn))
{
case MODE_V2DF:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
(eq_attr "alternative" "3,4,5,6,11,12")
(const_string "DI")
- /* xorps is one byte shorter. */
+ /* xorps is one byte shorter for !TARGET_AVX. */
(eq_attr "alternative" "7")
- (cond [(match_test "optimize_function_for_size_p (cfun)")
+ (cond [(match_test "TARGET_AVX")
+ (const_string "V2DF")
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
(match_test "TARGET_SSE_LOAD0_BY_PXOR")
(const_string "TI")
whole SSE registers use APD move to break dependency
chains, otherwise use short move to avoid extra work.
- movaps encodes one byte shorter. */
+ movaps encodes one byte shorter for !TARGET_AVX. */
(eq_attr "alternative" "8")
- (cond
- [(match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_string "V2DF")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+ (const_string "V2DF")
+ (match_test "TARGET_AVX")
+ (const_string "DF")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
]
(const_string "DF"))
/* For architectures resolving dependencies on register
switch (get_attr_mode (insn))
{
case MODE_V2DF:
- if (!TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL)
- return "%vmovapd\t{%1, %0|%0, %1}";
+ return "%vmovapd\t{%1, %0|%0, %1}";
case MODE_V4SF:
return "%vmovaps\t{%1, %0|%0, %1}";
(const_string "V4SF")
(const_string "V2SF"))
- /* xorps is one byte shorter. */
+ /* xorps is one byte shorter for !TARGET_AVX. */
(eq_attr "alternative" "5,9")
- (cond [(match_test "optimize_function_for_size_p (cfun)")
+ (cond [(match_test "TARGET_AVX")
+ (const_string "V2DF")
+ (match_test "optimize_function_for_size_p (cfun)")
(const_string "V4SF")
(match_test "TARGET_SSE_LOAD0_BY_PXOR")
(const_string "TI")
whole SSE registers use APD move to break dependency
chains, otherwise use short move to avoid extra work.
- movaps encodes one byte shorter. */
+ movaps encodes one byte shorter for !TARGET_AVX. */
(eq_attr "alternative" "6,10")
- (cond
- [(match_test "optimize_function_for_size_p (cfun)")
- (const_string "V4SF")
- (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_string "V2DF")
+ (cond [(match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
+ (const_string "V4SF")
+ (match_test "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+ (const_string "V2DF")
+ (match_test "TARGET_AVX")
+ (const_string "DF")
+ (match_test "optimize_function_for_size_p (cfun)")
+ (const_string "V4SF")
]
(const_string "DF"))
+
/* For architectures resolving dependencies on register
parts we may avoid extra work to zero out upper part
of register. */
(cond [(eq_attr "alternative" "3,4,9,10")
(const_string "SI")
(eq_attr "alternative" "5")
- (if_then_else
- (and (and (match_test "TARGET_SSE_LOAD0_BY_PXOR")
- (match_test "TARGET_SSE2"))
- (not (match_test "optimize_function_for_size_p (cfun)")))
- (const_string "TI")
- (const_string "V4SF"))
+ (cond [(match_test "TARGET_AVX")
+ (const_string "V4SF")
+ (ior (not (match_test "TARGET_SSE2"))
+ (match_test "optimize_function_for_size_p (cfun)"))
+ (const_string "V4SF")
+ (match_test "TARGET_SSE_LOAD0_BY_PXOR")
+ (const_string "TI")
+ ]
+ (const_string "V4SF"))
+
/* For architectures resolving dependencies on
whole SSE registers use APS move to break dependency
chains, otherwise use short move to avoid extra work.
(const_string "SF")))])
(define_split
- [(set (match_operand 0 "any_fp_register_operand" "")
- (match_operand 1 "memory_operand" ""))]
+ [(set (match_operand 0 "any_fp_register_operand")
+ (match_operand 1 "memory_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
})
(define_split
- [(set (match_operand 0 "any_fp_register_operand" "")
- (float_extend (match_operand 1 "memory_operand" "")))]
+ [(set (match_operand 0 "any_fp_register_operand")
+ (float_extend (match_operand 1 "memory_operand")))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Split the load of -0.0 or -1.0 into fldz;fchs or fld1;fchs sequence
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (match_operand:X87MODEF 1 "immediate_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (match_operand:X87MODEF 1 "immediate_operand"))]
"reload_completed
&& (standard_80387_constant_p (operands[1]) == 8
|| standard_80387_constant_p (operands[1]) == 9)"
})
(define_split
- [(set (match_operand 0 "nonimmediate_operand" "")
- (match_operand 1 "general_operand" ""))]
+ [(set (match_operand 0 "nonimmediate_operand")
+ (match_operand 1 "general_operand"))]
"reload_completed
&& (GET_MODE (operands[0]) == TFmode
|| GET_MODE (operands[0]) == XFmode
;; Zero extension instructions
(define_expand "zero_extendsidi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
- ""
-{
- if (!TARGET_64BIT)
- {
- emit_insn (gen_zero_extendsidi2_1 (operands[0], operands[1]));
- DONE;
- }
-})
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
(define_insn "*zero_extendsidi2_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x")
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=r ,o,?*Ym,?*y,?*Yi,?*x")
(zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
+ (match_operand:SI 1 "x86_64_zext_general_operand"
+ "rmWz,0,r ,m ,r ,m")))]
"TARGET_64BIT"
"@
mov{l}\t{%1, %k0|%k0, %1}
movd\t{%1, %0|%0, %1}
%vmovd\t{%1, %0|%0, %1}
%vmovd\t{%1, %0|%0, %1}"
- [(set_attr "type" "imovx,imov,mmxmov,mmxmov,ssemov,ssemov")
+ [(set_attr "type" "imovx,multi,mmxmov,mmxmov,ssemov,ssemov")
(set_attr "prefix" "orig,*,orig,orig,maybe_vex,maybe_vex")
(set_attr "prefix_0f" "0,*,*,*,*,*")
- (set_attr "mode" "SI,DI,DI,DI,TI,TI")])
-
-(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (zero_extend:DI (match_dup 0)))]
- "TARGET_64BIT"
- [(set (match_dup 4) (const_int 0))]
- "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
+ (set_attr "mode" "SI,SI,DI,DI,TI,TI")])
-;; %%% Kill me once multi-word ops are sane.
-(define_insn "zero_extendsidi2_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x")
- (zero_extend:DI
- (match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
- (clobber (reg:CC FLAGS_REG))]
+(define_insn "*zero_extendsidi2"
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=ro,?r,?o,?*Ym,?*y,?*Yi,?*x")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
+ "0 ,rm,r ,r ,m ,r ,m")))]
"!TARGET_64BIT"
"@
#
(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (zero_extend:DI (match_operand:SI 1 "memory_operand")))]
+ "reload_completed"
+ [(set (match_dup 4) (const_int 0))]
+ "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
+
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI (match_operand:SI 1 "register_operand")))]
"!TARGET_64BIT && reload_completed
+ && !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))
&& true_regnum (operands[0]) == true_regnum (operands[1])"
[(set (match_dup 4) (const_int 0))]
"split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);")
(define_split
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))
&& !(MMX_REG_P (operands[0]) || SSE_REG_P (operands[0]))"
[(set (match_dup 3) (match_dup 1))
(set (match_dup 4) (const_int 0))]
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
-(define_expand "zero_extendhisi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
+(define_expand "zero_extend<mode>si2"
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extend:SI (match_operand:SWI12 1 "nonimmediate_operand")))]
""
{
if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
{
- operands[1] = force_reg (HImode, operands[1]);
- emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ emit_insn (gen_zero_extend<mode>si2_and (operands[0], operands[1]));
DONE;
}
})
-(define_insn_and_split "zero_extendhisi2_and"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
+(define_insn_and_split "zero_extend<mode>si2_and"
+ [(set (match_operand:SI 0 "register_operand" "=r,?&<r>")
+ (zero_extend:SI
+ (match_operand:SWI12 1 "nonimmediate_operand" "0,<r>m")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
"#"
"&& reload_completed"
- [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
+ [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
- ""
+{
+ if (true_regnum (operands[0]) != true_regnum (operands[1]))
+ {
+ ix86_expand_clear (operands[0]);
+
+ gcc_assert (!TARGET_PARTIAL_REG_STALL);
+ emit_insn (gen_movstrict<mode>
+ (gen_lowpart (<MODE>mode, operands[0]), operands[1]));
+ DONE;
+ }
+
+ operands[2] = GEN_INT (GET_MODE_MASK (<MODE>mode));
+}
[(set_attr "type" "alu1")
(set_attr "mode" "SI")])
-(define_insn "*zero_extendhisi2_movzwl"
+(define_insn "*zero_extend<mode>si2"
[(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
- "!TARGET_ZERO_EXTEND_WITH_AND
- || optimize_function_for_size_p (cfun)"
- "movz{wl|x}\t{%1, %0|%0, %1}"
+ (zero_extend:SI
+ (match_operand:SWI12 1 "nonimmediate_operand" "<r>m")))]
+ "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))"
+ "movz{<imodesuffix>l|x}\t{%1, %0|%0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
-(define_expand "zero_extendqi<mode>2"
- [(parallel
- [(set (match_operand:SWI24 0 "register_operand" "")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])])
+(define_expand "zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
+ ""
+{
+ if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
+ {
+ operands[1] = force_reg (QImode, operands[1]);
+ emit_insn (gen_zero_extendqihi2_and (operands[0], operands[1]));
+ DONE;
+ }
+})
-(define_insn "*zero_extendqi<mode>2_and"
- [(set (match_operand:SWI24 0 "register_operand" "=r,?&q")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
+(define_insn_and_split "zero_extendqihi2_and"
+ [(set (match_operand:HI 0 "register_operand" "=r,?&q")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
"#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "<MODE>")])
-
-;; When source and destination does not overlap, clear destination
-;; first and then do the movb
-(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
- && ANY_QI_REG_P (operands[0])
- && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
- && !reg_overlap_mentioned_p (operands[0], operands[1])"
- [(set (strict_low_part (match_dup 2)) (match_dup 1))]
+ "&& reload_completed"
+ [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
+ (clobber (reg:CC FLAGS_REG))])]
{
- operands[2] = gen_lowpart (QImode, operands[0]);
- ix86_expand_clear (operands[0]);
-})
+ if (true_regnum (operands[0]) != true_regnum (operands[1]))
+ {
+ ix86_expand_clear (operands[0]);
-(define_insn "*zero_extendqi<mode>2_movzbl_and"
- [(set (match_operand:SWI24 0 "register_operand" "=r,r")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
- "#"
- [(set_attr "type" "imovx,alu1")
- (set_attr "mode" "<MODE>")])
+ gcc_assert (!TARGET_PARTIAL_REG_STALL);
+ emit_insn (gen_movstrictqi
+ (gen_lowpart (QImode, operands[0]), operands[1]));
+ DONE;
+ }
-;; For the movzbl case strip only the clobber
-(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
- && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
- [(set (match_dup 0)
- (zero_extend:SWI24 (match_dup 1)))])
+ operands[0] = gen_lowpart (SImode, operands[0]);
+}
+ [(set_attr "type" "alu1")
+ (set_attr "mode" "SI")])
; zero extend to SImode to avoid partial register stalls
-(define_insn "*zero_extendqi<mode>2_movzbl"
- [(set (match_operand:SWI24 0 "register_operand" "=r")
- (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "qm")))]
- "reload_completed
- && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))"
+(define_insn "*zero_extendqihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
+ "!(TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))"
"movz{bl|x}\t{%1, %k0|%k0, %1}"
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
-
-;; Rest is handled by single and.
-(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (zero_extend:SWI24 (match_operand:QI 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && true_regnum (operands[0]) == true_regnum (operands[1])"
- [(parallel [(set (match_dup 0) (and:SWI24 (match_dup 0) (const_int 255)))
- (clobber (reg:CC FLAGS_REG))])])
\f
;; Sign extension instructions
(define_expand "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))]
""
{
if (!TARGET_64BIT)
;; Extend to memory case when source register does die.
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "memory_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_operand:SI 2 "register_operand" ""))]
+ (clobber (match_operand:SI 2 "register_operand"))]
"(reload_completed
&& dead_or_set_p (insn, operands[1])
&& !reg_mentioned_p (operands[1], operands[0]))"
;; Extend to memory case when source register does not die.
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "memory_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_operand:SI 2 "register_operand" ""))]
+ (clobber (match_operand:SI 2 "register_operand"))]
"reload_completed"
[(const_int 0)]
{
;; Extend to register case. Optimize case where source and destination
;; registers match and cases where we can use cltd.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:SI 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))
- (clobber (match_scratch:SI 2 ""))]
+ (clobber (match_scratch:SI 2))]
"reload_completed"
[(const_int 0)]
{
;; %%% Kill these when call knows how to work out a DFmode push earlier.
(define_split
- [(set (match_operand:DF 0 "push_operand" "")
- (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
+ [(set (match_operand:DF 0 "push_operand")
+ (float_extend:DF (match_operand:SF 1 "fp_register_operand")))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
(set (mem:DF (reg:P SP_REG)) (float_extend:DF (match_dup 1)))])
(define_split
- [(set (match_operand:XF 0 "push_operand" "")
- (float_extend:XF (match_operand:MODEF 1 "fp_register_operand" "")))]
+ [(set (match_operand:XF 0 "push_operand")
+ (float_extend:XF (match_operand:MODEF 1 "fp_register_operand")))]
"reload_completed"
[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
(set (mem:XF (reg:P SP_REG)) (float_extend:XF (match_dup 1)))]
"operands[2] = GEN_INT (-GET_MODE_SIZE (XFmode));")
(define_expand "extendsfdf2"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
+ [(set (match_operand:DF 0 "nonimmediate_operand")
+ (float_extend:DF (match_operand:SF 1 "general_operand")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
/* ??? Needed for compress_float_constant since all fp constants
that might lead to ICE on 32bit target. The sequence unlikely combine
anyway. */
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(float_extend:DF
- (match_operand:SF 1 "nonimmediate_operand" "")))]
+ (match_operand:SF 1 "nonimmediate_operand")))]
"TARGET_USE_VECTOR_FP_CONVERTS
&& optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
(set_attr "mode" "SF,XF")])
(define_expand "extend<mode>xf2"
- [(set (match_operand:XF 0 "nonimmediate_operand" "")
- (float_extend:XF (match_operand:MODEF 1 "general_operand" "")))]
+ [(set (match_operand:XF 0 "nonimmediate_operand")
+ (float_extend:XF (match_operand:MODEF 1 "general_operand")))]
"TARGET_80387"
{
/* ??? Needed for compress_float_constant since all fp constants
;; Conversion from DFmode to SFmode.
(define_expand "truncdfsf2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ [(set (match_operand:SF 0 "nonimmediate_operand")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (match_operand:DF 1 "nonimmediate_operand")))]
"TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
that might lead to ICE on 32bit target. The sequence unlikely combine
anyway. */
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))]
+ (match_operand:DF 1 "nonimmediate_operand")))]
"TARGET_USE_VECTOR_FP_CONVERTS
&& optimize_insn_for_speed_p ()
&& reload_completed && SSE_REG_P (operands[0])"
})
(define_expand "truncdfsf2_with_temp"
- [(parallel [(set (match_operand:SF 0 "" "")
- (float_truncate:SF (match_operand:DF 1 "" "")))
- (clobber (match_operand:SF 2 "" ""))])])
+ [(parallel [(set (match_operand:SF 0)
+ (float_truncate:SF (match_operand:DF 1)))
+ (clobber (match_operand:SF 2))])])
(define_insn "*truncdfsf_fast_mixed"
[(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x")
(set_attr "mode" "SF")])
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(float_truncate:SF
- (match_operand:DF 1 "fp_register_operand" "")))
- (clobber (match_operand 2 "" ""))]
+ (match_operand:DF 1 "fp_register_operand")))
+ (clobber (match_operand 2))]
"reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))]
;; Conversion from XFmode to {SF,DF}mode
(define_expand "truncxf<mode>2"
- [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand" "")
+ [(parallel [(set (match_operand:MODEF 0 "nonimmediate_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
+ (match_operand:XF 1 "register_operand")))
(clobber (match_dup 2))])]
"TARGET_80387"
{
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
- (clobber (match_operand:MODEF 2 "memory_operand" ""))]
+ (match_operand:XF 1 "register_operand")))
+ (clobber (match_operand:MODEF 2 "memory_operand"))]
"TARGET_80387 && reload_completed"
[(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:MODEF 0 "memory_operand" "")
+ [(set (match_operand:MODEF 0 "memory_operand")
(float_truncate:MODEF
- (match_operand:XF 1 "register_operand" "")))
- (clobber (match_operand:MODEF 2 "memory_operand" ""))]
+ (match_operand:XF 1 "register_operand")))
+ (clobber (match_operand:MODEF 2 "memory_operand"))]
"TARGET_80387"
[(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))])
\f
;; Signed conversion to DImode.
(define_expand "fix_truncxfdi2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:XF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand")
+ (fix:DI (match_operand:XF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
{
})
(define_expand "fix_trunc<mode>di2"
- [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (fix:DI (match_operand:MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:DI 0 "nonimmediate_operand")
+ (fix:DI (match_operand:MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
{
;; Signed conversion to SImode.
(define_expand "fix_truncxfsi2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:XF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
+ (fix:SI (match_operand:XF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387"
{
})
(define_expand "fix_trunc<mode>si2"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (fix:SI (match_operand:MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
+ (fix:SI (match_operand:MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
{
;; Signed conversion to HImode.
(define_expand "fix_trunc<mode>hi2"
- [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
+ [(parallel [(set (match_operand:HI 0 "nonimmediate_operand")
+ (fix:HI (match_operand:X87MODEF 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_80387
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
(define_expand "fixuns_trunc<mode>si2"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unsigned_fix:SI
- (match_operand:MODEF 1 "nonimmediate_operand" "")))
+ (match_operand:MODEF 1 "nonimmediate_operand")))
(use (match_dup 2))
- (clobber (match_scratch:<ssevecmode> 3 ""))
- (clobber (match_scratch:<ssevecmode> 4 ""))])]
+ (clobber (match_scratch:<ssevecmode> 3))
+ (clobber (match_scratch:<ssevecmode> 4))])]
"!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
{
enum machine_mode mode = <MODE>mode;
(define_expand "fixuns_trunc<mode>hi2"
[(set (match_dup 2)
- (fix:SI (match_operand:MODEF 1 "nonimmediate_operand" "")))
- (set (match_operand:HI 0 "nonimmediate_operand" "")
+ (fix:SI (match_operand:MODEF 1 "nonimmediate_operand")))
+ (set (match_operand:HI 0 "nonimmediate_operand")
(subreg:HI (match_dup 2) 0))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"operands[2] = gen_reg_rtx (SImode);")
;; Shorten x87->SSE reload sequences of fix_trunc?f?i_sse patterns.
(define_peephole2
- [(set (match_operand:MODEF 0 "register_operand" "")
- (match_operand:MODEF 1 "memory_operand" ""))
- (set (match_operand:SWI48x 2 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
+ (match_operand:MODEF 1 "memory_operand"))
+ (set (match_operand:SWI48x 2 "register_operand")
(fix:SWI48x (match_dup 0)))]
"TARGET_SHORTEN_X87_SSE
&& !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
;; Avoid vector decoded forms of the instruction.
(define_peephole2
[(match_scratch:DF 2 "x")
- (set (match_operand:SWI48x 0 "register_operand" "")
- (fix:SWI48x (match_operand:DF 1 "memory_operand" "")))]
+ (set (match_operand:SWI48x 0 "register_operand")
+ (fix:SWI48x (match_operand:DF 1 "memory_operand")))]
"TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SWI48x (match_dup 2)))])
(define_peephole2
[(match_scratch:SF 2 "x")
- (set (match_operand:SWI48x 0 "register_operand" "")
- (fix:SWI48x (match_operand:SF 1 "memory_operand" "")))]
+ (set (match_operand:SWI48x 0 "register_operand")
+ (fix:SWI48x (match_operand:SF 1 "memory_operand")))]
"TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SWI48x (match_dup 2)))])
(define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_FISTTP
&& !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI248x 0 "register_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
- (clobber (match_operand:SWI248x 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ [(set (match_operand:SWI248x 0 "register_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
+ (clobber (match_operand:SWI248x 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 2) (fix:SWI248x (match_dup 1)))
(clobber (match_dup 3))])
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:SWI248x 0 "memory_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
- (clobber (match_operand:SWI248x 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ [(set (match_operand:SWI248x 0 "memory_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
+ (clobber (match_operand:SWI248x 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:SWI248x (match_dup 1)))
(clobber (match_dup 3))])])
;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
;; function in i386.c.
(define_insn_and_split "*fix_trunc<mode>_i387_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (fix:SWI248x (match_operand 1 "register_operand" "")))
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (fix:SWI248x (match_operand 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& !TARGET_FISTTP
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (fix:DI (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
(use (match_dup 2))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (fix:DI (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (fix:DI (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
(use (match_dup 2))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (fix:SWI24 (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (fix:SWI24 (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 4) (fix:SWI24 (match_dup 1)))
(use (match_dup 2))
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (fix:SWI24 (match_operand 1 "register_operand" "")))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (fix:SWI24 (match_operand 1 "register_operand")))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 0) (fix:SWI24 (match_dup 1)))
(use (match_dup 2))
;; wants to be able to do this between registers.
(define_expand "floathi<mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "nonimmediate_operand")))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)")
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*floathi<mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "register_operand")))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "register_operand" "")))
- (clobber (match_operand:HI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "register_operand")))
+ (clobber (match_operand:HI 2 "memory_operand"))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:HI 1 "memory_operand" "")))
- (clobber (match_operand:HI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:HI 1 "memory_operand")))
+ (clobber (match_operand:HI 2 "memory_operand"))]
"TARGET_80387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
[(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
(define_expand "float<SWI48x:mode><X87MODEF:mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(float:X87MODEF
- (match_operand:SWI48x 1 "nonimmediate_operand" "")))]
+ (match_operand:SWI48x 1 "nonimmediate_operand")))]
"TARGET_80387
|| ((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)"
;; Pre-reload splitter to add memory clobber to the pattern.
(define_insn_and_split "*float<SWI48x:mode><X87MODEF:mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))]
"((TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& (!((<SWI48x:MODE>mode != DImode || TARGET_64BIT)
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& TARGET_INTER_UNIT_CONVERSIONS
[(set (match_dup 0) (float:MODEF (match_dup 1)))])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:SI 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "register_operand")))
+ (clobber (match_operand:SI 2 "memory_operand"))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "memory_operand" "")))
- (clobber (match_operand:SI 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "memory_operand")))
+ (clobber (match_operand:SI 2 "memory_operand"))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "register_operand")))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
})
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SI 1 "memory_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SI 1 "memory_operand")))]
"TARGET_SSE2 && TARGET_SSE_MATH
&& TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
&& reload_completed
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "nonimmediate_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
(set (match_dup 0) (float:MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:MODEF 0 "register_operand" "")
- (float:MODEF (match_operand:SWI48x 1 "memory_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (float:MODEF (match_operand:SWI48x 1 "memory_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"(<SWI48x:MODE>mode != DImode || TARGET_64BIT)
&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& reload_completed
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "register_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "register_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& reload_completed"
(set (match_dup 0) (float:X87MODEF (match_dup 2)))])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:SWI48x 1 "memory_operand" "")))
- (clobber (match_operand:SWI48x 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:SWI48x 1 "memory_operand")))
+ (clobber (match_operand:SWI48x 2 "memory_operand"))]
"TARGET_80387
&& X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SWI48x:MODE>mode)
&& reload_completed"
(set_attr "fp_int_src" "true")])
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:DI 1 "register_operand" "")))
- (clobber (match_scratch:V4SI 3 ""))
- (clobber (match_scratch:V4SI 4 ""))
- (clobber (match_operand:DI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:DI 1 "register_operand")))
+ (clobber (match_scratch:V4SI 3))
+ (clobber (match_scratch:V4SI 4))
+ (clobber (match_operand:DI 2 "memory_operand"))]
"TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
})
(define_split
- [(set (match_operand:X87MODEF 0 "fp_register_operand" "")
- (float:X87MODEF (match_operand:DI 1 "memory_operand" "")))
- (clobber (match_scratch:V4SI 3 ""))
- (clobber (match_scratch:V4SI 4 ""))
- (clobber (match_operand:DI 2 "memory_operand" ""))]
+ [(set (match_operand:X87MODEF 0 "fp_register_operand")
+ (float:X87MODEF (match_operand:DI 1 "memory_operand")))
+ (clobber (match_scratch:V4SI 3))
+ (clobber (match_scratch:V4SI 4))
+ (clobber (match_operand:DI 2 "memory_operand"))]
"TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
&& !TARGET_64BIT && optimize_function_for_speed_p (cfun)
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "register_operand" "")))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch:SI 3 ""))]
+ (match_operand:SI 1 "register_operand")))
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
"operands[1] = simplify_gen_subreg (DImode, operands[1], SImode, 0);")
(define_split
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "memory_operand" "")))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch:SI 3 ""))]
+ (match_operand:SI 1 "memory_operand")))
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch:SI 3))]
"!TARGET_64BIT
&& TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE
(define_expand "floatunssi<mode>2"
[(parallel
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(unsigned_float:X87MODEF
- (match_operand:SI 1 "nonimmediate_operand" "")))
+ (match_operand:SI 1 "nonimmediate_operand")))
(clobber (match_dup 2))
- (clobber (match_scratch:SI 3 ""))])]
+ (clobber (match_scratch:SI 3))])]
"!TARGET_64BIT
&& ((TARGET_80387 && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, DImode)
&& TARGET_SSE)
})
(define_expand "floatunsdisf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:DI 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:SF 0 "register_operand"))
+ (use (match_operand:DI 1 "nonimmediate_operand"))]
"TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:DI 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:DF 0 "register_operand"))
+ (use (match_operand:DI 1 "nonimmediate_operand"))]
"(TARGET_64BIT || TARGET_KEEPS_VECTOR_ALIGNED_STACK)
&& TARGET_SSE2 && TARGET_SSE_MATH"
{
;; Add instructions
(define_expand "add<mode>3"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (plus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (PLUS, <MODE>mode, operands); DONE;")
[(set (match_operand:SI 0 "register_operand" "=r")
(subreg:SI (match_operand:DI 1 "lea_address_operand" "p") 0))]
"TARGET_64BIT"
- "lea{l}\t{%a1, %0|%0, %a1}"
+ "lea{l}\t{%E1, %0|%0, %E1}"
"&& reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
[(const_int 0)]
{
[(set (match_operand:SWI48 0 "register_operand" "=r")
(match_operand:SWI48 1 "lea_address_operand" "p"))]
""
- "lea{<imodesuffix>}\t{%a1, %0|%0, %a1}"
+ "lea{<imodesuffix>}\t{%E1, %0|%0, %E1}"
"reload_completed && ix86_avoid_lea_for_addr (insn, operands)"
[(const_int 0)]
{
(zero_extend:DI
(subreg:SI (match_operand:DI 1 "lea_address_operand" "j") 0)))]
"TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
+ "lea{l}\t{%E1, %k0|%k0, %E1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(zero_extend:DI
(match_operand:SI 1 "lea_address_operand" "j")))]
"TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
+ "lea{l}\t{%E1, %k0|%k0, %E1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(subreg:DI (match_operand:SI 1 "lea_address_operand" "p") 0)
(match_operand:DI 2 "const_32bit_mask" "n")))]
"TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
+ "lea{l}\t{%E1, %k0|%k0, %E1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
(match_operand:DI 1 "lea_address_operand" "p")
(match_operand:DI 2 "const_32bit_mask" "n")))]
"TARGET_64BIT"
- "lea{l}\t{%a1, %k0|%k0, %a1}"
+ "lea{l}\t{%E1, %k0|%k0, %E1}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")])
[(set (attr "type")
(cond [(eq_attr "alternative" "3")
(const_string "lea")
- (match_operand:SWI48 2 "incdec_operand" "")
+ (match_operand:SWI48 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
[(set (attr "type")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
- (match_operand:SI 2 "incdec_operand" "")
+ (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
[(set (attr "type")
(cond [(eq_attr "alternative" "3")
(const_string "lea")
- (match_operand:HI 2 "incdec_operand" "")
+ (match_operand:HI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "HI,HI,HI,SI")])
[(set (attr "type")
(cond [(eq_attr "alternative" "5")
(const_string "lea")
- (match_operand:QI 2 "incdec_operand" "")
+ (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
]
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "QI,QI,QI,SI,SI,SI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 1 "incdec_operand" "")
+ (if_then_else (match_operand:QI 1 "incdec_operand")
(const_string "incdec")
(const_string "alu1")))
(set (attr "memory")
- (if_then_else (match_operand 1 "memory_operand" "")
+ (if_then_else (match_operand 1 "memory_operand")
(const_string "load")
(const_string "none")))
(set_attr "mode" "QI")])
;; Split non destructive adds if we cannot use lea.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (plus:SWI48 (match_operand:SWI48 1 "register_operand" "")
- (match_operand:SWI48 2 "nonmemory_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (plus:SWI48 (match_operand:SWI48 1 "register_operand")
+ (match_operand:SWI48 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && ix86_avoid_lea_for_add (insn, operands)"
[(set (match_dup 0) (match_dup 1))
;; Convert add to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI 0 "register_operand" "")
- (plus:SWI (match_operand:SWI 1 "register_operand" "")
- (match_operand:SWI 2 "<nonmemory_operand>" "")))
+ [(set (match_operand:SWI 0 "register_operand")
+ (plus:SWI (match_operand:SWI 1 "register_operand")
+ (match_operand:SWI 2 "<nonmemory_operand>")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && ix86_lea_for_add_ok (insn, operands)"
[(const_int 0)]
;; Convert add to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "x86_64_nonmemory_operand" ""))))
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "x86_64_nonmemory_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed && ix86_lea_for_add_ok (insn, operands)"
[(set (match_dup 0)
[(set (reg FLAGS_REG)
(compare
(plus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
+ (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>,0"))
(const_int 0)))
- (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m,<r>")
(plus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
}
default:
+ if (which_alternative == 2)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
(define_insn "*addsi_2_zext"
[(set (reg FLAGS_REG)
(compare
- (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
- (match_operand:SI 2 "x86_64_general_operand" "rme"))
+ (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
+ (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, SImode, operands)"
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
if (x86_maybe_negate_const_int (&operands[2], SImode))
return "sub{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(define_insn "*add<mode>_3"
[(set (reg FLAGS_REG)
(compare
- (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>"))
- (match_operand:SWI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:SWI 0 "=<r>"))]
+ (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>,0"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")))
+ (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
"ix86_match_ccmode (insn, CCZmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
(define_insn "*addsi_3_zext"
[(set (reg FLAGS_REG)
(compare
- (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme"))
- (match_operand:SI 1 "nonimmediate_operand" "%0")))
- (set (match_operand:DI 0 "register_operand" "=r")
+ (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+ (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
+ (set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
&& ix86_binary_operator_ok (PLUS, SImode, operands)"
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
if (x86_maybe_negate_const_int (&operands[2], SImode))
return "sub{l}\t{%2, %k0|%k0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:DI 2 "incdec_operand" "")
+ (if_then_else (match_operand:DI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "DI")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:<MODE> 2 "incdec_operand" "")
+ (if_then_else (match_operand:<MODE> 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
[(set (reg FLAGS_REG)
(compare
(plus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "%0")
- (match_operand:SWI 2 "<general_operand>" "<g>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,<r>")
+ (match_operand:SWI 2 "<general_operand>" "<g>,0"))
(const_int 0)))
- (clobber (match_scratch:SWI 0 "=<r>"))]
+ (clobber (match_scratch:SWI 0 "=<r>,<r>"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
}
default:
+ if (which_alternative == 1)
+ {
+ rtx tmp;
+ tmp = operands[1], operands[1] = operands[2], operands[2] = tmp;
+ }
+
+ gcc_assert (rtx_equal_p (operands[0], operands[1]));
if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
(if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
+ (and (eq_attr "type" "alu") (match_operand 2 "const128_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "<MODE>")])
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
}
}
[(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
+ (if_then_else (match_operand:QI 2 "incdec_operand")
(const_string "incdec")
(const_string "alu")))
(set_attr "modrm" "1")
operands[2] = GEN_INT (1 << INTVAL (operands[2]));
- pat = plus_constant (gen_rtx_MULT (mode, operands[1], operands[2]),
+ pat = plus_constant (mode, gen_rtx_MULT (mode, operands[1], operands[2]),
INTVAL (operands[3]));
emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
}
[(set_attr "type" "lea")
(set (attr "mode")
- (if_then_else (match_operand:DI 0 "" "")
+ (if_then_else (match_operand:DI 0)
(const_string "DI")
(const_string "SI")))])
\f
;; Subtract instructions
(define_expand "sub<mode>3"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")
- (match_operand:SDWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (minus:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")
+ (match_operand:SDWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (MINUS, <MODE>mode, operands); DONE;")
(define_expand "<plusminus_insn><mode>3_carry"
[(parallel
- [(set (match_operand:SWI 0 "nonimmediate_operand" "")
+ [(set (match_operand:SWI 0 "nonimmediate_operand")
(plusminus:SWI
- (match_operand:SWI 1 "nonimmediate_operand" "")
+ (match_operand:SWI 1 "nonimmediate_operand")
(plus:SWI (match_operator:SWI 4 "ix86_carry_flag_operator"
- [(match_operand 3 "flags_reg_operand" "")
+ [(match_operand 3 "flags_reg_operand")
(const_int 0)])
- (match_operand:SWI 2 "<general_operand>" ""))))
+ (match_operand:SWI 2 "<general_operand>"))))
(clobber (reg:CC FLAGS_REG))])]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)")
;; The patterns that match these are at the end of this file.
(define_expand "<plusminus_insn>xf3"
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(plusminus:XF
- (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "<plusminus_insn><mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(plusminus:MODEF
- (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ (match_operand:MODEF 1 "register_operand")
+ (match_operand:MODEF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
\f
;; Multiply instructions
(define_expand "mul<mode>3"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(mult:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "<general_operand>" "")))
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "<general_operand>")))
(clobber (reg:CC FLAGS_REG))])])
(define_expand "mulqi3"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(mult:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set (attr "amdfam10_decode")
(cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set_attr "bdver1_decode" "direct")
(eq_attr "alternative" "1")
(const_string "vector")
(and (eq_attr "alternative" "2")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set (attr "amdfam10_decode")
(cond [(and (eq_attr "alternative" "0,1")
- (match_operand 1 "memory_operand" ""))
+ (match_operand 1 "memory_operand"))
(const_string "vector")]
(const_string "direct")))
(set_attr "bdver1_decode" "direct")
(set_attr "mode" "QI")])
(define_expand "<u>mul<mode><dwi>3"
- [(parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ [(parallel [(set (match_operand:<DWI> 0 "register_operand")
(mult:<DWI>
(any_extend:<DWI>
- (match_operand:DWIH 1 "nonimmediate_operand" ""))
+ (match_operand:DWIH 1 "nonimmediate_operand"))
(any_extend:<DWI>
- (match_operand:DWIH 2 "register_operand" ""))))
+ (match_operand:DWIH 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))])])
(define_expand "<u>mulqihi3"
- [(parallel [(set (match_operand:HI 0 "register_operand" "")
+ [(parallel [(set (match_operand:HI 0 "register_operand")
(mult:HI
(any_extend:HI
- (match_operand:QI 1 "nonimmediate_operand" ""))
+ (match_operand:QI 1 "nonimmediate_operand"))
(any_extend:HI
- (match_operand:QI 2 "register_operand" ""))))
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH")
(set_attr "mode" "SI")])
(define_insn "*umul<mode><dwi>3_1"
- [(set (match_operand:<DWI> 0 "register_operand" "=A,r")
+ [(set (match_operand:<DWI> 0 "register_operand" "=r,A")
(mult:<DWI>
(zero_extend:<DWI>
- (match_operand:DWIH 1 "nonimmediate_operand" "%0,d"))
+ (match_operand:DWIH 1 "nonimmediate_operand" "%d,0"))
(zero_extend:<DWI>
(match_operand:DWIH 2 "nonimmediate_operand" "rm,rm"))))
(clobber (reg:CC FLAGS_REG))]
"!(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
- mul{<imodesuffix>}\t%2
- #"
- [(set_attr "isa" "*,bmi2")
- (set_attr "type" "imul,imulx")
- (set_attr "length_immediate" "0,*")
+ #
+ mul{<imodesuffix>}\t%2"
+ [(set_attr "isa" "bmi2,*")
+ (set_attr "type" "imulx,imul")
+ (set_attr "length_immediate" "*,0")
(set (attr "athlon_decode")
- (cond [(eq_attr "alternative" "0")
+ (cond [(eq_attr "alternative" "1")
(if_then_else (eq_attr "cpu" "athlon")
(const_string "vector")
(const_string "double"))]
(const_string "*")))
- (set_attr "amdfam10_decode" "double,*")
- (set_attr "bdver1_decode" "direct,*")
- (set_attr "prefix" "orig,vex")
+ (set_attr "amdfam10_decode" "*,double")
+ (set_attr "bdver1_decode" "*,direct")
+ (set_attr "prefix" "vex,orig")
(set_attr "mode" "<MODE>")])
;; Convert mul to the mulx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:<DWI> 0 "register_operand" "")
+ [(set (match_operand:<DWI> 0 "register_operand")
(mult:<DWI>
(zero_extend:<DWI>
- (match_operand:DWIH 1 "register_operand" ""))
+ (match_operand:DWIH 1 "register_operand"))
(zero_extend:<DWI>
- (match_operand:DWIH 2 "nonimmediate_operand" ""))))
+ (match_operand:DWIH 2 "nonimmediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed
&& true_regnum (operands[1]) == DX_REG"
(set_attr "mode" "QI")])
(define_expand "<s>mul<mode>3_highpart"
- [(parallel [(set (match_operand:SWI48 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI48 0 "register_operand")
(truncate:SWI48
(lshiftrt:<DWI>
(mult:<DWI>
(any_extend:<DWI>
- (match_operand:SWI48 1 "nonimmediate_operand" ""))
+ (match_operand:SWI48 1 "nonimmediate_operand"))
(any_extend:<DWI>
- (match_operand:SWI48 2 "register_operand" "")))
+ (match_operand:SWI48 2 "register_operand")))
(match_dup 4))))
- (clobber (match_scratch:SWI48 3 ""))
+ (clobber (match_scratch:SWI48 3))
(clobber (reg:CC FLAGS_REG))])]
""
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
;; The patterns that match these are at the end of this file.
(define_expand "mulxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ [(set (match_operand:XF 0 "register_operand")
+ (mult:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "mul<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "")
- (mult:MODEF (match_operand:MODEF 1 "register_operand" "")
- (match_operand:MODEF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:MODEF 0 "register_operand")
+ (mult:MODEF (match_operand:MODEF 1 "register_operand")
+ (match_operand:MODEF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
\f
;; The patterns that match these are at the end of this file.
(define_expand "divxf3"
- [(set (match_operand:XF 0 "register_operand" "")
- (div:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))]
+ [(set (match_operand:XF 0 "register_operand")
+ (div:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))]
"TARGET_80387")
(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "")
- (div:DF (match_operand:DF 1 "register_operand" "")
- (match_operand:DF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:DF 0 "register_operand")
+ (div:DF (match_operand:DF 1 "register_operand")
+ (match_operand:DF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
|| (TARGET_SSE2 && TARGET_SSE_MATH)")
(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand" "")
- (div:SF (match_operand:SF 1 "register_operand" "")
- (match_operand:SF 2 "nonimmediate_operand" "")))]
+ [(set (match_operand:SF 0 "register_operand")
+ (div:SF (match_operand:SF 1 "register_operand")
+ (match_operand:SF 2 "nonimmediate_operand")))]
"(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
|| TARGET_SSE_MATH"
{
;; Divmod instructions.
(define_expand "divmod<mode>4"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(div:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "nonimmediate_operand" "")))
- (set (match_operand:SWIM248 3 "register_operand" "")
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "nonimmediate_operand")))
+ (set (match_operand:SWIM248 3 "register_operand")
(mod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
;; else
;; use original integer divide
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (div:SWI48 (match_operand:SWI48 2 "register_operand" "")
- (match_operand:SWI48 3 "nonimmediate_operand" "")))
- (set (match_operand:SWI48 1 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
+ (div:SWI48 (match_operand:SWI48 2 "register_operand")
+ (match_operand:SWI48 3 "nonimmediate_operand")))
+ (set (match_operand:SWI48 1 "register_operand")
(mod:SWI48 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_8BIT_IDIV
(set_attr "mode" "<MODE>")])
(define_expand "divmodqi4"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(div:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
- (set (match_operand:QI 3 "register_operand" "")
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
+ (set (match_operand:QI 3 "register_operand")
(mod:QI (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
(set_attr "mode" "QI")])
(define_expand "udivmod<mode>4"
- [(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWIM248 0 "register_operand")
(udiv:SWIM248
- (match_operand:SWIM248 1 "register_operand" "")
- (match_operand:SWIM248 2 "nonimmediate_operand" "")))
- (set (match_operand:SWIM248 3 "register_operand" "")
+ (match_operand:SWIM248 1 "register_operand")
+ (match_operand:SWIM248 2 "nonimmediate_operand")))
+ (set (match_operand:SWIM248 3 "register_operand")
(umod:SWIM248 (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])])
;; else
;; use original integer divide
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "")
- (match_operand:SWI48 3 "nonimmediate_operand" "")))
- (set (match_operand:SWI48 1 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
+ (udiv:SWI48 (match_operand:SWI48 2 "register_operand")
+ (match_operand:SWI48 3 "nonimmediate_operand")))
+ (set (match_operand:SWI48 1 "register_operand")
(umod:SWI48 (match_dup 2) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_8BIT_IDIV
(set_attr "mode" "<MODE>")])
(define_expand "udivmodqi4"
- [(parallel [(set (match_operand:QI 0 "register_operand" "")
+ [(parallel [(set (match_operand:QI 0 "register_operand")
(udiv:QI
- (match_operand:QI 1 "register_operand" "")
- (match_operand:QI 2 "nonimmediate_operand" "")))
- (set (match_operand:QI 3 "register_operand" "")
+ (match_operand:QI 1 "register_operand")
+ (match_operand:QI 2 "nonimmediate_operand")))
+ (set (match_operand:QI 3 "register_operand")
(umod:QI (match_dup 1) (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_QIMODE_MATH"
(define_expand "testsi_ccno_1"
[(set (reg:CCNO FLAGS_REG)
(compare:CCNO
- (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "x86_64_nonmemory_operand" ""))
+ (and:SI (match_operand:SI 0 "nonimmediate_operand")
+ (match_operand:SI 1 "x86_64_nonmemory_operand"))
(const_int 0)))])
(define_expand "testqi_ccz_1"
[(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
- (match_operand:QI 1 "nonmemory_operand" ""))
+ (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand")
+ (match_operand:QI 1 "nonmemory_operand"))
(const_int 0)))])
(define_expand "testdi_ccno_1"
[(set (reg:CCNO FLAGS_REG)
(compare:CCNO
- (and:DI (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "x86_64_szext_general_operand" ""))
+ (and:DI (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "x86_64_szext_general_operand"))
(const_int 0)))]
"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
(compare:CCNO
(and:SI
(zero_extract:SI
- (match_operand 0 "ext_register_operand" "")
+ (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand 1 "const_int_operand" ""))
+ (match_operand 1 "const_int_operand"))
(const_int 0)))])
(define_insn "*testqi_ext_0"
[(set (reg FLAGS_REG)
(compare (zero_extract:DI
(match_operand 0 "nonimmediate_operand" "rm")
- (match_operand:DI 1 "const_int_operand" "")
- (match_operand:DI 2 "const_int_operand" ""))
+ (match_operand:DI 1 "const_int_operand")
+ (match_operand:DI 2 "const_int_operand"))
(const_int 0)))]
"TARGET_64BIT
&& ix86_match_ccmode (insn, CCNOmode)
[(set (reg FLAGS_REG)
(compare (zero_extract:SI
(match_operand 0 "nonimmediate_operand" "rm")
- (match_operand:SI 1 "const_int_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))
+ (match_operand:SI 1 "const_int_operand")
+ (match_operand:SI 2 "const_int_operand"))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)
&& INTVAL (operands[1]) > 0
"#")
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
[(zero_extract
- (match_operand 2 "nonimmediate_operand" "")
- (match_operand 3 "const_int_operand" "")
- (match_operand 4 "const_int_operand" ""))
+ (match_operand 2 "nonimmediate_operand")
+ (match_operand 3 "const_int_operand")
+ (match_operand 4 "const_int_operand"))
(const_int 0)]))]
"ix86_match_ccmode (insn, CCNOmode)"
[(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
;; Do the conversion only post-reload to avoid limiting of the register class
;; to QI regs.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand 2 "register_operand" "")
- (match_operand 3 "const_int_operand" ""))
+ [(and (match_operand 2 "register_operand")
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"reload_completed
&& QI_REG_P (operands[2])
})
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand 2 "nonimmediate_operand" "")
- (match_operand 3 "const_int_operand" ""))
+ [(and (match_operand 2 "nonimmediate_operand")
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"reload_completed
&& GET_MODE (operands[2]) != QImode
;; it should be done with splitters.
(define_expand "and<mode>3"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_szext_operand>" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (and:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
+ (match_operand:SWIM 2 "<general_szext_operand>")))]
""
- "ix86_expand_binary_operator (AND, <MODE>mode, operands); DONE;")
+{
+ enum machine_mode mode = <MODE>mode;
+ rtx (*insn) (rtx, rtx);
+
+ if (CONST_INT_P (operands[2]) && REG_P (operands[0]))
+ {
+ HOST_WIDE_INT ival = INTVAL (operands[2]);
+
+ if (ival == (HOST_WIDE_INT) 0xffffffff)
+ mode = SImode;
+ else if (ival == 0xffff)
+ mode = HImode;
+ else if (ival == 0xff)
+ mode = QImode;
+ }
+
+ if (mode == <MODE>mode)
+ {
+ ix86_expand_binary_operator (AND, <MODE>mode, operands);
+ DONE;
+ }
+
+ if (<MODE>mode == DImode)
+ insn = (mode == SImode)
+ ? gen_zero_extendsidi2
+ : (mode == HImode)
+ ? gen_zero_extendhidi2
+ : gen_zero_extendqidi2;
+ else if (<MODE>mode == SImode)
+ insn = (mode == HImode)
+ ? gen_zero_extendhisi2
+ : gen_zero_extendqisi2;
+ else if (<MODE>mode == HImode)
+ insn = gen_zero_extendqihi2;
+ else
+ gcc_unreachable ();
+
+ emit_insn (insn (operands[0], gen_lowpart (mode, operands[1])));
+ DONE;
+})
(define_insn "*anddi_1"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- {
- enum machine_mode mode;
-
- gcc_assert (CONST_INT_P (operands[2]));
- if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff)
- mode = SImode;
- else if (INTVAL (operands[2]) == 0xffff)
- mode = HImode;
- else
- {
- gcc_assert (INTVAL (operands[2]) == 0xff);
- mode = QImode;
- }
-
- operands[1] = gen_lowpart (mode, operands[1]);
- if (mode == SImode)
- return "mov{l}\t{%1, %k0|%k0, %1}";
- else if (mode == HImode)
- return "movz{wl|x}\t{%1, %k0|%k0, %1}";
- else
- return "movz{bl|x}\t{%1, %k0|%k0, %1}";
- }
+ return "#";
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
(if_then_else
(and (eq_attr "type" "imovx")
(and (match_test "INTVAL (operands[2]) == 0xff")
- (match_operand 1 "ext_QIreg_operand" "")))
+ (match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI,DI,DI,SI")])
(define_insn "*andsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,Ya")
(and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
(match_operand:SI 2 "x86_64_general_operand" "re,rm,L")))
(clobber (reg:CC FLAGS_REG))]
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- {
- enum machine_mode mode;
-
- gcc_assert (CONST_INT_P (operands[2]));
- if (INTVAL (operands[2]) == 0xffff)
- mode = HImode;
- else
- {
- gcc_assert (INTVAL (operands[2]) == 0xff);
- mode = QImode;
- }
-
- operands[1] = gen_lowpart (mode, operands[1]);
- if (mode == HImode)
- return "movz{wl|x}\t{%1, %0|%0, %1}";
- else
- return "movz{bl|x}\t{%1, %0|%0, %1}";
- }
+ return "#";
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
(if_then_else
(and (eq_attr "type" "imovx")
(and (match_test "INTVAL (operands[2]) == 0xff")
- (match_operand 1 "ext_QIreg_operand" "")))
+ (match_operand 1 "ext_QIreg_operand")))
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "*,*,0")
(set_attr "mode" "SI")])
(define_insn "*andhi_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,Ya")
(and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
(match_operand:HI 2 "general_operand" "rn,rm,L")))
(clobber (reg:CC FLAGS_REG))]
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
- gcc_assert (CONST_INT_P (operands[2]));
- gcc_assert (INTVAL (operands[2]) == 0xff);
- return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
+ return "#";
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
-
return "and{w}\t{%2, %0|%0, %2}";
}
}
(set (attr "prefix_rex")
(if_then_else
(and (eq_attr "type" "imovx")
- (match_operand 1 "ext_QIreg_operand" ""))
+ (match_operand 1 "ext_QIreg_operand"))
(const_string "1")
(const_string "*")))
(set_attr "mode" "HI,HI,SI")])
[(set_attr "type" "alu1")
(set_attr "mode" "QI")])
+;; Turn *anddi_1 into *andsi_1_zext if possible.
+(define_split
+ [(set (match_operand:DI 0 "register_operand")
+ (and:DI (subreg:DI (match_operand:SI 1 "register_operand") 0)
+ (match_operand:DI 2 "x86_64_zext_immediate_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+ [(parallel [(set (match_dup 0)
+ (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[2] = gen_lowpart (SImode, operands[2]);")
+
+(define_split
+ [(set (match_operand:SWI248 0 "register_operand")
+ (and:SWI248 (match_operand:SWI248 1 "nonimmediate_operand")
+ (match_operand:SWI248 2 "const_int_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "reload_completed
+ && true_regnum (operands[0]) != true_regnum (operands[1])"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT ival = INTVAL (operands[2]);
+ enum machine_mode mode;
+ rtx (*insn) (rtx, rtx);
+
+ if (ival == (HOST_WIDE_INT) 0xffffffff)
+ mode = SImode;
+ else if (ival == 0xffff)
+ mode = HImode;
+ else
+ {
+ gcc_assert (ival == 0xff);
+ mode = QImode;
+ }
+
+ if (<MODE>mode == DImode)
+ insn = (mode == SImode)
+ ? gen_zero_extendsidi2
+ : (mode == HImode)
+ ? gen_zero_extendhidi2
+ : gen_zero_extendqidi2;
+ else
+ {
+ if (<MODE>mode != SImode)
+ /* Zero extend to SImode to avoid partial register stalls. */
+ operands[0] = gen_lowpart (SImode, operands[0]);
+
+ insn = (mode == HImode)
+ ? gen_zero_extendhisi2
+ : gen_zero_extendqisi2;
+ }
+ emit_insn (insn (operands[0], gen_lowpart (mode, operands[1])));
+ DONE;
+})
+
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(and (match_dup 0)
(const_int -65536)))
(clobber (reg:CC FLAGS_REG))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
(define_split
- [(set (match_operand 0 "ext_register_operand" "")
+ [(set (match_operand 0 "ext_register_operand")
(and (match_dup 0)
(const_int -256)))
(clobber (reg:CC FLAGS_REG))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
- [(set (match_operand 0 "ext_register_operand" "")
+ [(set (match_operand 0 "ext_register_operand")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC FLAGS_REG))]
;; of memory mismatch stalls. We may want to do the splitting for optimizing
;; for size, but that can (should?) be handled by generic code instead.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (and (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (and (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
;; Since AND can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is not set.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (and (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (and (match_operand 1 "general_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
;; If this is considered useful, it should be done with splitters.
(define_expand "<code><mode>3"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")
- (match_operand:SWIM 2 "<general_operand>" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (any_or:SWIM (match_operand:SWIM 1 "nonimmediate_operand")
+ (match_operand:SWIM 2 "<general_operand>")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(set_attr "mode" "QI")])
(define_split
- [(set (match_operand 0 "register_operand" "")
- (any_or (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (any_or (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& QI_REG_P (operands[0])
;; Since OR can be encoded with sign extended immediate, this is only
;; profitable when 7th bit is set.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (any_or (match_operand 1 "general_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (any_or (match_operand 1 "general_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& ANY_QI_REG_P (operands[0])
(compare:CCNO
(xor:SI
(zero_extract:SI
- (match_operand 1 "ext_register_operand" "")
+ (match_operand 1 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand:QI 2 "general_operand" ""))
+ (match_operand:QI 2 "general_operand"))
(const_int 0)))
- (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
+ (set (zero_extract:SI (match_operand 0 "ext_register_operand")
(const_int 8)
(const_int 8))
(xor:SI
;; Negation instructions
(define_expand "neg<mode>2"
- [(set (match_operand:SDWIM 0 "nonimmediate_operand" "")
- (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SDWIM 0 "nonimmediate_operand")
+ (neg:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))]
""
"ix86_expand_unary_operator (NEG, <MODE>mode, operands); DONE;")
;; Changing of sign for FP values is doable using integer unit too.
(define_expand "<code><mode>2"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
- (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "")))]
+ [(set (match_operand:X87MODEF 0 "register_operand")
+ (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand")))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
[(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
(match_operator:X87MODEF 3 "absneg_operator"
[(match_operand:X87MODEF 1 "register_operand" "0,0")]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"#")
(define_expand "<code>tf2"
- [(set (match_operand:TF 0 "register_operand" "")
- (absneg:TF (match_operand:TF 1 "register_operand" "")))]
- "TARGET_SSE2"
+ [(set (match_operand:TF 0 "register_operand")
+ (absneg:TF (match_operand:TF 1 "register_operand")))]
+ "TARGET_SSE"
"ix86_expand_fp_absneg_operator (<CODE>, TFmode, operands); DONE;")
(define_insn "*absnegtf2_sse"
[(match_operand:TF 1 "register_operand" "0,x")]))
(use (match_operand:TF 2 "nonimmediate_operand" "xm,0"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_SSE2"
+ "TARGET_SSE"
"#")
;; Splitters for fp abs and neg.
(define_split
- [(set (match_operand 0 "fp_register_operand" "")
+ [(set (match_operand 0 "fp_register_operand")
(match_operator 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "absneg_operator"
- [(match_operand 1 "register_operand" "")]))
- (use (match_operand 2 "nonimmediate_operand" ""))
+ [(match_operand 1 "register_operand")]))
+ (use (match_operand 2 "nonimmediate_operand"))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
[(set (match_dup 0) (match_dup 3))]
})
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "register_operand")
(match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand:V4SF 2 "" ""))
+ (use (match_operand:V4SF 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "register_operand")
(match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
})
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
- (use (match_operand 2 "" ""))
+ (use (match_operand 2))
(clobber (reg:CC FLAGS_REG))]
"reload_completed"
[(parallel [(set (match_dup 0) (match_dup 1))
(define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
(define_expand "copysign<mode>3"
- [(match_operand:CSGNMODE 0 "register_operand" "")
- (match_operand:CSGNMODE 1 "nonmemory_operand" "")
- (match_operand:CSGNMODE 2 "register_operand" "")]
+ [(match_operand:CSGNMODE 0 "register_operand")
+ (match_operand:CSGNMODE 1 "nonmemory_operand")
+ (match_operand:CSGNMODE 2 "register_operand")]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
+ || (TARGET_SSE && (<MODE>mode == TFmode))"
"ix86_expand_copysign (operands); DONE;")
(define_insn_and_split "copysign<mode>3_const"
(match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
UNSPEC_COPYSIGN))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
+ || (TARGET_SSE && (<MODE>mode == TFmode))"
"#"
"&& reload_completed"
[(const_int 0)]
UNSPEC_COPYSIGN))
(clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
"(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
+ || (TARGET_SSE && (<MODE>mode == TFmode))"
"#")
(define_split
- [(set (match_operand:CSGNMODE 0 "register_operand" "")
+ [(set (match_operand:CSGNMODE 0 "register_operand")
(unspec:CSGNMODE
- [(match_operand:CSGNMODE 2 "register_operand" "")
- (match_operand:CSGNMODE 3 "register_operand" "")
- (match_operand:<CSGNVMODE> 4 "" "")
- (match_operand:<CSGNVMODE> 5 "" "")]
+ [(match_operand:CSGNMODE 2 "register_operand")
+ (match_operand:CSGNMODE 3 "register_operand")
+ (match_operand:<CSGNVMODE> 4)
+ (match_operand:<CSGNVMODE> 5)]
UNSPEC_COPYSIGN))
- (clobber (match_scratch:<CSGNVMODE> 1 ""))]
+ (clobber (match_scratch:<CSGNVMODE> 1))]
"((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode)))
+ || (TARGET_SSE && (<MODE>mode == TFmode)))
&& reload_completed"
[(const_int 0)]
"ix86_split_copysign_var (operands); DONE;")
;; One complement instructions
(define_expand "one_cmpl<mode>2"
- [(set (match_operand:SWIM 0 "nonimmediate_operand" "")
- (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SWIM 0 "nonimmediate_operand")
+ (not:SWIM (match_operand:SWIM 1 "nonimmediate_operand")))]
""
"ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;")
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(not:SWI (match_operand:SWI 3 "nonimmediate_operand" ""))
+ [(not:SWI (match_operand:SWI 3 "nonimmediate_operand"))
(const_int 0)]))
- (set (match_operand:SWI 1 "nonimmediate_operand" "")
+ (set (match_operand:SWI 1 "nonimmediate_operand")
(not:SWI (match_dup 3)))]
"ix86_match_ccmode (insn, CCNOmode)"
[(parallel [(set (match_dup 0)
(set_attr "mode" "SI")])
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(not:SI (match_operand:SI 3 "register_operand" ""))
+ [(not:SI (match_operand:SI 3 "register_operand"))
(const_int 0)]))
- (set (match_operand:DI 1 "register_operand" "")
+ (set (match_operand:DI 1 "register_operand")
(zero_extend:DI (not:SI (match_dup 3))))]
"ix86_match_ccmode (insn, CCNOmode)"
[(parallel [(set (match_dup 0)
;; than 31.
(define_expand "ashl<mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SDWIM 0 "<shift_operand>")
+ (ashift:SDWIM (match_operand:SDWIM 1 "<ashl_input_operand>")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (ASHIFT, <MODE>mode, operands); DONE;")
[(set_attr "type" "multi")])
(define_split
- [(set (match_operand:DWI 0 "register_operand" "")
- (ashift:DWI (match_operand:DWI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ [(set (match_operand:DWI 0 "register_operand")
+ (ashift:DWI (match_operand:DWI 1 "nonmemory_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))]
"(optimize && flag_peephole2) ? epilogue_completed : reload_completed"
[(const_int 0)]
(define_peephole2
[(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (parallel [(set (match_operand:<DWI> 0 "register_operand")
(ashift:<DWI>
- (match_operand:<DWI> 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ (match_operand:<DWI> 1 "nonmemory_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
(define_expand "x86_shift<mode>_adj_1"
[(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
+ (compare:CCZ (and:QI (match_operand:QI 2 "register_operand")
(match_dup 4))
(const_int 0)))
- (set (match_operand:SWI48 0 "register_operand" "")
+ (set (match_operand:SWI48 0 "register_operand")
(if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SWI48 1 "register_operand" "")
+ (match_operand:SWI48 1 "register_operand")
(match_dup 0)))
(set (match_dup 1)
(if_then_else:SWI48 (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SWI48 3 "register_operand" "")
+ (match_operand:SWI48 3 "register_operand")
(match_dup 1)))]
"TARGET_CMOVE"
"operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));")
(define_expand "x86_shift<mode>_adj_2"
- [(use (match_operand:SWI48 0 "register_operand" ""))
- (use (match_operand:SWI48 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
+ [(use (match_operand:SWI48 0 "register_operand"))
+ (use (match_operand:SWI48 1 "register_operand"))
+ (use (match_operand:QI 2 "register_operand"))]
""
{
rtx label = gen_label_rtx ();
(eq_attr "alternative" "2")
(const_string "ishiftx")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (ashift:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(eq_attr "alternative" "2")
(const_string "ishiftx")
(and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 2 "const1_operand" ""))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" ""))))
+ (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(cond [(eq_attr "alternative" "1")
(const_string "lea")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
(cond [(eq_attr "alternative" "2")
(const_string "lea")
(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 1 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 1 "const1_operand"))
(const_string "alu")
]
(const_string "ishift1")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift1")
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; Convert ashift to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "index_register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (ashift (match_operand 1 "index_register_operand")
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"GET_MODE (operands[0]) == GET_MODE (operands[1])
&& reload_completed
;; Convert ashift to the lea pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (ashift:SI (match_operand:SI 1 "index_register_operand" "")
- (match_operand:QI 2 "const_int_operand" ""))))
+ (ashift:SI (match_operand:SI 1 "index_register_operand")
+ (match_operand:QI 2 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
&& true_regnum (operands[0]) != true_regnum (operands[1])"
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 2 "const1_operand" ""))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
}
[(set (attr "type")
(cond [(and (and (match_test "TARGET_DOUBLE_WITH_ADD")
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
+ (match_operand 0 "register_operand"))
+ (match_operand 2 "const1_operand"))
(const_string "alu")
]
(const_string "ishift")))
(if_then_else
(ior (eq_attr "type" "alu")
(and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))))
(const_string "0")
;; See comment above `ashl<mode>3' about how this works.
(define_expand "<shift_insn><mode>3"
- [(set (match_operand:SDWIM 0 "<shift_operand>" "")
- (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SDWIM 0 "<shift_operand>")
+ (any_shiftrt:SDWIM (match_operand:SDWIM 1 "<shift_operand>")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(define_peephole2
[(match_scratch:DWIH 3 "r")
- (parallel [(set (match_operand:<DWI> 0 "register_operand" "")
+ (parallel [(set (match_operand:<DWI> 0 "register_operand")
(any_shiftrt:<DWI>
- (match_operand:<DWI> 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ (match_operand:<DWI> 1 "register_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_dup 3)]
"TARGET_CMOVE"
(define_insn "ashrdi3_cvt"
[(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" "")))
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && INTVAL (operands[2]) == 63
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
(define_insn "ashrsi3_cvt"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" "")))
+ (match_operand:QI 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))]
"INTVAL (operands[2]) == 31
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
[(set (match_operand:DI 0 "register_operand" "=*d,r")
(zero_extend:DI
(ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
- (match_operand:QI 2 "const_int_operand" ""))))
+ (match_operand:QI 2 "const_int_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && INTVAL (operands[2]) == 31
&& (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
(set_attr "mode" "SI")])
(define_expand "x86_shift<mode>_adj_3"
- [(use (match_operand:SWI48 0 "register_operand" ""))
- (use (match_operand:SWI48 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
+ [(use (match_operand:SWI48 0 "register_operand"))
+ (use (match_operand:SWI48 1 "register_operand"))
+ (use (match_operand:QI 2 "register_operand"))]
""
{
rtx label = gen_label_rtx ();
(set_attr "type" "ishift,ishiftx")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(set_attr "type" "ishift,ishiftx")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Convert shift to the shiftx pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "register_operand" ""))))
+ (any_shiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "register_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift1")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "ishift")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
;; Rotate instructions
(define_expand "<rotate_insn>ti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (any_rotate:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:TI 0 "register_operand")
+ (any_rotate:TI (match_operand:TI 1 "register_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
"TARGET_64BIT"
{
if (const_1_to_63_operand (operands[2], VOIDmode))
})
(define_expand "<rotate_insn>di3"
- [(set (match_operand:DI 0 "shiftdi_operand" "")
- (any_rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:DI 0 "shiftdi_operand")
+ (any_rotate:DI (match_operand:DI 1 "shiftdi_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
{
if (TARGET_64BIT)
})
(define_expand "<rotate_insn><mode>3"
- [(set (match_operand:SWIM124 0 "nonimmediate_operand" "")
- (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
+ [(set (match_operand:SWIM124 0 "nonimmediate_operand")
+ (any_rotate:SWIM124 (match_operand:SWIM124 1 "nonimmediate_operand")
+ (match_operand:QI 2 "nonmemory_operand")))]
""
"ix86_expand_binary_operator (<CODE>, <MODE>mode, operands); DONE;")
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "rotate")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)"))))
(const_string "0")
;; Convert rotate to the rotatex pattern to avoid flags dependency.
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
})
(define_split
- [(set (match_operand:SWI48 0 "register_operand" "")
- (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
(set (attr "length_immediate")
(if_then_else
(and (eq_attr "type" "rotate")
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)"))))
(const_string "0")
;; Convert rotate to the rotatex pattern to avoid flags dependency.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" ""))))
+ (rotate:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "immediate_operand" ""))))
+ (rotatert:SI (match_operand:SI 1 "nonimmediate_operand")
+ (match_operand:QI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_BMI2 && reload_completed"
[(set (match_dup 0)
[(set_attr "type" "rotate")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 2 "const1_operand" "")
+ (and (match_operand 2 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
[(set_attr "type" "rotate1")
(set (attr "length_immediate")
(if_then_else
- (and (match_operand 1 "const1_operand" "")
+ (and (match_operand 1 "const1_operand")
(ior (match_test "TARGET_SHIFT1")
(match_test "optimize_function_for_size_p (cfun)")))
(const_string "0")
(set_attr "mode" "QI")])
(define_split
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "register_operand")
(any_rotate:HI (match_dup 0) (const_int 8)))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
;; Bit set / bit test instructions
(define_expand "extv"
- [(set (match_operand:SI 0 "register_operand" "")
- (sign_extract:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const8_operand" "")
- (match_operand:SI 3 "const8_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (sign_extract:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const8_operand")
+ (match_operand:SI 3 "const8_operand")))]
""
{
/* Handle extractions from %ah et al. */
})
(define_expand "extzv"
- [(set (match_operand:SI 0 "register_operand" "")
- (zero_extract:SI (match_operand 1 "ext_register_operand" "")
- (match_operand:SI 2 "const8_operand" "")
- (match_operand:SI 3 "const8_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (zero_extract:SI (match_operand 1 "ext_register_operand")
+ (match_operand:SI 2 "const8_operand")
+ (match_operand:SI 3 "const8_operand")))]
""
{
/* Handle extractions from %ah et al. */
})
(define_expand "insv"
- [(set (zero_extract (match_operand 0 "register_operand" "")
- (match_operand 1 "const_int_operand" "")
- (match_operand 2 "const_int_operand" ""))
- (match_operand 3 "register_operand" ""))]
+ [(set (zero_extract (match_operand 0 "register_operand")
+ (match_operand 1 "const_int_operand")
+ (match_operand 2 "const_int_operand"))
+ (match_operand 3 "register_operand"))]
""
{
rtx (*gen_mov_insv_1) (rtx, rtx);
(define_insn "*btsq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 1))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_insn "*btrq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 0))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_insn "*btcq"
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 1))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && !TARGET_USE_BT"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(const_int 0))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT && !TARGET_USE_BT"
(define_peephole2
[(match_scratch:DI 2 "r")
(parallel [(set (zero_extract:DI
- (match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 0 "register_operand")
(const_int 1)
- (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (match_operand:DI 1 "const_0_to_63_operand"))
(not:DI (zero_extract:DI
(match_dup 0) (const_int 1) (match_dup 1))))
(clobber (reg:CC FLAGS_REG))])]
;; sete %al
(define_split
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ [(set (match_operand:QI 0 "nonimmediate_operand")
(ne:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
"PUT_MODE (operands[1], QImode);")
(define_split
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"))
(ne:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
"PUT_MODE (operands[1], QImode);")
(define_split
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
+ [(set (match_operand:QI 0 "nonimmediate_operand")
(eq:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
})
(define_split
- [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
+ [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand"))
(eq:QI (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0)))]
[(set (pc)
(if_then_else (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
""
"%+j%C1\t%l0"
(if_then_else (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(pc)
- (label_ref (match_operand 0 "" ""))))]
+ (label_ref (match_operand 0))))]
""
"%+j%c1\t%l0"
[(set_attr "type" "ibr")
(if_then_else (ne (match_operator 0 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
[(set (pc)
(if_then_else (eq (match_operator 0 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(const_int 0))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
[(set (pc)
(zero_extend:SI
(match_operand:QI 2 "register_operand" "r")))
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
(and:SI
(match_operand:SI 2 "register_operand" "r")
(match_operand:SI 3 "const_int_operand" "n")))])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
(match_operand:QI 2 "register_operand" "r"))
(const_int 1))
(const_int 0)])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_BT || optimize_function_for_size_p (cfun)"
(match_operand:SI 3 "const_int_operand" "n")) 0))
(const_int 1))
(const_int 0)])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CC FLAGS_REG))]
"(TARGET_USE_BT || optimize_function_for_size_p (cfun))
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
[(match_operand 1 "register_operand" "f")
(match_operand 2 "nonimmediate_operand" "fm")])
(pc)
- (label_ref (match_operand 3 "" ""))))
+ (label_ref (match_operand 3))))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
- (label_ref (match_operand 3 "" ""))
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
[(match_operand 1 "register_operand" "f")
(match_operand 2 "register_operand" "f")])
(pc)
- (label_ref (match_operand 3 "" ""))))
+ (label_ref (match_operand 3))))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 4 "=a"))]
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
[(match_operand 1 "register_operand" "f")
- (match_operand 2 "const0_operand" "")])
- (label_ref (match_operand 3 "" ""))
+ (match_operand 2 "const0_operand")])
+ (label_ref (match_operand 3))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(define_split
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "nonimmediate_operand" "")])
- (match_operand 3 "" "")
- (match_operand 4 "" "")))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "nonimmediate_operand")])
+ (match_operand 3)
+ (match_operand 4)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))]
"reload_completed"
(define_split
[(set (pc)
(if_then_else (match_operator 0 "ix86_fp_comparison_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "general_operand" "")])
- (match_operand 3 "" "")
- (match_operand 4 "" "")))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "general_operand")])
+ (match_operand 3)
+ (match_operand 4)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 5 "=a"))]
[(match_operator 1 "float_operator"
[(match_operand:SWI24 2 "nonimmediate_operand" "m,?r")])
(match_operand 3 "register_operand" "f,f")])
- (label_ref (match_operand 4 "" ""))
+ (label_ref (match_operand 4))
(pc)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(if_then_else
(match_operator 0 "ix86_swapped_fp_comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SWI24 2 "memory_operand" "")])
- (match_operand 3 "register_operand" "")])
- (match_operand 4 "" "")
- (match_operand 5 "" "")))
+ [(match_operand:SWI24 2 "memory_operand")])
+ (match_operand 3 "register_operand")])
+ (match_operand 4)
+ (match_operand 5)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 6 "=a"))]
(if_then_else
(match_operator 0 "ix86_swapped_fp_comparison_operator"
[(match_operator 1 "float_operator"
- [(match_operand:SWI24 2 "register_operand" "")])
- (match_operand 3 "register_operand" "")])
- (match_operand 4 "" "")
- (match_operand 5 "" "")))
+ [(match_operand:SWI24 2 "register_operand")])
+ (match_operand 3 "register_operand")])
+ (match_operand 4)
+ (match_operand 5)))
(clobber (reg:CCFP FPSR_REG))
(clobber (reg:CCFP FLAGS_REG))
(clobber (match_scratch:HI 6 "=a"))]
(define_insn "jump"
[(set (pc)
- (label_ref (match_operand 0 "" "")))]
+ (label_ref (match_operand 0)))]
""
"jmp\t%l0"
[(set_attr "type" "ibr")
(set_attr "modrm" "0")])
(define_expand "indirect_jump"
- [(set (pc) (match_operand 0 "indirect_branch_operand" ""))])
+ [(set (pc) (match_operand 0 "indirect_branch_operand"))]
+ ""
+{
+ if (TARGET_X32)
+ operands[0] = convert_memory_address (word_mode, operands[0]);
+})
(define_insn "*indirect_jump"
- [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))]
+ [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))]
""
"jmp\t%A0"
[(set_attr "type" "ibr")
(set_attr "length_immediate" "0")])
(define_expand "tablejump"
- [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand" ""))
- (use (label_ref (match_operand 1 "" "")))])]
+ [(parallel [(set (pc) (match_operand 0 "indirect_branch_operand"))
+ (use (label_ref (match_operand 1)))])]
""
{
/* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
OPTAB_DIRECT);
}
- else if (TARGET_X32)
- operands[0] = convert_memory_address (Pmode, operands[0]);
+
+ if (TARGET_X32)
+ operands[0] = convert_memory_address (word_mode, operands[0]);
})
(define_insn "*tablejump_1"
- [(set (pc) (match_operand:P 0 "indirect_branch_operand" "rw"))
- (use (label_ref (match_operand 1 "" "")))]
+ [(set (pc) (match_operand:W 0 "indirect_branch_operand" "rw"))
+ (use (label_ref (match_operand 1)))]
""
"jmp\t%A0"
[(set_attr "type" "ibr")
;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
(define_peephole2
- [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (set (match_operand:QI 1 "register_operand" "")
+ [(set (reg FLAGS_REG) (match_operand 0))
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (set (match_operand 3 "q_regs_operand" "")
+ (set (match_operand 3 "q_regs_operand")
(zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
ix86_expand_clear (operands[3]);
})
-;; Similar, but match zero_extendhisi2_and, which adds a clobber.
-
(define_peephole2
- [(set (reg FLAGS_REG) (match_operand 0 "" ""))
- (set (match_operand:QI 1 "register_operand" "")
+ [(parallel [(set (reg FLAGS_REG) (match_operand 0))
+ (match_operand 4)])
+ (set (match_operand:QI 1 "register_operand")
(match_operator:QI 2 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)]))
- (parallel [(set (match_operand 3 "q_regs_operand" "")
- (zero_extend (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
+ (set (match_operand 3 "q_regs_operand")
+ (zero_extend (match_dup 1)))]
"(peep2_reg_dead_p (3, operands[1])
|| operands_match_p (operands[1], operands[3]))
&& ! reg_overlap_mentioned_p (operands[3], operands[0])"
- [(set (match_dup 4) (match_dup 0))
- (set (strict_low_part (match_dup 5))
+ [(parallel [(set (match_dup 5) (match_dup 0))
+ (match_dup 4)])
+ (set (strict_low_part (match_dup 6))
(match_dup 2))]
{
- operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
- operands[5] = gen_lowpart (QImode, operands[3]);
+ operands[5] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
+ operands[6] = gen_lowpart (QImode, operands[3]);
ix86_expand_clear (operands[3]);
})
-\f
-;; Call instructions.
+
+;; Similar, but match zero extend with andsi3.
+
+(define_peephole2
+ [(set (reg FLAGS_REG) (match_operand 0))
+ (set (match_operand:QI 1 "register_operand")
+ (match_operator:QI 2 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))
+ (parallel [(set (match_operand:SI 3 "q_regs_operand")
+ (and:SI (match_dup 3) (const_int 255)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "REGNO (operands[1]) == REGNO (operands[3])
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+ [(set (match_dup 4) (match_dup 0))
+ (set (strict_low_part (match_dup 5))
+ (match_dup 2))]
+{
+ operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
+ operands[5] = gen_lowpart (QImode, operands[3]);
+ ix86_expand_clear (operands[3]);
+})
+
+(define_peephole2
+ [(parallel [(set (reg FLAGS_REG) (match_operand 0))
+ (match_operand 4)])
+ (set (match_operand:QI 1 "register_operand")
+ (match_operator:QI 2 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)]))
+ (parallel [(set (match_operand 3 "q_regs_operand")
+ (zero_extend (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+ [(parallel [(set (match_dup 5) (match_dup 0))
+ (match_dup 4)])
+ (set (strict_low_part (match_dup 6))
+ (match_dup 2))]
+{
+ operands[5] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
+ operands[6] = gen_lowpart (QImode, operands[3]);
+ ix86_expand_clear (operands[3]);
+})
+\f
+;; Call instructions.
;; The predicates normally associated with named expanders are not properly
;; checked for calls. This is a bug in the generic code, but it isn't that
;; Call subroutine returning no value.
(define_expand "call"
- [(call (match_operand:QI 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
+ [(call (match_operand:QI 0)
+ (match_operand 1))
+ (use (match_operand 2))]
""
{
ix86_expand_call (NULL, operands[0], operands[1],
})
(define_expand "sibcall"
- [(call (match_operand:QI 0 "" "")
- (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))]
+ [(call (match_operand:QI 0)
+ (match_operand 1))
+ (use (match_operand 2))]
""
{
ix86_expand_call (NULL, operands[0], operands[1],
})
(define_insn_and_split "*call_vzeroupper"
- [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
- (match_operand 1 "" ""))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw"))
+ (match_operand 1))
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "call")])
(define_insn "*call"
- [(call (mem:QI (match_operand:P 0 "call_insn_operand" "<c>zw"))
- (match_operand 1 "" ""))]
+ [(call (mem:QI (match_operand:W 0 "call_insn_operand" "<c>zw"))
+ (match_operand 1))]
"!SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
(define_insn_and_split "*call_rex64_ms_sysv_vzeroupper"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
(define_insn "*call_rex64_ms_sysv"
[(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rzw"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
[(set_attr "type" "call")])
(define_insn_and_split "*sibcall_vzeroupper"
- [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
- (unspec [(match_operand 2 "const_int_operand" "")]
+ [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz"))
+ (match_operand 1))
+ (unspec [(match_operand 2 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "call")])
(define_insn "*sibcall"
- [(call (mem:QI (match_operand:P 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))]
+ [(call (mem:QI (match_operand:W 0 "sibcall_insn_operand" "Uz"))
+ (match_operand 1))]
"SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
(define_expand "call_pop"
- [(parallel [(call (match_operand:QI 0 "" "")
- (match_operand:SI 1 "" ""))
+ [(parallel [(call (match_operand:QI 0)
+ (match_operand:SI 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
- (match_operand:SI 3 "" "")))])]
+ (match_operand:SI 3)))])]
"!TARGET_64BIT"
{
ix86_expand_call (NULL, operands[0], operands[1],
(define_insn_and_split "*call_pop_vzeroupper"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
- (match_operand:SI 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
(define_insn "*call_pop"
[(call (mem:QI (match_operand:SI 0 "call_insn_operand" "lzm"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
(define_insn_and_split "*sibcall_pop_vzeroupper"
[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
"#"
(define_insn "*sibcall_pop"
[(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "Uz"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 2 "immediate_operand" "i")))]
;; Call subroutine, returning value in operand 0
(define_expand "call_value"
- [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))]
+ [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand 2)))
+ (use (match_operand 3))]
""
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_expand "sibcall_value"
- [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand 2 "" "")))
- (use (match_operand 3 "" ""))]
+ [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand 2)))
+ (use (match_operand 3))]
""
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_insn_and_split "*call_value_vzeroupper"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
- (match_operand 2 "" "")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ [(set (match_operand 0)
+ (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw"))
+ (match_operand 2)))
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:P 1 "call_insn_operand" "<c>zw"))
- (match_operand 2 "" "")))]
+ [(set (match_operand 0)
+ (call (mem:QI (match_operand:W 1 "call_insn_operand" "<c>zw"))
+ (match_operand 2)))]
"!SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
(define_insn_and_split "*sibcall_value_vzeroupper"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ [(set (match_operand 0)
+ (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz"))
+ (match_operand 2)))
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value"
- [(set (match_operand 0 "" "")
- (call (mem:QI (match_operand:P 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))]
+ [(set (match_operand 0)
+ (call (mem:QI (match_operand:W 1 "sibcall_insn_operand" "Uz"))
+ (match_operand 2)))]
"SIBLING_CALL_P (insn)"
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
(define_insn_and_split "*call_value_rex64_ms_sysv_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
(clobber (reg:TI XMM15_REG))
(clobber (reg:DI SI_REG))
(clobber (reg:DI DI_REG))
- (unspec [(match_operand 3 "const_int_operand" "")]
+ (unspec [(match_operand 3 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value_rex64_ms_sysv"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:DI 1 "call_insn_operand" "rzw"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(const_int 0)] UNSPEC_MS_TO_SYSV_CALL)
(clobber (reg:TI XMM6_REG))
(clobber (reg:TI XMM7_REG))
[(set_attr "type" "callv")])
(define_expand "call_value_pop"
- [(parallel [(set (match_operand 0 "" "")
- (call (match_operand:QI 1 "" "")
- (match_operand:SI 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (match_operand:QI 1)
+ (match_operand:SI 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
- (match_operand:SI 4 "" "")))])]
+ (match_operand:SI 4)))])]
"!TARGET_64BIT"
{
ix86_expand_call (operands[0], operands[1], operands[2],
})
(define_insn_and_split "*call_value_pop_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))
- (unspec [(match_operand 4 "const_int_operand" "")]
+ (unspec [(match_operand 4 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && !SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*call_value_pop"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "call_insn_operand" "lzm"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
[(set_attr "type" "callv")])
(define_insn_and_split "*sibcall_value_pop_vzeroupper"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))
- (unspec [(match_operand 4 "const_int_operand" "")]
+ (unspec [(match_operand 4 "const_int_operand")]
UNSPEC_CALL_NEEDS_VZEROUPPER)]
"TARGET_VZEROUPPER && !TARGET_64BIT && SIBLING_CALL_P (insn)"
"#"
[(set_attr "type" "callv")])
(define_insn "*sibcall_value_pop"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "Uz"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:SI SP_REG)
(plus:SI (reg:SI SP_REG)
(match_operand:SI 3 "immediate_operand" "i")))]
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0)
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1)
+ (match_operand 2)])]
""
{
int i;
})
(define_insn "*memory_blockage"
- [(set (match_operand:BLK 0 "" "")
+ [(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BLOCKAGE))]
""
""
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for PIC code
(define_insn "prologue_use"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_PROLOGUE_USE)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_PROLOGUE_USE)]
""
""
[(set_attr "length" "0")])
[(simple_return)
(unspec [(const_int 0)] UNSPEC_REP)]
"reload_completed"
- "rep\;ret"
+ "rep%; ret"
[(set_attr "length" "2")
(set_attr "atom_unit" "jeu")
(set_attr "length_immediate" "0")
(define_insn "simple_return_pop_internal"
[(simple_return)
- (use (match_operand:SI 0 "const_int_operand" ""))]
+ (use (match_operand:SI 0 "const_int_operand"))]
"reload_completed"
"ret\t%0"
[(set_attr "length" "3")
;; Generate nops. Operand 0 is the number of nops, up to 8.
(define_insn "nops"
- [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand 0 "const_int_operand")]
UNSPECV_NOPS)]
"reload_completed"
{
int num = INTVAL (operands[0]);
- gcc_assert (num >= 1 && num <= 8);
+ gcc_assert (IN_RANGE (num, 1, 8));
while (num--)
fputs ("\tnop\n", asm_out_file);
;; block on K8.
(define_insn "pad"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_ALIGN)]
""
{
#ifdef ASM_OUTPUT_MAX_SKIP_PAD
(define_insn "set_got_labelled"
[(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(label_ref (match_operand 1 "" ""))]
+ (unspec:SI [(label_ref (match_operand 1))]
UNSPEC_SET_GOT))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT"
(define_insn "set_rip_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_SET_RIP))]
+ (unspec:DI [(label_ref (match_operand 1))] UNSPEC_SET_RIP))]
"TARGET_64BIT"
"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
[(set_attr "type" "lea")
(define_insn "set_got_offset_rex64"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI
- [(label_ref (match_operand 1 "" ""))]
+ [(label_ref (match_operand 1))]
UNSPEC_SET_GOT_OFFSET))]
"TARGET_LP64"
"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
"ix86_expand_epilogue (0); DONE;")
(define_expand "eh_return"
- [(use (match_operand 0 "register_operand" ""))]
+ [(use (match_operand 0 "register_operand"))]
""
{
rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
be returning into someone else's stack frame, one word below the
stack address we wish to restore. */
tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
- tmp = plus_constant (tmp, -UNITS_PER_WORD);
+ tmp = plus_constant (Pmode, tmp, -UNITS_PER_WORD);
tmp = gen_rtx_MEM (Pmode, tmp);
emit_move_insn (tmp, ra);
;; In order to support the call/return predictor, we use a return
;; instruction which the middle-end doesn't see.
(define_insn "split_stack_return"
- [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")]
+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand")]
UNSPECV_SPLIT_STACK_RETURN)]
""
{
[(set_attr "atom_unit" "jeu")
(set_attr "modrm" "0")
(set (attr "length")
- (if_then_else (match_operand:SI 0 "const0_operand" "")
+ (if_then_else (match_operand:SI 0 "const0_operand")
(const_int 1)
(const_int 3)))
(set (attr "length_immediate")
- (if_then_else (match_operand:SI 0 "const0_operand" "")
+ (if_then_else (match_operand:SI 0 "const0_operand")
(const_int 0)
(const_int 2)))])
(define_expand "split_stack_space_check"
[(set (pc) (if_then_else
(ltu (minus (reg SP_REG)
- (match_operand 0 "register_operand" ""))
+ (match_operand 0 "register_operand"))
(unspec [(const_int 0)] UNSPEC_STACK_CHECK))
- (label_ref (match_operand 1 "" ""))
+ (label_ref (match_operand 1))
(pc)))]
""
{
(define_expand "ffs<mode>2"
[(set (match_dup 2) (const_int -1))
- (parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ
- (match_operand:SWI48 1 "nonimmediate_operand" "")
- (const_int 0)))
- (set (match_operand:SWI48 0 "register_operand" "")
- (ctz:SWI48 (match_dup 1)))])
+ (parallel [(set (match_dup 3) (match_dup 4))
+ (set (match_operand:SWI48 0 "register_operand")
+ (ctz:SWI48
+ (match_operand:SWI48 1 "nonimmediate_operand")))])
(set (match_dup 0) (if_then_else:SWI48
- (eq (reg:CCZ FLAGS_REG) (const_int 0))
+ (eq (match_dup 3) (const_int 0))
(match_dup 2)
(match_dup 0)))
(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
""
{
+ enum machine_mode flags_mode;
+
if (<MODE>mode == SImode && !TARGET_CMOVE)
{
emit_insn (gen_ffssi2_no_cmove (operands[0], operands [1]));
DONE;
}
+
+ flags_mode = TARGET_BMI ? CCCmode : CCZmode;
+
operands[2] = gen_reg_rtx (<MODE>mode);
+ operands[3] = gen_rtx_REG (flags_mode, FLAGS_REG);
+ operands[4] = gen_rtx_COMPARE (flags_mode, operands[1], const0_rtx);
})
(define_insn_and_split "ffssi2_no_cmove"
"!TARGET_CMOVE"
"#"
"&& reload_completed"
- [(parallel [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (match_dup 1) (const_int 0)))
+ [(parallel [(set (match_dup 4) (match_dup 5))
(set (match_dup 0) (ctz:SI (match_dup 1)))])
(set (strict_low_part (match_dup 3))
- (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
+ (eq:QI (match_dup 4) (const_int 0)))
(parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
(clobber (reg:CC FLAGS_REG))])
(parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
(clobber (reg:CC FLAGS_REG))])]
{
+ enum machine_mode flags_mode = TARGET_BMI ? CCCmode : CCZmode;
+
operands[3] = gen_lowpart (QImode, operands[2]);
+ operands[4] = gen_rtx_REG (flags_mode, FLAGS_REG);
+ operands[5] = gen_rtx_COMPARE (flags_mode, operands[1], const0_rtx);
+
ix86_expand_clear (operands[2]);
})
-(define_insn "*ffs<mode>_1"
+(define_insn "*tzcnt<mode>_1"
+ [(set (reg:CCC FLAGS_REG)
+ (compare:CCC (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+ (const_int 0)))
+ (set (match_operand:SWI48 0 "register_operand" "=r")
+ (ctz:SWI48 (match_dup 1)))]
+ "TARGET_BMI"
+ "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}"
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn "*bsf<mode>_1"
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
(const_int 0)))
{
if (TARGET_BMI)
return "tzcnt{<imodesuffix>}\t{%1, %0|%0, %1}";
- else
- return "bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
+ else if (optimize_function_for_size_p (cfun))
+ ;
+ else if (TARGET_GENERIC)
+ /* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */
+ return "rep%; bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
+
+ return "bsf{<imodesuffix>}\t{%1, %0|%0, %1}";
}
[(set_attr "type" "alu1")
(set_attr "prefix_0f" "1")
- (set (attr "prefix_rep") (symbol_ref "TARGET_BMI"))
+ (set (attr "prefix_rep")
+ (if_then_else
+ (ior (match_test "TARGET_BMI")
+ (and (not (match_test "optimize_function_for_size_p (cfun)"))
+ (match_test "TARGET_GENERIC")))
+ (const_string "1")
+ (const_string "0")))
(set_attr "mode" "<MODE>")])
(define_expand "clz<mode>2"
[(parallel
- [(set (match_operand:SWI248 0 "register_operand" "")
+ [(set (match_operand:SWI248 0 "register_operand")
(minus:SWI248
(match_dup 2)
- (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" ""))))
+ (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand"))))
(clobber (reg:CC FLAGS_REG))])
(parallel
[(set (match_dup 0) (xor:SWI248 (match_dup 0) (match_dup 2)))
(set_attr "type" "bitmanip")
(set_attr "mode" "SI")])
-(define_expand "bswap<mode>2"
- [(set (match_operand:SWI48 0 "register_operand" "")
- (bswap:SWI48 (match_operand:SWI48 1 "register_operand" "")))]
+(define_expand "bswapdi2"
+ [(set (match_operand:DI 0 "register_operand")
+ (bswap:DI (match_operand:DI 1 "nonimmediate_operand")))]
+ ""
+{
+ if (TARGET_64BIT && !TARGET_MOVBE)
+ operands[1] = force_reg (DImode, operands[1]);
+})
+
+(define_insn_and_split "*bswapdi2_doubleword"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
+ (bswap:DI
+ (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
+ "!TARGET_64BIT
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 2)
+ (bswap:SI (match_dup 1)))
+ (set (match_dup 0)
+ (bswap:SI (match_dup 3)))]
+{
+ split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);
+
+ if (REG_P (operands[0]) && REG_P (operands[1]))
+ {
+ emit_insn (gen_swapsi (operands[0], operands[2]));
+ emit_insn (gen_bswapsi2 (operands[0], operands[0]));
+ emit_insn (gen_bswapsi2 (operands[2], operands[2]));
+ DONE;
+ }
+
+ if (!TARGET_MOVBE)
+ {
+ if (MEM_P (operands[0]))
+ {
+ emit_insn (gen_bswapsi2 (operands[3], operands[3]));
+ emit_insn (gen_bswapsi2 (operands[1], operands[1]));
+
+ emit_move_insn (operands[0], operands[3]);
+ emit_move_insn (operands[2], operands[1]);
+ }
+ if (MEM_P (operands[1]))
+ {
+ emit_move_insn (operands[2], operands[1]);
+ emit_move_insn (operands[0], operands[3]);
+
+ emit_insn (gen_bswapsi2 (operands[2], operands[2]));
+ emit_insn (gen_bswapsi2 (operands[0], operands[0]));
+ }
+ DONE;
+ }
+})
+
+(define_expand "bswapsi2"
+ [(set (match_operand:SI 0 "register_operand")
+ (bswap:SI (match_operand:SI 1 "nonimmediate_operand")))]
""
{
- if (<MODE>mode == SImode && !(TARGET_BSWAP || TARGET_MOVBE))
+ if (TARGET_MOVBE)
+ ;
+ else if (TARGET_BSWAP)
+ operands[1] = force_reg (SImode, operands[1]);
+ else
{
rtx x = operands[0];
(set_attr "prefix_extra" "*,1,1")
(set_attr "mode" "<MODE>")])
-(define_insn "*bswap<mode>2_1"
+(define_insn "*bswap<mode>2"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(bswap:SWI48 (match_operand:SWI48 1 "register_operand" "0")))]
"TARGET_BSWAP"
(set_attr "mode" "HI")])
(define_expand "paritydi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (parity:DI (match_operand:DI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (parity:DI (match_operand:DI 1 "register_operand")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
})
(define_expand "paritysi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (parity:SI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (parity:SI (match_operand:SI 1 "register_operand")))]
"! TARGET_POPCNT"
{
rtx scratch = gen_reg_rtx (QImode);
[(set (match_operand:SI 0 "register_operand" "=a")
(unspec:SI
[(match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "tls_symbolic_operand" "")
- (match_operand:SI 3 "constant_call_address_operand" "z")]
+ (match_operand 2 "tls_symbolic_operand")
+ (match_operand 3 "constant_call_address_operand" "z")]
UNSPEC_TLS_GD))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
"!TARGET_64BIT && TARGET_GNU_TLS"
{
output_asm_insn
- ("lea{l}\t{%a2@tlsgd(,%1,1), %0|%0, %a2@tlsgd[%1*1]}", operands);
+ ("lea{l}\t{%E2@tlsgd(,%1,1), %0|%0, %E2@tlsgd[%1*1]}", operands);
if (TARGET_SUN_TLS)
#ifdef HAVE_AS_IX86_TLSGDPLT
return "call\t%a2@tlsgdplt";
(define_expand "tls_global_dynamic_32"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (unspec:SI [(match_operand:SI 2 "register_operand" "")
- (match_operand:SI 1 "tls_symbolic_operand" "")
- (match_operand:SI 3 "constant_call_address_operand" "")]
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec:SI [(match_operand:SI 2 "register_operand")
+ (match_operand 1 "tls_symbolic_operand")
+ (match_operand 3 "constant_call_address_operand")]
UNSPEC_TLS_GD))
- (clobber (match_scratch:SI 4 ""))
- (clobber (match_scratch:SI 5 ""))
+ (clobber (match_scratch:SI 4))
+ (clobber (match_scratch:SI 5))
(clobber (reg:CC FLAGS_REG))])])
-(define_insn "*tls_global_dynamic_64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (call:DI
- (mem:QI (match_operand:DI 2 "constant_call_address_operand" "z"))
- (match_operand:DI 3 "" "")))
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
- UNSPEC_TLS_GD)]
+(define_insn "*tls_global_dynamic_64_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=a")
+ (call:P
+ (mem:QI (match_operand 2 "constant_call_address_operand" "z"))
+ (match_operand 3)))
+ (unspec:P [(match_operand 1 "tls_symbolic_operand")]
+ UNSPEC_TLS_GD)]
"TARGET_64BIT"
{
if (!TARGET_X32)
fputs (ASM_BYTE "0x66\n", asm_out_file);
output_asm_insn
- ("lea{q}\t{%a1@tlsgd(%%rip), %%rdi|rdi, %a1@tlsgd[rip]}", operands);
+ ("lea{q}\t{%E1@tlsgd(%%rip), %%rdi|rdi, %E1@tlsgd[rip]}", operands);
fputs (ASM_SHORT "0x6666\n", asm_out_file);
fputs ("\trex64\n", asm_out_file);
if (TARGET_SUN_TLS)
(set (attr "length")
(symbol_ref "TARGET_X32 ? 15 : 16"))])
-(define_expand "tls_global_dynamic_64"
+(define_expand "tls_global_dynamic_64_<mode>"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (call:DI
- (mem:QI (match_operand:DI 2 "constant_call_address_operand" ""))
+ [(set (match_operand:P 0 "register_operand")
+ (call:P
+ (mem:QI (match_operand 2 "constant_call_address_operand"))
(const_int 0)))
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
- UNSPEC_TLS_GD)])])
+ (unspec:P [(match_operand 1 "tls_symbolic_operand")]
+ UNSPEC_TLS_GD)])]
+ "TARGET_64BIT")
(define_insn "*tls_local_dynamic_base_32_gnu"
[(set (match_operand:SI 0 "register_operand" "=a")
(unspec:SI
[(match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "constant_call_address_operand" "z")]
+ (match_operand 2 "constant_call_address_operand" "z")]
UNSPEC_TLS_LD_BASE))
(clobber (match_scratch:SI 3 "=d"))
(clobber (match_scratch:SI 4 "=c"))
(define_expand "tls_local_dynamic_base_32"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI
- [(match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "constant_call_address_operand" "")]
+ [(match_operand:SI 1 "register_operand")
+ (match_operand 2 "constant_call_address_operand")]
UNSPEC_TLS_LD_BASE))
- (clobber (match_scratch:SI 3 ""))
- (clobber (match_scratch:SI 4 ""))
+ (clobber (match_scratch:SI 3))
+ (clobber (match_scratch:SI 4))
(clobber (reg:CC FLAGS_REG))])])
-(define_insn "*tls_local_dynamic_base_64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (call:DI
- (mem:QI (match_operand:DI 1 "constant_call_address_operand" "z"))
- (match_operand:DI 2 "" "")))
- (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
+(define_insn "*tls_local_dynamic_base_64_<mode>"
+ [(set (match_operand:P 0 "register_operand" "=a")
+ (call:P
+ (mem:QI (match_operand 1 "constant_call_address_operand" "z"))
+ (match_operand 2)))
+ (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)]
"TARGET_64BIT"
{
output_asm_insn
[(set_attr "type" "multi")
(set_attr "length" "12")])
-(define_expand "tls_local_dynamic_base_64"
+(define_expand "tls_local_dynamic_base_64_<mode>"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (call:DI
- (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
+ [(set (match_operand:P 0 "register_operand")
+ (call:P
+ (mem:QI (match_operand 1 "constant_call_address_operand"))
(const_int 0)))
- (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])])
+ (unspec:P [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
+ "TARGET_64BIT")
;; Local dynamic of a single variable is a lose. Show combine how
;; to convert that back to global dynamic.
[(set (match_operand:SI 0 "register_operand" "=a")
(plus:SI
(unspec:SI [(match_operand:SI 1 "register_operand" "b")
- (match_operand:SI 2 "constant_call_address_operand" "z")]
+ (match_operand 2 "constant_call_address_operand" "z")]
UNSPEC_TLS_LD_BASE)
(const:SI (unspec:SI
- [(match_operand:SI 3 "tls_symbolic_operand" "")]
+ [(match_operand 3 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (match_scratch:SI 4 "=d"))
(clobber (match_scratch:SI 5 "=c"))
(define_insn "tls_initial_exec_64_sun"
[(set (match_operand:DI 0 "register_operand" "=a")
(unspec:DI
- [(match_operand:DI 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLS_IE_SUN))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_SUN_TLS"
(define_expand "tls_dynamic_gnu2_32"
[(set (match_dup 3)
- (plus:SI (match_operand:SI 2 "register_operand" "")
+ (plus:SI (match_operand:SI 2 "register_operand")
(const:SI
- (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")]
+ (unspec:SI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))))
(parallel
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
(unspec:SI [(match_dup 1) (match_dup 3)
(match_dup 2) (reg:SI SP_REG)]
UNSPEC_TLSDESC))
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (match_operand:SI 1 "register_operand" "b")
(const:SI
- (unspec:SI [(match_operand:SI 2 "tls_symbolic_operand" "")]
+ (unspec:SI [(match_operand 2 "tls_symbolic_operand")]
UNSPEC_TLSDESC))))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
- "lea{l}\t{%a2@TLSDESC(%1), %0|%0, %a2@TLSDESC[%1]}"
+ "lea{l}\t{%E2@TLSDESC(%1), %0|%0, %E2@TLSDESC[%1]}"
[(set_attr "type" "lea")
(set_attr "mode" "SI")
(set_attr "length" "6")
(define_insn "*tls_dynamic_gnu2_call_32"
[(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(match_operand:SI 1 "tls_symbolic_operand" "")
+ (unspec:SI [(match_operand 1 "tls_symbolic_operand")
(match_operand:SI 2 "register_operand" "0")
;; we have to make sure %ebx still points to the GOT
(match_operand:SI 3 "register_operand" "b")
(define_insn_and_split "*tls_dynamic_gnu2_combine_32"
[(set (match_operand:SI 0 "register_operand" "=&a")
(plus:SI
- (unspec:SI [(match_operand:SI 3 "tls_modbase_operand" "")
- (match_operand:SI 4 "" "")
+ (unspec:SI [(match_operand 3 "tls_modbase_operand")
+ (match_operand:SI 4)
(match_operand:SI 2 "register_operand" "b")
(reg:SI SP_REG)]
UNSPEC_TLSDESC)
(const:SI (unspec:SI
- [(match_operand:SI 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_GNU2_TLS"
(define_expand "tls_dynamic_gnu2_64"
[(set (match_dup 2)
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))
(parallel
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(unspec:DI [(match_dup 1) (match_dup 2) (reg:DI SP_REG)]
UNSPEC_TLSDESC))
(clobber (reg:CC FLAGS_REG))])]
(define_insn "*tls_dynamic_gnu2_lea_64"
[(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")]
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_TLSDESC))]
"TARGET_64BIT && TARGET_GNU2_TLS"
- "lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
+ "lea{q}\t{%E1@TLSDESC(%%rip), %0|%0, %E1@TLSDESC[rip]}"
[(set_attr "type" "lea")
(set_attr "mode" "DI")
(set_attr "length" "7")
(define_insn "*tls_dynamic_gnu2_call_64"
[(set (match_operand:DI 0 "register_operand" "=a")
- (unspec:DI [(match_operand 1 "tls_symbolic_operand" "")
+ (unspec:DI [(match_operand 1 "tls_symbolic_operand")
(match_operand:DI 2 "register_operand" "0")
(reg:DI SP_REG)]
UNSPEC_TLSDESC))
(define_insn_and_split "*tls_dynamic_gnu2_combine_64"
[(set (match_operand:DI 0 "register_operand" "=&a")
(plus:DI
- (unspec:DI [(match_operand:DI 2 "tls_modbase_operand" "")
- (match_operand:DI 3 "" "")
+ (unspec:DI [(match_operand 2 "tls_modbase_operand")
+ (match_operand:DI 3)
(reg:DI SP_REG)]
UNSPEC_TLSDESC)
(const:DI (unspec:DI
- [(match_operand 1 "tls_symbolic_operand" "")]
+ [(match_operand 1 "tls_symbolic_operand")]
UNSPEC_DTPOFF))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && TARGET_GNU2_TLS"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1,2")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
(const_string "sseadd"))
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
(const_string "fop"))))
(set_attr "isa" "*,noavx,avx")
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
(const_string "sseadd")))
(set_attr "isa" "noavx,avx")
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:MODEF 3 "mult_operator" "")
+ (if_then_else (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
(const_string "fop")))
(set_attr "mode" "<MODE>")])
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(and (eq_attr "alternative" "2,3")
- (match_operand:MODEF 3 "mult_operator" ""))
+ (match_operand:MODEF 3 "mult_operator"))
(const_string "ssemul")
(and (eq_attr "alternative" "2,3")
- (match_operand:MODEF 3 "div_operator" ""))
+ (match_operand:MODEF 3 "div_operator"))
(const_string "ssediv")
(eq_attr "alternative" "2,3")
(const_string "sseadd")
- (match_operand:MODEF 3 "mult_operator" "")
+ (match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "ssemul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "ssediv")
]
(const_string "sseadd")))
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& (TARGET_USE_<SWI24:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:MODEF 3 "mult_operator" "")
+ (cond [(match_operand:MODEF 3 "mult_operator")
(const_string "fmul")
- (match_operand:MODEF 3 "div_operator" "")
+ (match_operand:MODEF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
+ (cond [(match_operand:DF 3 "mult_operator")
(const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
+ (match_operand:DF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
&& COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (if_then_else (match_operand:XF 3 "mult_operator" "")
+ (if_then_else (match_operand:XF 3 "mult_operator")
(const_string "fmul")
(const_string "fop")))
(set_attr "mode" "XF")])
&& !COMMUTATIVE_ARITH_P (operands[3])"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
"TARGET_80387"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:XF 3 "mult_operator" "")
+ (cond [(match_operand:XF 3 "mult_operator")
(const_string "fmul")
- (match_operand:XF 3 "div_operator" "")
+ (match_operand:XF 3 "div_operator")
(const_string "fdiv")
]
(const_string "fop")))
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "binary_fp_operator"
- [(float (match_operand:SWI24 1 "register_operand" ""))
- (match_operand 2 "register_operand" "")]))]
+ [(float (match_operand:SWI24 1 "register_operand"))
+ (match_operand 2 "register_operand")]))]
"reload_completed
&& X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[1]))"
})
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "binary_fp_operator"
- [(match_operand 1 "register_operand" "")
- (float (match_operand:SWI24 2 "register_operand" ""))]))]
+ [(match_operand 1 "register_operand")
+ (float (match_operand:SWI24 2 "register_operand"))]))]
"reload_completed
&& X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& X87_ENABLE_FLOAT (GET_MODE (operands[0]), GET_MODE (operands[2]))"
(set_attr "mode" "SF")])
(define_expand "rsqrtsf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "")]
+ [(set (match_operand:SF 0 "register_operand")
+ (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
UNSPEC_RSQRT))]
"TARGET_SSE_MATH"
{
(set_attr "bdver1_decode" "*")])
(define_expand "sqrt<mode>2"
- [(set (match_operand:MODEF 0 "register_operand" "")
+ [(set (match_operand:MODEF 0 "register_operand")
(sqrt:MODEF
- (match_operand:MODEF 1 "nonimmediate_operand" "")))]
+ (match_operand:MODEF 1 "nonimmediate_operand")))]
"(TARGET_USE_FANCY_MATH_387 && X87_ENABLE_ARITH (<MODE>mode))
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
(set_attr "mode" "XF")])
(define_expand "fmodxf3"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "general_operand" ""))
- (use (match_operand:XF 2 "general_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "general_operand"))
+ (use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
})
(define_expand "fmod<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx (*gen_truncxf) (rtx, rtx);
(set_attr "mode" "XF")])
(define_expand "remainderxf3"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "general_operand" ""))
- (use (match_operand:XF 2 "general_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "general_operand"))
+ (use (match_operand:XF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx label = gen_label_rtx ();
})
(define_expand "remainder<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx (*gen_truncxf) (rtx, rtx);
DONE;
})
-(define_insn "*sinxf2_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "fsin"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "XF")])
+(define_int_iterator SINCOS
+ [UNSPEC_SIN
+ UNSPEC_COS])
-(define_insn "*sin_extend<mode>xf2_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(float_extend:XF
- (match_operand:MODEF 1 "register_operand" "0"))]
- UNSPEC_SIN))]
- "TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations"
- "fsin"
- [(set_attr "type" "fpspc")
- (set_attr "mode" "XF")])
+(define_int_attr sincos
+ [(UNSPEC_SIN "sin")
+ (UNSPEC_COS "cos")])
-(define_insn "*cosxf2_i387"
+(define_insn "*<sincos>xf2_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ SINCOS))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
- "fcos"
+ "f<sincos>"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
-(define_insn "*cos_extend<mode>xf2_i387"
+(define_insn "*<sincos>_extend<mode>xf2_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(float_extend:XF
(match_operand:MODEF 1 "register_operand" "0"))]
- UNSPEC_COS))]
+ SINCOS))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations"
- "fcos"
+ "f<sincos>"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
(set_attr "mode" "XF")])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
[(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")]
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
(set_attr "mode" "XF")])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
- (match_operand:MODEF 2 "register_operand" ""))]
+ (match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
&& can_create_pseudo_p ()"
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
(define_split
- [(set (match_operand:XF 0 "register_operand" "")
+ [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(float_extend:XF
- (match_operand:MODEF 2 "register_operand" ""))]
+ (match_operand:MODEF 2 "register_operand"))]
UNSPEC_SINCOS_COS))
- (set (match_operand:XF 1 "register_operand" "")
+ (set (match_operand:XF 1 "register_operand")
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
"find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
&& can_create_pseudo_p ()"
(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
(define_expand "sincos<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))
+ (use (match_operand:MODEF 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "tanxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "tan<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "atan2xf3"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 2 "register_operand" "")
- (match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 2 "register_operand")
+ (match_operand:XF 1 "register_operand")]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations")
(define_expand "atan2<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))
- (use (match_operand:MODEF 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))
+ (use (match_operand:MODEF 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "atanxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 2)
- (match_operand:XF 1 "register_operand" "")]
+ (match_operand:XF 1 "register_operand")]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "atan<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "asinxf2"
[(set (match_dup 2)
- (mult:XF (match_operand:XF 1 "register_operand" "")
+ (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 1)))
(set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
(set (match_dup 5) (sqrt:XF (match_dup 4)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 5) (match_dup 1)]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 6 ""))])]
+ (clobber (match_scratch:XF 6))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "asin<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "acosxf2"
[(set (match_dup 2)
- (mult:XF (match_operand:XF 1 "register_operand" "")
+ (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 1)))
(set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
(set (match_dup 5) (sqrt:XF (match_dup 4)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 1) (match_dup 5)]
UNSPEC_FPATAN))
- (clobber (match_scratch:XF 6 ""))])]
+ (clobber (match_scratch:XF 6))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "acos<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "logxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "log10xf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log10<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "log2xf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 2)] UNSPEC_FYL2X))
- (clobber (match_scratch:XF 3 ""))])]
+ (clobber (match_scratch:XF 3))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log2<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "log1pxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "log1p<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "logbxf2"
[(parallel [(set (match_dup 2)
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_XTRACT_FRACT))
- (set (match_operand:XF 0 "register_operand" "")
+ (set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"operands[2] = gen_reg_rtx (XFmode);")
(define_expand "logb<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "ilogbxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "ilogb<mode>2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "expNcorexf3"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")))
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
(set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
(set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
- (parallel [(set (match_operand:XF 0 "register_operand" "")
+ (parallel [(set (match_operand:XF 0 "register_operand")
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_FRACT))
(set (match_dup 9)
})
(define_expand "expxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "exp10xf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp10<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "exp2xf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:XF 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
})
(define_expand "exp2<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "expm1xf2"
- [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
+ [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand")
(match_dup 2)))
(set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
(set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
UNSPEC_FSCALE_EXP))])
(set (match_dup 12) (minus:XF (match_dup 10)
(float_extend:XF (match_dup 13))))
- (set (match_operand:XF 0 "register_operand" "")
+ (set (match_operand:XF 0 "register_operand")
(plus:XF (match_dup 12) (match_dup 7)))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
})
(define_expand "expm1<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(define_expand "ldexpxf3"
[(set (match_dup 3)
- (float:XF (match_operand:SI 2 "register_operand" "")))
- (parallel [(set (match_operand:XF 0 " register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
+ (float:XF (match_operand:SI 2 "register_operand")))
+ (parallel [(set (match_operand:XF 0 " register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
(match_dup 3)]
UNSPEC_FSCALE_FRACT))
(set (match_dup 4)
})
(define_expand "ldexp<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:SI 2 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:SI 2 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "scalbxf3"
- [(parallel [(set (match_operand:XF 0 " register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")
- (match_operand:XF 2 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 " register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")
+ (match_operand:XF 2 "register_operand")]
UNSPEC_FSCALE_FRACT))
(set (match_dup 3)
(unspec:XF [(match_dup 1) (match_dup 2)]
})
(define_expand "scalb<mode>3"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "general_operand" ""))
- (use (match_operand:MODEF 2 "general_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "general_operand"))
+ (use (match_operand:MODEF 2 "general_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "significandxf2"
- [(parallel [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
UNSPEC_XTRACT_FRACT))
(set (match_dup 2)
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
"operands[2] = gen_reg_rtx (XFmode);")
(define_expand "significand<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
(set_attr "mode" "XF")])
(define_expand "rint<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_expand "round<mode>2"
- [(match_operand:X87MODEF 0 "register_operand" "")
- (match_operand:X87MODEF 1 "nonimmediate_operand" "")]
+ [(match_operand:X87MODEF 0 "register_operand")
+ (match_operand:X87MODEF 1 "nonimmediate_operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
})
(define_insn_and_split "*fistdi2_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& can_create_pseudo_p ()"
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "register_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
(clobber (match_dup 3))])
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:DI 0 "memory_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:DI 2 "memory_operand" ""))
- (clobber (match_scratch 3 ""))]
+ (clobber (match_operand:DI 2 "memory_operand"))
+ (clobber (match_scratch 3))]
"reload_completed"
[(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
(clobber (match_dup 3))])])
(define_insn_and_split "*fist<mode>2_1"
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387
&& can_create_pseudo_p ()"
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:SWI24 2 "memory_operand" ""))]
+ (clobber (match_operand:SWI24 2 "memory_operand"))]
"reload_completed"
[(set (match_dup 2) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))
(set (match_dup 0) (match_dup 2))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))
- (clobber (match_operand:SWI24 2 "memory_operand" ""))]
+ (clobber (match_operand:SWI24 2 "memory_operand"))]
"reload_completed"
[(set (match_dup 0) (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST))])
(define_expand "lrintxf<mode>2"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
UNSPEC_FIST))]
"TARGET_USE_FANCY_MATH_387")
(define_expand "lrint<MODEF:mode><SWI48x:mode>2"
- [(set (match_operand:SWI48x 0 "nonimmediate_operand" "")
- (unspec:SWI48x [(match_operand:MODEF 1 "register_operand" "")]
+ [(set (match_operand:SWI48x 0 "nonimmediate_operand")
+ (unspec:SWI48x [(match_operand:MODEF 1 "register_operand")]
UNSPEC_FIX_NOTRUNC))]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& ((<SWI48x:MODE>mode != DImode) || TARGET_64BIT)")
(define_expand "lround<X87MODEF:mode><SWI248x:mode>2"
- [(match_operand:SWI248x 0 "nonimmediate_operand" "")
- (match_operand:X87MODEF 1 "register_operand" "")]
+ [(match_operand:SWI248x 0 "nonimmediate_operand")
+ (match_operand:X87MODEF 1 "register_operand")]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
DONE;
})
+(define_int_iterator FRNDINT_ROUNDING
+ [UNSPEC_FRNDINT_FLOOR
+ UNSPEC_FRNDINT_CEIL
+ UNSPEC_FRNDINT_TRUNC])
+
+(define_int_iterator FIST_ROUNDING
+ [UNSPEC_FIST_FLOOR
+ UNSPEC_FIST_CEIL])
+
+;; Base name for define_insn
+(define_int_attr rounding_insn
+ [(UNSPEC_FRNDINT_FLOOR "floor")
+ (UNSPEC_FRNDINT_CEIL "ceil")
+ (UNSPEC_FRNDINT_TRUNC "btrunc")
+ (UNSPEC_FIST_FLOOR "floor")
+ (UNSPEC_FIST_CEIL "ceil")])
+
+(define_int_attr rounding
+ [(UNSPEC_FRNDINT_FLOOR "floor")
+ (UNSPEC_FRNDINT_CEIL "ceil")
+ (UNSPEC_FRNDINT_TRUNC "trunc")
+ (UNSPEC_FIST_FLOOR "floor")
+ (UNSPEC_FIST_CEIL "ceil")])
+
+(define_int_attr ROUNDING
+ [(UNSPEC_FRNDINT_FLOOR "FLOOR")
+ (UNSPEC_FRNDINT_CEIL "CEIL")
+ (UNSPEC_FRNDINT_TRUNC "TRUNC")
+ (UNSPEC_FIST_FLOOR "FLOOR")
+ (UNSPEC_FIST_CEIL "CEIL")])
+
;; Rounding mode control word calculation could clobber FLAGS_REG.
-(define_insn_and_split "frndintxf2_floor"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FRNDINT_FLOOR))
+(define_insn_and_split "frndintxf2_<rounding>"
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
+ FRNDINT_ROUNDING))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
"&& 1"
[(const_int 0)]
{
- ix86_optimize_mode_switching[I387_FLOOR] = 1;
+ ix86_optimize_mode_switching[I387_<ROUNDING>] = 1;
operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>);
- emit_insn (gen_frndintxf2_floor_i387 (operands[0], operands[1],
- operands[2], operands[3]));
+ emit_insn (gen_frndintxf2_<rounding>_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
DONE;
}
[(set_attr "type" "frndint")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "XF")])
-(define_insn "frndintxf2_floor_i387"
+(define_insn "frndintxf2_<rounding>_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT_FLOOR))
+ FRNDINT_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "XF")])
-(define_expand "floorxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+(define_expand "<rounding_insn>xf2"
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
+ FRNDINT_ROUNDING))
+ (clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
-{
- if (optimize_insn_for_size_p ())
- FAIL;
- emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
- DONE;
-})
+ && flag_unsafe_math_optimizations
+ && !optimize_insn_for_size_p ()")
-(define_expand "floor<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
+(define_expand "<rounding_insn><mode>2"
+ [(parallel [(set (match_operand:MODEF 0 "register_operand")
+ (unspec:MODEF [(match_operand:MODEF 1 "register_operand")]
+ FRNDINT_ROUNDING))
+ (clobber (reg:CC FLAGS_REG))])]
"(TARGET_USE_FANCY_MATH_387
&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
|| TARGET_MIX_SSE_I387)
{
if (TARGET_ROUND)
emit_insn (gen_sse4_1_round<mode>2
- (operands[0], operands[1], GEN_INT (ROUND_FLOOR)));
+ (operands[0], operands[1], GEN_INT (ROUND_<ROUNDING>)));
else if (optimize_insn_for_size_p ())
- FAIL;
+ FAIL;
else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_floorceil (operands[0], operands[1], true);
+ {
+ if (ROUND_<ROUNDING> == ROUND_FLOOR)
+ ix86_expand_floorceil (operands[0], operands[1], true);
+ else if (ROUND_<ROUNDING> == ROUND_CEIL)
+ ix86_expand_floorceil (operands[0], operands[1], false);
+ else if (ROUND_<ROUNDING> == ROUND_TRUNC)
+ ix86_expand_trunc (operands[0], operands[1]);
+ else
+ gcc_unreachable ();
+ }
else
- ix86_expand_floorceildf_32 (operands[0], operands[1], true);
+ {
+ if (ROUND_<ROUNDING> == ROUND_FLOOR)
+ ix86_expand_floorceildf_32 (operands[0], operands[1], true);
+ else if (ROUND_<ROUNDING> == ROUND_CEIL)
+ ix86_expand_floorceildf_32 (operands[0], operands[1], false);
+ else if (ROUND_<ROUNDING> == ROUND_TRUNC)
+ ix86_expand_truncdf_32 (operands[0], operands[1]);
+ else
+ gcc_unreachable ();
+ }
}
else
{
op0 = gen_reg_rtx (XFmode);
op1 = gen_reg_rtx (XFmode);
emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_floor (op0, op1));
+ emit_insn (gen_frndintxf2_<rounding> (op0, op1));
emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
}
DONE;
})
-(define_insn_and_split "*fist<mode>2_floor_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "frndintxf2_mask_pm"
+ [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
+ UNSPEC_FRNDINT_MASK_PM))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations
+ && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ ix86_optimize_mode_switching[I387_MASK_PM] = 1;
+
+ operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
+
+ emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
+ operands[2], operands[3]));
+ DONE;
+}
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "mask_pm")
+ (set_attr "mode" "XF")])
+
+(define_insn "frndintxf2_mask_pm_i387"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
+ UNSPEC_FRNDINT_MASK_PM))
+ (use (match_operand:HI 2 "memory_operand" "m"))
+ (use (match_operand:HI 3 "memory_operand" "m"))]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations"
+ "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
+ [(set_attr "type" "frndint")
+ (set_attr "i387_cw" "mask_pm")
+ (set_attr "mode" "XF")])
+
+(define_expand "nearbyintxf2"
+ [(parallel [(set (match_operand:XF 0 "register_operand")
+ (unspec:XF [(match_operand:XF 1 "register_operand")]
+ UNSPEC_FRNDINT_MASK_PM))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_USE_FANCY_MATH_387
+ && flag_unsafe_math_optimizations")
+
+(define_expand "nearbyint<mode>2"
+ [(use (match_operand:MODEF 0 "register_operand"))
+ (use (match_operand:MODEF 1 "register_operand"))]
+ "TARGET_USE_FANCY_MATH_387
+ && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
+ || TARGET_MIX_SSE_I387)
+ && flag_unsafe_math_optimizations"
+{
+ rtx op0 = gen_reg_rtx (XFmode);
+ rtx op1 = gen_reg_rtx (XFmode);
+
+ emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
+ emit_insn (gen_frndintxf2_mask_pm (op0, op1));
+
+ emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
+ DONE;
+})
+
+;; Rounding mode control word calculation could clobber FLAGS_REG.
+(define_insn_and_split "*fist<mode>2_<rounding>_1"
+ [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
(clobber (reg:CC FLAGS_REG))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations
"&& 1"
[(const_int 0)]
{
- ix86_optimize_mode_switching[I387_FLOOR] = 1;
+ ix86_optimize_mode_switching[I387_<ROUNDING>] = 1;
operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
+ operands[3] = assign_386_stack_local (HImode, SLOT_CW_<ROUNDING>);
if (memory_operand (operands[0], VOIDmode))
- emit_insn (gen_fist<mode>2_floor (operands[0], operands[1],
- operands[2], operands[3]));
+ emit_insn (gen_fist<mode>2_<rounding> (operands[0], operands[1],
+ operands[2], operands[3]));
else
{
operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
- emit_insn (gen_fist<mode>2_floor_with_temp (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
+ emit_insn (gen_fist<mode>2_<rounding>_with_temp
+ (operands[0], operands[1], operands[2],
+ operands[3], operands[4]));
}
DONE;
}
[(set_attr "type" "fistp")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "<MODE>")])
-(define_insn "fistdi2_floor"
+(define_insn "fistdi2_<rounding>"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST_FLOOR))
+ FIST_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))
(clobber (match_scratch:XF 4 "=&1f"))]
&& flag_unsafe_math_optimizations"
"* return output_fix_trunc (insn, operands, false);"
[(set_attr "type" "fistp")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "DI")])
-(define_insn "fistdi2_floor_with_temp"
+(define_insn "fistdi2_<rounding>_with_temp"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
(unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST_FLOOR))
+ FIST_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m,m"))
(use (match_operand:HI 3 "memory_operand" "m,m"))
(clobber (match_operand:DI 4 "memory_operand" "=X,m"))
&& flag_unsafe_math_optimizations"
"#"
[(set_attr "type" "fistp")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "DI")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 4)
- (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (unspec:DI [(match_dup 1)] FIST_ROUNDING))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 5))])
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
+ [(set (match_operand:DI 0 "memory_operand")
+ (unspec:DI [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:DI 4 "memory_operand"))
+ (clobber (match_scratch 5))]
"reload_completed"
[(parallel [(set (match_dup 0)
- (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (unspec:DI [(match_dup 1)] FIST_ROUNDING))
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 5))])])
-(define_insn "fist<mode>2_floor"
+(define_insn "fist<mode>2_<rounding>"
[(set (match_operand:SWI24 0 "memory_operand" "=m")
(unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST_FLOOR))
+ FIST_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"* return output_fix_trunc (insn, operands, false);"
[(set_attr "type" "fistp")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "<MODE>")])
-(define_insn "fist<mode>2_floor_with_temp"
+(define_insn "fist<mode>2_<rounding>_with_temp"
[(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
(unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST_FLOOR))
+ FIST_ROUNDING))
(use (match_operand:HI 2 "memory_operand" "m,m"))
(use (match_operand:HI 3 "memory_operand" "m,m"))
(clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
&& flag_unsafe_math_optimizations"
"#"
[(set_attr "type" "fistp")
- (set_attr "i387_cw" "floor")
+ (set_attr "i387_cw" "<rounding>")
(set_attr "mode" "<MODE>")])
(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "register_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 4)
- (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (unspec:SWI24 [(match_dup 1)] FIST_ROUNDING))
(use (match_dup 2))
(use (match_dup 3))])
(set (match_dup 0) (match_dup 4))])
(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
+ [(set (match_operand:SWI24 0 "memory_operand")
+ (unspec:SWI24 [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
+ (use (match_operand:HI 2 "memory_operand"))
+ (use (match_operand:HI 3 "memory_operand"))
+ (clobber (match_operand:SWI24 4 "memory_operand"))]
"reload_completed"
[(parallel [(set (match_dup 0)
- (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_FLOOR))
+ (unspec:SWI24 [(match_dup 1)] FIST_ROUNDING))
(use (match_dup 2))
(use (match_dup 3))])])
-(define_expand "lfloorxf<mode>2"
- [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_FLOOR))
+(define_expand "l<rounding_insn>xf<mode>2"
+ [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand")
+ (unspec:SWI248x [(match_operand:XF 1 "register_operand")]
+ FIST_ROUNDING))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
&& flag_unsafe_math_optimizations")
-(define_expand "lfloor<MODEF:mode><SWI48:mode>2"
- [(match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
+(define_expand "l<rounding_insn><MODEF:mode><SWI48:mode>2"
+ [(parallel [(set (match_operand:SWI48 0 "nonimmediate_operand")
+ (unspec:SWI48 [(match_operand:MODEF 1 "register_operand")]
+ FIST_ROUNDING))
+ (clobber (reg:CC FLAGS_REG))])]
"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
&& !flag_trapping_math"
{
if (TARGET_64BIT && optimize_insn_for_size_p ())
FAIL;
- ix86_expand_lfloorceil (operands[0], operands[1], true);
+
+ if (ROUND_<ROUNDING> == ROUND_FLOOR)
+ ix86_expand_lfloorceil (operands[0], operands[1], true);
+ else if (ROUND_<ROUNDING> == ROUND_CEIL)
+ ix86_expand_lfloorceil (operands[0], operands[1], false);
+ else
+ gcc_unreachable ();
+
DONE;
})
-;; Rounding mode control word calculation could clobber FLAGS_REG.
-(define_insn_and_split "frndintxf2_ceil"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FRNDINT_CEIL))
- (clobber (reg:CC FLAGS_REG))]
+(define_insn "fxam<mode>2_i387"
+ [(set (match_operand:HI 0 "register_operand" "=a")
+ (unspec:HI
+ [(match_operand:X87MODEF 1 "register_operand" "f")]
+ UNSPEC_FXAM))]
+ "TARGET_USE_FANCY_MATH_387"
+ "fxam\n\tfnstsw\t%0"
+ [(set_attr "type" "multi")
+ (set_attr "length" "4")
+ (set_attr "unit" "i387")
+ (set_attr "mode" "<MODE>")])
+
+(define_insn_and_split "fxam<mode>2_i387_with_temp"
+ [(set (match_operand:HI 0 "register_operand")
+ (unspec:HI
+ [(match_operand:MODEF 1 "memory_operand")]
+ UNSPEC_FXAM_MEM))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations
&& can_create_pseudo_p ()"
"#"
"&& 1"
- [(const_int 0)]
+ [(set (match_dup 2)(match_dup 1))
+ (set (match_dup 0)
+ (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
{
- ix86_optimize_mode_switching[I387_CEIL] = 1;
-
- operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
+ operands[2] = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_frndintxf2_ceil_i387 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
+ MEM_VOLATILE_P (operands[1]) = 1;
}
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "XF")])
-
-(define_insn "frndintxf2_ceil_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT_CEIL))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "XF")])
+ [(set_attr "type" "multi")
+ (set_attr "unit" "i387")
+ (set_attr "mode" "<MODE>")])
-(define_expand "ceilxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+(define_expand "isinfxf2"
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
+ && TARGET_C99_FUNCTIONS"
{
- if (optimize_insn_for_size_p ())
- FAIL;
- emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
- DONE;
-})
-
-(define_expand "ceil<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
- "(TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations)
- || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math)"
-{
- if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math)
- {
- if (TARGET_ROUND)
- emit_insn (gen_sse4_1_round<mode>2
- (operands[0], operands[1], GEN_INT (ROUND_CEIL)));
- else if (optimize_insn_for_size_p ())
- FAIL;
- else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_floorceil (operands[0], operands[1], false);
- else
- ix86_expand_floorceildf_32 (operands[0], operands[1], false);
- }
- else
- {
- rtx op0, op1;
-
- if (optimize_insn_for_size_p ())
- FAIL;
-
- op0 = gen_reg_rtx (XFmode);
- op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_ceil (op0, op1));
-
- emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
- }
- DONE;
-})
-
-(define_insn_and_split "*fist<mode>2_ceil_1"
- [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- ix86_optimize_mode_switching[I387_CEIL] = 1;
-
- operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
- if (memory_operand (operands[0], VOIDmode))
- emit_insn (gen_fist<mode>2_ceil (operands[0], operands[1],
- operands[2], operands[3]));
- else
- {
- operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
- emit_insn (gen_fist<mode>2_ceil_with_temp (operands[0], operands[1],
- operands[2], operands[3],
- operands[4]));
- }
- DONE;
-}
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "fistdi2_ceil"
- [(set (match_operand:DI 0 "memory_operand" "=m")
- (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))
- (clobber (match_scratch:XF 4 "=&1f"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "* return output_fix_trunc (insn, operands, false);"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "DI")])
-
-(define_insn "fistdi2_ceil_with_temp"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
- (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" "m,m"))
- (use (match_operand:HI 3 "memory_operand" "m,m"))
- (clobber (match_operand:DI 4 "memory_operand" "=X,m"))
- (clobber (match_scratch:XF 5 "=&1f,&1f"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "#"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 4)
- (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
- (use (match_dup 2))
- (use (match_dup 3))
- (clobber (match_dup 5))])
- (set (match_dup 0) (match_dup 4))])
-
-(define_split
- [(set (match_operand:DI 0 "memory_operand" "")
- (unspec:DI [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:DI 4 "memory_operand" ""))
- (clobber (match_scratch 5 ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
- (use (match_dup 2))
- (use (match_dup 3))
- (clobber (match_dup 5))])])
-
-(define_insn "fist<mode>2_ceil"
- [(set (match_operand:SWI24 0 "memory_operand" "=m")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "* return output_fix_trunc (insn, operands, false);"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "fist<mode>2_ceil_with_temp"
- [(set (match_operand:SWI24 0 "nonimmediate_operand" "=m,?r")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "f,f")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" "m,m"))
- (use (match_operand:HI 3 "memory_operand" "m,m"))
- (clobber (match_operand:SWI24 4 "memory_operand" "=X,m"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "#"
- [(set_attr "type" "fistp")
- (set_attr "i387_cw" "ceil")
- (set_attr "mode" "<MODE>")])
-
-(define_split
- [(set (match_operand:SWI24 0 "register_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
- "reload_completed"
- [(parallel [(set (match_dup 4)
- (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
- (use (match_dup 2))
- (use (match_dup 3))])
- (set (match_dup 0) (match_dup 4))])
-
-(define_split
- [(set (match_operand:SWI24 0 "memory_operand" "")
- (unspec:SWI24 [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (use (match_operand:HI 2 "memory_operand" ""))
- (use (match_operand:HI 3 "memory_operand" ""))
- (clobber (match_operand:SWI24 4 "memory_operand" ""))]
- "reload_completed"
- [(parallel [(set (match_dup 0)
- (unspec:SWI24 [(match_dup 1)] UNSPEC_FIST_CEIL))
- (use (match_dup 2))
- (use (match_dup 3))])])
-
-(define_expand "lceilxf<mode>2"
- [(parallel [(set (match_operand:SWI248x 0 "nonimmediate_operand" "")
- (unspec:SWI248x [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FIST_CEIL))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations")
-
-(define_expand "lceil<MODEF:mode><SWI48:mode>2"
- [(match_operand:SWI48 0 "nonimmediate_operand" "")
- (match_operand:MODEF 1 "register_operand" "")]
- "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math"
-{
- ix86_expand_lfloorceil (operands[0], operands[1], false);
- DONE;
-})
-
-;; Rounding mode control word calculation could clobber FLAGS_REG.
-(define_insn_and_split "frndintxf2_trunc"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FRNDINT_TRUNC))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- ix86_optimize_mode_switching[I387_TRUNC] = 1;
-
- operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
-
- emit_insn (gen_frndintxf2_trunc_i387 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-}
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "XF")])
-
-(define_insn "frndintxf2_trunc_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT_TRUNC))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "trunc")
- (set_attr "mode" "XF")])
-
-(define_expand "btruncxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
-{
- if (optimize_insn_for_size_p ())
- FAIL;
- emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
- DONE;
-})
-
-(define_expand "btrunc<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
- "(TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations)
- || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math)"
-{
- if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
- && !flag_trapping_math)
- {
- if (TARGET_ROUND)
- emit_insn (gen_sse4_1_round<mode>2
- (operands[0], operands[1], GEN_INT (ROUND_TRUNC)));
- else if (optimize_insn_for_size_p ())
- FAIL;
- else if (TARGET_64BIT || (<MODE>mode != DFmode))
- ix86_expand_trunc (operands[0], operands[1]);
- else
- ix86_expand_truncdf_32 (operands[0], operands[1]);
- }
- else
- {
- rtx op0, op1;
-
- if (optimize_insn_for_size_p ())
- FAIL;
-
- op0 = gen_reg_rtx (XFmode);
- op1 = gen_reg_rtx (XFmode);
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_trunc (op0, op1));
-
- emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
- }
- DONE;
-})
-
-;; Rounding mode control word calculation could clobber FLAGS_REG.
-(define_insn_and_split "frndintxf2_mask_pm"
- [(set (match_operand:XF 0 "register_operand" "")
- (unspec:XF [(match_operand:XF 1 "register_operand" "")]
- UNSPEC_FRNDINT_MASK_PM))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(const_int 0)]
-{
- ix86_optimize_mode_switching[I387_MASK_PM] = 1;
-
- operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
- operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
-
- emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-}
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "mask_pm")
- (set_attr "mode" "XF")])
-
-(define_insn "frndintxf2_mask_pm_i387"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
- UNSPEC_FRNDINT_MASK_PM))
- (use (match_operand:HI 2 "memory_operand" "m"))
- (use (match_operand:HI 3 "memory_operand" "m"))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
- "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
- [(set_attr "type" "frndint")
- (set_attr "i387_cw" "mask_pm")
- (set_attr "mode" "XF")])
-
-(define_expand "nearbyintxf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && flag_unsafe_math_optimizations"
-{
- emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
- DONE;
-})
-
-(define_expand "nearbyint<mode>2"
- [(use (match_operand:MODEF 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || TARGET_MIX_SSE_I387)
- && flag_unsafe_math_optimizations"
-{
- rtx op0 = gen_reg_rtx (XFmode);
- rtx op1 = gen_reg_rtx (XFmode);
-
- emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
- emit_insn (gen_frndintxf2_mask_pm (op0, op1));
-
- emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
- DONE;
-})
-
-(define_insn "fxam<mode>2_i387"
- [(set (match_operand:HI 0 "register_operand" "=a")
- (unspec:HI
- [(match_operand:X87MODEF 1 "register_operand" "f")]
- UNSPEC_FXAM))]
- "TARGET_USE_FANCY_MATH_387"
- "fxam\n\tfnstsw\t%0"
- [(set_attr "type" "multi")
- (set_attr "length" "4")
- (set_attr "unit" "i387")
- (set_attr "mode" "<MODE>")])
-
-(define_insn_and_split "fxam<mode>2_i387_with_temp"
- [(set (match_operand:HI 0 "register_operand" "")
- (unspec:HI
- [(match_operand:MODEF 1 "memory_operand" "")]
- UNSPEC_FXAM_MEM))]
- "TARGET_USE_FANCY_MATH_387
- && can_create_pseudo_p ()"
- "#"
- "&& 1"
- [(set (match_dup 2)(match_dup 1))
- (set (match_dup 0)
- (unspec:HI [(match_dup 2)] UNSPEC_FXAM))]
-{
- operands[2] = gen_reg_rtx (<MODE>mode);
-
- MEM_VOLATILE_P (operands[1]) = 1;
-}
- [(set_attr "type" "multi")
- (set_attr "unit" "i387")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "isinfxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
- "TARGET_USE_FANCY_MATH_387
- && TARGET_C99_FUNCTIONS"
-{
- rtx mask = GEN_INT (0x45);
- rtx val = GEN_INT (0x05);
-
- rtx cond;
-
- rtx scratch = gen_reg_rtx (HImode);
- rtx res = gen_reg_rtx (QImode);
-
- emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
-
- emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
- emit_insn (gen_cmpqi_ext_3 (scratch, val));
- cond = gen_rtx_fmt_ee (EQ, QImode,
- gen_rtx_REG (CCmode, FLAGS_REG),
- const0_rtx);
- emit_insn (gen_rtx_SET (VOIDmode, res, cond));
- emit_insn (gen_zero_extendqisi2 (operands[0], res));
+ rtx mask = GEN_INT (0x45);
+ rtx val = GEN_INT (0x05);
+
+ rtx cond;
+
+ rtx scratch = gen_reg_rtx (HImode);
+ rtx res = gen_reg_rtx (QImode);
+
+ emit_insn (gen_fxamxf2_i387 (scratch, operands[1]));
+
+ emit_insn (gen_andqi_ext_0 (scratch, scratch, mask));
+ emit_insn (gen_cmpqi_ext_3 (scratch, val));
+ cond = gen_rtx_fmt_ee (EQ, QImode,
+ gen_rtx_REG (CCmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, res, cond));
+ emit_insn (gen_zero_extendqisi2 (operands[0], res));
DONE;
})
(define_expand "isinf<mode>2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:MODEF 1 "nonimmediate_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:MODEF 1 "nonimmediate_operand"))]
"TARGET_USE_FANCY_MATH_387
&& TARGET_C99_FUNCTIONS
&& !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
})
(define_expand "signbitxf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:XF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387"
{
rtx scratch = gen_reg_rtx (HImode);
;; Use movmskpd in SSE mode to avoid store forwarding stall
;; for 32bit targets and movq+shrq sequence for 64bit targets.
(define_expand "signbitdf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:DF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:DF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
|| (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH)"
{
})
(define_expand "signbitsf2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:SF 1 "register_operand" ""))]
+ [(use (match_operand:SI 0 "register_operand"))
+ (use (match_operand:SF 1 "register_operand"))]
"TARGET_USE_FANCY_MATH_387
&& !(SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH)"
{
(set_attr "modrm" "0")])
(define_expand "movmem<mode>"
- [(use (match_operand:BLK 0 "memory_operand" ""))
- (use (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:SWI48 2 "nonmemory_operand" ""))
- (use (match_operand:SWI48 3 "const_int_operand" ""))
- (use (match_operand:SI 4 "const_int_operand" ""))
- (use (match_operand:SI 5 "const_int_operand" ""))]
+ [(use (match_operand:BLK 0 "memory_operand"))
+ (use (match_operand:BLK 1 "memory_operand"))
+ (use (match_operand:SWI48 2 "nonmemory_operand"))
+ (use (match_operand:SWI48 3 "const_int_operand"))
+ (use (match_operand:SI 4 "const_int_operand"))
+ (use (match_operand:SI 5 "const_int_operand"))]
""
{
if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3],
;; Handle this case here to simplify previous expander.
(define_expand "strmov"
- [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
- (set (match_operand 1 "memory_operand" "") (match_dup 4))
- (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
+ [(set (match_dup 4) (match_operand 3 "memory_operand"))
+ (set (match_operand 1 "memory_operand") (match_dup 4))
+ (parallel [(set (match_operand 0 "register_operand") (match_dup 5))
(clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
+ (parallel [(set (match_operand 2 "register_operand") (match_dup 6))
(clobber (reg:CC FLAGS_REG))])]
""
{
})
(define_expand "strmov_singleop"
- [(parallel [(set (match_operand 1 "memory_operand" "")
- (match_operand 3 "memory_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (match_operand 4 "" ""))
- (set (match_operand 2 "register_operand" "")
- (match_operand 5 "" ""))])]
+ [(parallel [(set (match_operand 1 "memory_operand")
+ (match_operand 3 "memory_operand"))
+ (set (match_operand 0 "register_operand")
+ (match_operand 4))
+ (set (match_operand 2 "register_operand")
+ (match_operand 5))])]
""
"ix86_current_function_needs_cld = 1;")
(define_insn "*strmovdi_rex_1"
- [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
- (mem:DI (match_operand:DI 3 "register_operand" "1")))
- (set (match_operand:DI 0 "register_operand" "=D")
- (plus:DI (match_dup 2)
- (const_int 8)))
- (set (match_operand:DI 1 "register_operand" "=S")
- (plus:DI (match_dup 3)
- (const_int 8)))]
+ [(set (mem:DI (match_operand:P 2 "register_operand" "0"))
+ (mem:DI (match_operand:P 3 "register_operand" "1")))
+ (set (match_operand:P 0 "register_operand" "=D")
+ (plus:P (match_dup 2)
+ (const_int 8)))
+ (set (match_operand:P 1 "register_operand" "=S")
+ (plus:P (match_dup 3)
+ (const_int 8)))]
"TARGET_64BIT
&& !(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "movsq"
+ "%^movsq"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set_attr "mode" "DI")])
(plus:P (match_dup 3)
(const_int 4)))]
"!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "movs{l|d}"
+ "%^movs{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set_attr "mode" "SI")])
(plus:P (match_dup 3)
(const_int 2)))]
"!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "movsw"
+ "%^movsw"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set_attr "mode" "HI")])
(plus:P (match_dup 3)
(const_int 1)))]
"!(fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "movsb"
+ "%^movsb"
[(set_attr "type" "str")
(set_attr "memory" "both")
(set (attr "prefix_rex")
(set_attr "mode" "QI")])
(define_expand "rep_mov"
- [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
- (set (match_operand 0 "register_operand" "")
- (match_operand 5 "" ""))
- (set (match_operand 2 "register_operand" "")
- (match_operand 6 "" ""))
- (set (match_operand 1 "memory_operand" "")
- (match_operand 3 "memory_operand" ""))
+ [(parallel [(set (match_operand 4 "register_operand") (const_int 0))
+ (set (match_operand 0 "register_operand")
+ (match_operand 5))
+ (set (match_operand 2 "register_operand")
+ (match_operand 6))
+ (set (match_operand 1 "memory_operand")
+ (match_operand 3 "memory_operand"))
(use (match_dup 4))])]
""
"ix86_current_function_needs_cld = 1;")
(define_insn "*rep_movdi_rex64"
- [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
- (set (match_operand:DI 0 "register_operand" "=D")
- (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
- (const_int 3))
- (match_operand:DI 3 "register_operand" "0")))
- (set (match_operand:DI 1 "register_operand" "=S")
- (plus:DI (ashift:DI (match_dup 5) (const_int 3))
- (match_operand:DI 4 "register_operand" "1")))
+ [(set (match_operand:P 2 "register_operand" "=c") (const_int 0))
+ (set (match_operand:P 0 "register_operand" "=D")
+ (plus:P (ashift:P (match_operand:P 5 "register_operand" "2")
+ (const_int 3))
+ (match_operand:P 3 "register_operand" "0")))
+ (set (match_operand:P 1 "register_operand" "=S")
+ (plus:P (ashift:P (match_dup 5) (const_int 3))
+ (match_operand:P 4 "register_operand" "1")))
(set (mem:BLK (match_dup 3))
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"TARGET_64BIT
&& !(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "rep{%;} movsq"
+ "%^rep{%;} movsq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "rep{%;} movs{l|d}"
+ "%^rep{%;} movs{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(mem:BLK (match_dup 4)))
(use (match_dup 5))]
"!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "rep{%;} movsb"
+ "%^rep{%;} movsb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "both")
(set_attr "mode" "QI")])
(define_expand "setmem<mode>"
- [(use (match_operand:BLK 0 "memory_operand" ""))
- (use (match_operand:SWI48 1 "nonmemory_operand" ""))
- (use (match_operand:QI 2 "nonmemory_operand" ""))
- (use (match_operand 3 "const_int_operand" ""))
- (use (match_operand:SI 4 "const_int_operand" ""))
- (use (match_operand:SI 5 "const_int_operand" ""))]
+ [(use (match_operand:BLK 0 "memory_operand"))
+ (use (match_operand:SWI48 1 "nonmemory_operand"))
+ (use (match_operand:QI 2 "nonmemory_operand"))
+ (use (match_operand 3 "const_int_operand"))
+ (use (match_operand:SI 4 "const_int_operand"))
+ (use (match_operand:SI 5 "const_int_operand"))]
""
{
if (ix86_expand_setmem (operands[0], operands[1],
;; Handle this case here to simplify previous expander.
(define_expand "strset"
- [(set (match_operand 1 "memory_operand" "")
- (match_operand 2 "register_operand" ""))
- (parallel [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 1 "memory_operand")
+ (match_operand 2 "register_operand"))
+ (parallel [(set (match_operand 0 "register_operand")
(match_dup 3))
(clobber (reg:CC FLAGS_REG))])]
""
})
(define_expand "strset_singleop"
- [(parallel [(set (match_operand 1 "memory_operand" "")
- (match_operand 2 "register_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (match_operand 3 "" ""))])]
+ [(parallel [(set (match_operand 1 "memory_operand")
+ (match_operand 2 "register_operand"))
+ (set (match_operand 0 "register_operand")
+ (match_operand 3))])]
""
"ix86_current_function_needs_cld = 1;")
(define_insn "*strsetdi_rex_1"
- [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
+ [(set (mem:DI (match_operand:P 1 "register_operand" "0"))
(match_operand:DI 2 "register_operand" "a"))
- (set (match_operand:DI 0 "register_operand" "=D")
- (plus:DI (match_dup 1)
- (const_int 8)))]
+ (set (match_operand:P 0 "register_operand" "=D")
+ (plus:P (match_dup 1)
+ (const_int 8)))]
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
- "stosq"
+ "%^stosq"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set_attr "mode" "DI")])
(plus:P (match_dup 1)
(const_int 4)))]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
- "stos{l|d}"
+ "%^stos{l|d}"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set_attr "mode" "SI")])
(plus:P (match_dup 1)
(const_int 2)))]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
- "stosw"
+ "%^stosw"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set_attr "mode" "HI")])
(plus:P (match_dup 1)
(const_int 1)))]
"!(fixed_regs[AX_REG] || fixed_regs[DI_REG])"
- "stosb"
+ "%^stosb"
[(set_attr "type" "str")
(set_attr "memory" "store")
(set (attr "prefix_rex")
(set_attr "mode" "QI")])
(define_expand "rep_stos"
- [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
- (set (match_operand 0 "register_operand" "")
- (match_operand 4 "" ""))
- (set (match_operand 2 "memory_operand" "") (const_int 0))
- (use (match_operand 3 "register_operand" ""))
+ [(parallel [(set (match_operand 1 "register_operand") (const_int 0))
+ (set (match_operand 0 "register_operand")
+ (match_operand 4))
+ (set (match_operand 2 "memory_operand") (const_int 0))
+ (use (match_operand 3 "register_operand"))
(use (match_dup 1))])]
""
"ix86_current_function_needs_cld = 1;")
(define_insn "*rep_stosdi_rex64"
- [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
- (set (match_operand:DI 0 "register_operand" "=D")
- (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
- (const_int 3))
- (match_operand:DI 3 "register_operand" "0")))
+ [(set (match_operand:P 1 "register_operand" "=c") (const_int 0))
+ (set (match_operand:P 0 "register_operand" "=D")
+ (plus:P (ashift:P (match_operand:P 4 "register_operand" "1")
+ (const_int 3))
+ (match_operand:P 3 "register_operand" "0")))
(set (mem:BLK (match_dup 3))
(const_int 0))
(use (match_operand:DI 2 "register_operand" "a"))
(use (match_dup 4))]
"TARGET_64BIT
&& !(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
- "rep{%;} stosq"
+ "%^rep{%;} stosq"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:SI 2 "register_operand" "a"))
(use (match_dup 4))]
"!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
- "rep{%;} stos{l|d}"
+ "%^rep{%;} stos{l|d}"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(use (match_operand:QI 2 "register_operand" "a"))
(use (match_dup 4))]
"!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
- "rep{%;} stosb"
+ "%^rep{%;} stosb"
[(set_attr "type" "str")
(set_attr "prefix_rep" "1")
(set_attr "memory" "store")
(set_attr "mode" "QI")])
(define_expand "cmpstrnsi"
- [(set (match_operand:SI 0 "register_operand" "")
- (compare:SI (match_operand:BLK 1 "general_operand" "")
- (match_operand:BLK 2 "general_operand" "")))
- (use (match_operand 3 "general_operand" ""))
- (use (match_operand 4 "immediate_operand" ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (compare:SI (match_operand:BLK 1 "general_operand")
+ (match_operand:BLK 2 "general_operand")))
+ (use (match_operand 3 "general_operand"))
+ (use (match_operand 4 "immediate_operand"))]
""
{
rtx addr1, addr2, out, outlow, count, countreg, align;
if (!REG_P (out))
out = gen_reg_rtx (SImode);
- addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
- addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
+ addr1 = copy_addr_to_reg (XEXP (operands[1], 0));
+ addr2 = copy_addr_to_reg (XEXP (operands[2], 0));
if (addr1 != XEXP (operands[1], 0))
operands[1] = replace_equiv_address_nv (operands[1], addr1);
if (addr2 != XEXP (operands[2], 0))
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (match_dup 2)
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (parallel [(set (match_operand:QI 0 "register_operand" "")
+ (parallel [(set (match_operand:QI 0 "register_operand")
(minus:QI (match_dup 1)
(match_dup 2)))
(clobber (reg:CC FLAGS_REG))])]
(define_expand "cmpstrnqi_nz_1"
[(parallel [(set (reg:CC FLAGS_REG)
- (compare:CC (match_operand 4 "memory_operand" "")
- (match_operand 5 "memory_operand" "")))
- (use (match_operand 2 "register_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ (compare:CC (match_operand 4 "memory_operand")
+ (match_operand 5 "memory_operand")))
+ (use (match_operand 2 "register_operand"))
+ (use (match_operand:SI 3 "immediate_operand"))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
(clobber (match_dup 2))])]
""
"ix86_current_function_needs_cld = 1;")
(clobber (match_operand:P 1 "register_operand" "=D"))
(clobber (match_operand:P 2 "register_operand" "=c"))]
"!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "repz{%;} cmpsb"
+ "%^repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(define_expand "cmpstrnqi_1"
[(parallel [(set (reg:CC FLAGS_REG)
- (if_then_else:CC (ne (match_operand 2 "register_operand" "")
+ (if_then_else:CC (ne (match_operand 2 "register_operand")
(const_int 0))
- (compare:CC (match_operand 4 "memory_operand" "")
- (match_operand 5 "memory_operand" ""))
+ (compare:CC (match_operand 4 "memory_operand")
+ (match_operand 5 "memory_operand"))
(const_int 0)))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand"))
(use (reg:CC FLAGS_REG))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
(clobber (match_dup 2))])]
""
"ix86_current_function_needs_cld = 1;")
(clobber (match_operand:P 1 "register_operand" "=D"))
(clobber (match_operand:P 2 "register_operand" "=c"))]
"!(fixed_regs[CX_REG] || fixed_regs[SI_REG] || fixed_regs[DI_REG])"
- "repz{%;} cmpsb"
+ "%^repz{%;} cmpsb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(set_attr "prefix_rep" "1")])
(define_expand "strlen<mode>"
- [(set (match_operand:P 0 "register_operand" "")
- (unspec:P [(match_operand:BLK 1 "general_operand" "")
- (match_operand:QI 2 "immediate_operand" "")
- (match_operand 3 "immediate_operand" "")]
+ [(set (match_operand:P 0 "register_operand")
+ (unspec:P [(match_operand:BLK 1 "general_operand")
+ (match_operand:QI 2 "immediate_operand")
+ (match_operand 3 "immediate_operand")]
UNSPEC_SCAS))]
""
{
})
(define_expand "strlenqi_1"
- [(parallel [(set (match_operand 0 "register_operand" "")
- (match_operand 2 "" ""))
- (clobber (match_operand 1 "register_operand" ""))
+ [(parallel [(set (match_operand 0 "register_operand")
+ (match_operand 2))
+ (clobber (match_operand 1 "register_operand"))
(clobber (reg:CC FLAGS_REG))])]
""
"ix86_current_function_needs_cld = 1;")
(clobber (match_operand:P 1 "register_operand" "=D"))
(clobber (reg:CC FLAGS_REG))]
"!(fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])"
- "repnz{%;} scasb"
+ "%^repnz{%;} scasb"
[(set_attr "type" "str")
(set_attr "mode" "QI")
(set (attr "prefix_rex")
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
- (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
- (mem:BLK (match_operand 5 "register_operand" ""))))
- (use (match_operand 6 "register_operand" ""))
- (use (match_operand:SI 3 "immediate_operand" ""))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
- (clobber (match_operand 2 "register_operand" ""))])
- (set (match_operand:QI 7 "register_operand" "")
+ (compare:CC (mem:BLK (match_operand 4 "register_operand"))
+ (mem:BLK (match_operand 5 "register_operand"))))
+ (use (match_operand 6 "register_operand"))
+ (use (match_operand:SI 3 "immediate_operand"))
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
+ (clobber (match_operand 2 "register_operand"))])
+ (set (match_operand:QI 7 "register_operand")
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (match_operand:QI 8 "register_operand" "")
+ (set (match_operand:QI 8 "register_operand")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
(define_peephole2
[(parallel[
(set (reg:CC FLAGS_REG)
- (if_then_else:CC (ne (match_operand 6 "register_operand" "")
+ (if_then_else:CC (ne (match_operand 6 "register_operand")
(const_int 0))
- (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
- (mem:BLK (match_operand 5 "register_operand" "")))
+ (compare:CC (mem:BLK (match_operand 4 "register_operand"))
+ (mem:BLK (match_operand 5 "register_operand")))
(const_int 0)))
- (use (match_operand:SI 3 "immediate_operand" ""))
+ (use (match_operand:SI 3 "immediate_operand"))
(use (reg:CC FLAGS_REG))
- (clobber (match_operand 0 "register_operand" ""))
- (clobber (match_operand 1 "register_operand" ""))
- (clobber (match_operand 2 "register_operand" ""))])
- (set (match_operand:QI 7 "register_operand" "")
+ (clobber (match_operand 0 "register_operand"))
+ (clobber (match_operand 1 "register_operand"))
+ (clobber (match_operand 2 "register_operand"))])
+ (set (match_operand:QI 7 "register_operand")
(gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
- (set (match_operand:QI 8 "register_operand" "")
+ (set (match_operand:QI 8 "register_operand")
(ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
(set (reg FLAGS_REG)
(compare (match_dup 7) (match_dup 8)))
;; Conditional move instructions.
(define_expand "mov<mode>cc"
- [(set (match_operand:SWIM 0 "register_operand" "")
- (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator" "")
- (match_operand:SWIM 2 "<general_operand>" "")
- (match_operand:SWIM 3 "<general_operand>" "")))]
+ [(set (match_operand:SWIM 0 "register_operand")
+ (if_then_else:SWIM (match_operand 1 "ordered_comparison_operator")
+ (match_operand:SWIM 2 "<general_operand>")
+ (match_operand:SWIM 3 "<general_operand>")))]
""
"if (ix86_expand_int_movcc (operands)) DONE; else FAIL;")
(define_expand "x86_mov<mode>cc_0_m1"
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
(if_then_else:SWI48
(match_operator:SWI48 2 "ix86_carry_flag_operator"
- [(match_operand 1 "flags_reg_operand" "")
+ [(match_operand 1 "flags_reg_operand")
(const_int 0)])
(const_int -1)
(const_int 0)))
(define_insn "*x86_mov<mode>cc_0_m1_neg"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(neg:SWI48 (match_operator 1 "ix86_carry_flag_operator"
- [(reg FLAGS_REG) (const_int 0)])))]
+ [(reg FLAGS_REG) (const_int 0)])))
+ (clobber (reg:CC FLAGS_REG))]
""
"sbb{<imodesuffix>}\t%0, %0"
[(set_attr "type" "alu")
[(set_attr "type" "icmov")
(set_attr "mode" "<MODE>")])
-(define_insn_and_split "*movqicc_noc"
+(define_insn "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
+ [(reg FLAGS_REG) (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
"#"
- "&& reload_completed"
- [(set (match_dup 0)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 2)
- (match_dup 3)))]
- "operands[0] = gen_lowpart (SImode, operands[0]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- operands[3] = gen_lowpart (SImode, operands[3]);"
[(set_attr "type" "icmov")
- (set_attr "mode" "SI")])
+ (set_attr "mode" "QI")])
+
+(define_split
+ [(set (match_operand 0 "register_operand")
+ (if_then_else (match_operator 1 "ix86_comparison_operator"
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand 2 "register_operand")
+ (match_operand 3 "register_operand")))]
+ "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL
+ && (GET_MODE (operands[0]) == QImode
+ || GET_MODE (operands[0]) == HImode)
+ && reload_completed"
+ [(set (match_dup 0)
+ (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
+{
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[2] = gen_lowpart (SImode, operands[2]);
+ operands[3] = gen_lowpart (SImode, operands[3]);
+})
(define_expand "mov<mode>cc"
- [(set (match_operand:X87MODEF 0 "register_operand" "")
+ [(set (match_operand:X87MODEF 0 "register_operand")
(if_then_else:X87MODEF
- (match_operand 1 "ix86_fp_comparison_operator" "")
- (match_operand:X87MODEF 2 "register_operand" "")
- (match_operand:X87MODEF 3 "register_operand" "")))]
+ (match_operand 1 "ix86_fp_comparison_operator")
+ (match_operand:X87MODEF 2 "register_operand")
+ (match_operand:X87MODEF 3 "register_operand")))]
"(TARGET_80387 && TARGET_CMOVE)
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"if (ix86_expand_fp_movcc (operands)) DONE; else FAIL;")
(set_attr "mode" "DF,DF,DI,DI")])
(define_split
- [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
+ [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
- [(match_operand 4 "flags_reg_operand" "")
- (const_int 0)])
- (match_operand:DF 2 "nonimmediate_operand" "")
- (match_operand:DF 3 "nonimmediate_operand" "")))]
+ [(reg FLAGS_REG) (const_int 0)])
+ (match_operand:DF 2 "nonimmediate_operand")
+ (match_operand:DF 3 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed"
[(set (match_dup 2)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 5)
- (match_dup 6)))
+ (if_then_else:SI (match_dup 1) (match_dup 4) (match_dup 5)))
(set (match_dup 3)
- (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
- (match_dup 7)
- (match_dup 8)))]
+ (if_then_else:SI (match_dup 1) (match_dup 6) (match_dup 7)))]
{
- split_double_mode (DImode, &operands[2], 2, &operands[5], &operands[7]);
+ split_double_mode (DImode, &operands[2], 2, &operands[4], &operands[6]);
split_double_mode (DImode, &operands[0], 1, &operands[2], &operands[3]);
})
;; Their operands are not commutative, and thus they may be used in the
;; presence of -0.0 and NaN.
-(define_insn "*ieee_smin<mode>3"
- [(set (match_operand:MODEF 0 "register_operand" "=x,x")
- (unspec:MODEF
- [(match_operand:MODEF 1 "register_operand" "0,x")
- (match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
- UNSPEC_IEEE_MIN))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
- "@
- min<ssemodesuffix>\t{%2, %0|%0, %2}
- vmin<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "noavx,avx")
- (set_attr "prefix" "orig,vex")
- (set_attr "type" "sseadd")
- (set_attr "mode" "<MODE>")])
+(define_int_iterator IEEE_MAXMIN
+ [UNSPEC_IEEE_MAX
+ UNSPEC_IEEE_MIN])
-(define_insn "*ieee_smax<mode>3"
+(define_int_attr ieee_maxmin
+ [(UNSPEC_IEEE_MAX "max")
+ (UNSPEC_IEEE_MIN "min")])
+
+(define_insn "*ieee_s<ieee_maxmin><mode>3"
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
(unspec:MODEF
[(match_operand:MODEF 1 "register_operand" "0,x")
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
- UNSPEC_IEEE_MAX))]
+ IEEE_MAXMIN))]
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
"@
- max<ssemodesuffix>\t{%2, %0|%0, %2}
- vmax<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ <ieee_maxmin><ssemodesuffix>\t{%2, %0|%0, %2}
+ v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "prefix" "orig,vex")
(set_attr "type" "sseadd")
;;
;; Actually we only match the last two instructions for simplicity.
(define_peephole2
- [(set (match_operand 0 "fp_register_operand" "")
- (match_operand 1 "fp_register_operand" ""))
+ [(set (match_operand 0 "fp_register_operand")
+ (match_operand 1 "fp_register_operand"))
(set (match_dup 0)
(match_operator 2 "binary_fp_operator"
[(match_dup 0)
- (match_operand 3 "memory_operand" "")]))]
+ (match_operand 3 "memory_operand")]))]
"REGNO (operands[0]) != REGNO (operands[1])"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
;; Conditional addition patterns
(define_expand "add<mode>cc"
- [(match_operand:SWI 0 "register_operand" "")
- (match_operand 1 "ordered_comparison_operator" "")
- (match_operand:SWI 2 "register_operand" "")
- (match_operand:SWI 3 "const_int_operand" "")]
+ [(match_operand:SWI 0 "register_operand")
+ (match_operand 1 "ordered_comparison_operator")
+ (match_operand:SWI 2 "register_operand")
+ (match_operand:SWI 3 "const_int_operand")]
""
"if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
\f
default:
operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
- return "lea{<imodesuffix>}\t{%a2, %0|%0, %a2}";
+ return "lea{<imodesuffix>}\t{%E2, %0|%0, %E2}";
}
}
[(set (attr "type")
(cond [(and (eq_attr "alternative" "0")
(not (match_test "TARGET_OPT_AGU")))
(const_string "alu")
- (match_operand:<MODE> 2 "const0_operand" "")
+ (match_operand:<MODE> 2 "const0_operand")
(const_string "imov")
]
(const_string "lea")))
(cond [(eq_attr "type" "imov")
(const_string "0")
(and (eq_attr "type" "alu")
- (match_operand 2 "const128_operand" ""))
+ (match_operand 2 "const128_operand"))
(const_string "1")
]
(const_string "*")))
(set_attr "length" "5")])
(define_expand "allocate_stack"
- [(match_operand 0 "register_operand" "")
- (match_operand 1 "general_operand" "")]
+ [(match_operand 0 "register_operand")
+ (match_operand 1 "general_operand")]
"ix86_target_stack_probe ()"
{
rtx x;
if (CHECK_STACK_LIMIT && CONST_INT_P (operands[1])
&& INTVAL (operands[1]) < CHECK_STACK_LIMIT)
- {
- x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, operands[1],
- stack_pointer_rtx, 0, OPTAB_DIRECT);
- if (x != stack_pointer_rtx)
- emit_move_insn (stack_pointer_rtx, x);
- }
+ x = operands[1];
else
{
+ rtx (*insn) (rtx, rtx);
+
x = copy_to_mode_reg (Pmode, operands[1]);
- if (TARGET_64BIT)
- emit_insn (gen_allocate_stack_worker_probe_di (x, x));
- else
- emit_insn (gen_allocate_stack_worker_probe_si (x, x));
- x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, x,
- stack_pointer_rtx, 0, OPTAB_DIRECT);
- if (x != stack_pointer_rtx)
- emit_move_insn (stack_pointer_rtx, x);
+
+ insn = (TARGET_64BIT
+ ? gen_allocate_stack_worker_probe_di
+ : gen_allocate_stack_worker_probe_si);
+
+ emit_insn (insn (x, x));
}
+ x = expand_simple_binop (Pmode, MINUS, stack_pointer_rtx, x,
+ stack_pointer_rtx, 0, OPTAB_DIRECT);
+
+ if (x != stack_pointer_rtx)
+ emit_move_insn (stack_pointer_rtx, x);
+
emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
DONE;
})
;; Use IOR for stack probes, this is shorter.
(define_expand "probe_stack"
- [(match_operand 0 "memory_operand" "")]
+ [(match_operand 0 "memory_operand")]
""
{
rtx (*gen_ior3) (rtx, rtx, rtx);
[(set_attr "type" "multi")])
(define_expand "builtin_setjmp_receiver"
- [(label_ref (match_operand 0 "" ""))]
+ [(label_ref (match_operand 0))]
"!TARGET_64BIT && flag_pic"
{
#if TARGET_MACHO
;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(match_operator 3 "promotable_binary_operator"
- [(match_operand 1 "register_operand" "")
- (match_operand 2 "aligned_operand" "")]))
+ [(match_operand 1 "register_operand")
+ (match_operand 2 "aligned_operand")]))
(clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ((GET_MODE (operands[0]) == HImode
; instruction size is unchanged, except in the %eax case for
; which it is increased by one byte, hence the ! optimize_size.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 2 "compare_operator"
- [(and (match_operand 3 "aligned_operand" "")
- (match_operand 4 "const_int_operand" ""))
+ [(and (match_operand 3 "aligned_operand")
+ (match_operand 4 "const_int_operand"))
(const_int 0)]))
- (set (match_operand 1 "register_operand" "")
+ (set (match_operand 1 "register_operand")
(and (match_dup 3) (match_dup 4)))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& optimize_insn_for_speed_p ()
; the instruction size would at least double, which is not what we
; want even with ! optimize_size.
(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and (match_operand:HI 2 "aligned_operand" "")
- (match_operand:HI 3 "const_int_operand" ""))
+ [(and (match_operand:HI 2 "aligned_operand")
+ (match_operand:HI 3 "const_int_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& ! TARGET_FAST_PREFIX
})
(define_split
- [(set (match_operand 0 "register_operand" "")
- (neg (match_operand 1 "register_operand" "")))
+ [(set (match_operand 0 "register_operand")
+ (neg (match_operand 1 "register_operand")))
(clobber (reg:CC FLAGS_REG))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
})
(define_split
- [(set (match_operand 0 "register_operand" "")
- (not (match_operand 1 "register_operand" "")))]
+ [(set (match_operand 0 "register_operand")
+ (not (match_operand 1 "register_operand")))]
"! TARGET_PARTIAL_REG_STALL && reload_completed
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
})
-
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (if_then_else (match_operator 1 "ordered_comparison_operator"
- [(reg FLAGS_REG) (const_int 0)])
- (match_operand 2 "register_operand" "")
- (match_operand 3 "register_operand" "")))]
- "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
- && (GET_MODE (operands[0]) == HImode
- || (GET_MODE (operands[0]) == QImode
- && (TARGET_PROMOTE_QImode
- || optimize_insn_for_size_p ())))"
- [(set (match_dup 0)
- (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
-{
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[2] = gen_lowpart (SImode, operands[2]);
- operands[3] = gen_lowpart (SImode, operands[3]);
-})
\f
;; RTL Peephole optimizations, run before sched2. These primarily look to
;; transform a complex memory operation into two memory to register operations.
;; Don't push memory operands
(define_peephole2
- [(set (match_operand:SWI 0 "push_operand" "")
- (match_operand:SWI 1 "memory_operand" ""))
+ [(set (match_operand:SWI 0 "push_operand")
+ (match_operand:SWI 1 "memory_operand"))
(match_scratch:SWI 2 "<r>")]
"!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
;; We need to handle SFmode only, because DFmode and XFmode are split to
;; SImode pushes.
(define_peephole2
- [(set (match_operand:SF 0 "push_operand" "")
- (match_operand:SF 1 "memory_operand" ""))
+ [(set (match_operand:SF 0 "push_operand")
+ (match_operand:SF 1 "memory_operand"))
(match_scratch:SF 2 "r")]
"!(TARGET_PUSH_MEMORY || optimize_insn_for_size_p ())
&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
(set (match_dup 0) (match_dup 2))])
;; Don't move an immediate directly to memory when the instruction
-;; gets too big.
+;; gets too big, or if LCP stalls are a problem for 16-bit moves.
(define_peephole2
[(match_scratch:SWI124 1 "<r>")
- (set (match_operand:SWI124 0 "memory_operand" "")
+ (set (match_operand:SWI124 0 "memory_operand")
(const_int 0))]
"optimize_insn_for_speed_p ()
- && !TARGET_USE_MOV0
- && TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cur_cost ()->large_insn
+ && ((<MODE>mode == HImode
+ && TARGET_LCP_STALL)
+ || (!TARGET_USE_MOV0
+ && TARGET_SPLIT_LONG_MOVES
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn))
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 2) (const_int 0))
(clobber (reg:CC FLAGS_REG))])
(define_peephole2
[(match_scratch:SWI124 2 "<r>")
- (set (match_operand:SWI124 0 "memory_operand" "")
- (match_operand:SWI124 1 "immediate_operand" ""))]
+ (set (match_operand:SWI124 0 "memory_operand")
+ (match_operand:SWI124 1 "immediate_operand"))]
"optimize_insn_for_speed_p ()
- && TARGET_SPLIT_LONG_MOVES
- && get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
+ && ((<MODE>mode == HImode
+ && TARGET_LCP_STALL)
+ || (TARGET_SPLIT_LONG_MOVES
+ && get_attr_length (insn) >= ix86_cur_cost ()->large_insn))"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 2))])
;; Don't compare memory with zero, load and use a test instead.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(match_operand:SI 2 "memory_operand" "")
+ [(match_operand:SI 2 "memory_operand")
(const_int 0)]))
(match_scratch:SI 3 "r")]
"optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)"
;; lifetime information then.
(define_peephole2
- [(set (match_operand:SWI124 0 "nonimmediate_operand" "")
- (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:SWI124 0 "nonimmediate_operand")
+ (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand")))]
"optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
;; versions if we're concerned about partial register stalls.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and:SI (match_operand:SI 2 "register_operand" "")
- (match_operand:SI 3 "immediate_operand" ""))
+ [(and:SI (match_operand:SI 2 "register_operand")
+ (match_operand:SI 3 "immediate_operand"))
(const_int 0)]))]
"ix86_match_ccmode (insn, CCNOmode)
&& (true_regnum (operands[2]) != AX_REG
;; on ! TARGET_PARTIAL_REG_STALL
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(and:QI (match_operand:QI 2 "register_operand" "")
- (match_operand:QI 3 "immediate_operand" ""))
+ [(and:QI (match_operand:QI 2 "register_operand")
+ (match_operand:QI 3 "immediate_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
(and:QI (match_dup 2) (match_dup 3)))])])
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
[(and:SI
(zero_extract:SI
- (match_operand 2 "ext_register_operand" "")
+ (match_operand 2 "ext_register_operand")
(const_int 8)
(const_int 8))
- (match_operand 3 "const_int_operand" ""))
+ (match_operand 3 "const_int_operand"))
(const_int 0)]))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
;; Don't do logical operations with memory inputs.
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (parallel [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
- (match_operand:SI 1 "memory_operand" "")]))
+ (match_operand:SI 1 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
[(set (match_dup 2) (match_dup 1))
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (parallel [(set (match_operand:SI 0 "register_operand")
(match_operator:SI 3 "arith_or_logical_operator"
- [(match_operand:SI 1 "memory_operand" "")
+ [(match_operand:SI 1 "memory_operand")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY || optimize_insn_for_size_p ())"
;; refers to the destination of the load!
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "register_operand" ""))
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "register_operand"))
(parallel [(set (match_dup 0)
(match_operator:SI 3 "commutative_operator"
[(match_dup 0)
- (match_operand:SI 2 "memory_operand" "")]))
+ (match_operand:SI 2 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"REGNO (operands[0]) != REGNO (operands[1])
&& GENERAL_REGNO_P (REGNO (operands[0]))
"operands[4] = replace_rtx (operands[2], operands[0], operands[1]);")
(define_peephole2
- [(set (match_operand 0 "register_operand" "")
- (match_operand 1 "register_operand" ""))
+ [(set (match_operand 0 "register_operand")
+ (match_operand 1 "register_operand"))
(set (match_dup 0)
(match_operator 3 "commutative_operator"
[(match_dup 0)
- (match_operand 2 "memory_operand" "")]))]
+ (match_operand 2 "memory_operand")]))]
"REGNO (operands[0]) != REGNO (operands[1])
&& ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
|| (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "memory_operand" "")
+ (parallel [(set (match_operand:SI 0 "memory_operand")
(match_operator:SI 3 "arith_or_logical_operator"
[(match_dup 0)
- (match_operand:SI 1 "nonmemory_operand" "")]))
+ (match_operand:SI 1 "nonmemory_operand")]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
/* Do not split stack checking probes. */
(define_peephole2
[(match_scratch:SI 2 "r")
- (parallel [(set (match_operand:SI 0 "memory_operand" "")
+ (parallel [(set (match_operand:SI 0 "memory_operand")
(match_operator:SI 3 "arith_or_logical_operator"
- [(match_operand:SI 1 "nonmemory_operand" "")
+ [(match_operand:SI 1 "nonmemory_operand")
(match_dup 0)]))
(clobber (reg:CC FLAGS_REG))])]
"!(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
;; Attempt to use arith or logical operations with memory outputs with
;; setting of flags.
(define_peephole2
- [(set (match_operand:SWI 0 "register_operand" "")
- (match_operand:SWI 1 "memory_operand" ""))
+ [(set (match_operand:SWI 0 "register_operand")
+ (match_operand:SWI 1 "memory_operand"))
(parallel [(set (match_dup 0)
(match_operator:SWI 3 "plusminuslogic_operator"
[(match_dup 0)
- (match_operand:SWI 2 "<nonmemory_operand>" "")]))
+ (match_operand:SWI 2 "<nonmemory_operand>")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
"(TARGET_READ_MODIFY_WRITE || optimize_insn_for_size_p ())
&& peep2_reg_dead_p (4, operands[0])
&& !reg_overlap_mentioned_p (operands[0], operands[1])
+ && (<MODE>mode != QImode
+ || immediate_operand (operands[2], QImode)
+ || q_regs_operand (operands[2], QImode))
&& ix86_match_ccmode (peep2_next_insn (3),
(GET_CODE (operands[3]) == PLUS
|| GET_CODE (operands[3]) == MINUS)
})
(define_peephole2
- [(parallel [(set (match_operand:SWI 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI 0 "register_operand")
(match_operator:SWI 2 "plusminuslogic_operator"
[(match_dup 0)
- (match_operand:SWI 1 "memory_operand" "")]))
+ (match_operand:SWI 1 "memory_operand")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
})
(define_peephole2
- [(set (match_operand:SWI12 0 "register_operand" "")
- (match_operand:SWI12 1 "memory_operand" ""))
- (parallel [(set (match_operand:SI 4 "register_operand" "")
+ [(set (match_operand:SWI12 0 "register_operand")
+ (match_operand:SWI12 1 "memory_operand"))
+ (parallel [(set (match_operand:SI 4 "register_operand")
(match_operator:SI 3 "plusminuslogic_operator"
[(match_dup 4)
- (match_operand:SI 2 "nonmemory_operand" "")]))
+ (match_operand:SI 2 "nonmemory_operand")]))
(clobber (reg:CC FLAGS_REG))])
(set (match_dup 1) (match_dup 0))
(set (reg FLAGS_REG) (compare (match_dup 0) (const_int 0)))]
;; Attempt to always use XOR for zeroing registers.
(define_peephole2
- [(set (match_operand 0 "register_operand" "")
- (match_operand 1 "const0_operand" ""))]
+ [(set (match_operand 0 "register_operand")
+ (match_operand 1 "const0_operand"))]
"GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
&& (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
&& GENERAL_REG_P (operands[0])
"operands[0] = gen_lowpart (word_mode, operands[0]);")
(define_peephole2
- [(set (strict_low_part (match_operand 0 "register_operand" ""))
+ [(set (strict_low_part (match_operand 0 "register_operand"))
(const_int 0))]
"(GET_MODE (operands[0]) == QImode
|| GET_MODE (operands[0]) == HImode)
;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
(define_peephole2
- [(set (match_operand:SWI248 0 "register_operand" "")
+ [(set (match_operand:SWI248 0 "register_operand")
(const_int -1))]
"(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
&& peep2_regno_dead_p (0, FLAGS_REG)"
;; These can be created by move expanders.
(define_peephole2
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SWI48 0 "register_operand")
(plus:SWI48 (match_dup 0)
- (match_operand:SWI48 1 "<nonmemory_operand>" "")))]
+ (match_operand:SWI48 1 "<nonmemory_operand>")))]
+ "peep2_regno_dead_p (0, FLAGS_REG)"
+ [(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])])
+
+(define_peephole2
+ [(set (match_operand:SWI48 0 "register_operand")
+ (plus:SWI48 (match_operand:SWI48 1 "<nonmemory_operand>")
+ (match_dup 0)))]
"peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
(clobber (reg:CC FLAGS_REG))])])
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")) 0))]
+ [(set (match_operand:SI 0 "register_operand")
+ (subreg:SI (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "nonmemory_operand")) 0))]
"TARGET_64BIT
&& peep2_regno_dead_p (0, FLAGS_REG)
&& REGNO (operands[0]) == REGNO (operands[1])"
"operands[2] = gen_lowpart (SImode, operands[2]);")
(define_peephole2
- [(set (match_operand:SWI48 0 "register_operand" "")
+ [(set (match_operand:SI 0 "register_operand")
+ (subreg:SI (plus:DI (match_operand:DI 1 "nonmemory_operand")
+ (match_operand:DI 2 "register_operand")) 0))]
+ "TARGET_64BIT
+ && peep2_regno_dead_p (0, FLAGS_REG)
+ && REGNO (operands[0]) == REGNO (operands[2])"
+ [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "operands[1] = gen_lowpart (SImode, operands[1]);")
+
+(define_peephole2
+ [(set (match_operand:SWI48 0 "register_operand")
(mult:SWI48 (match_dup 0)
- (match_operand:SWI48 1 "const_int_operand" "")))]
+ (match_operand:SWI48 1 "const_int_operand")))]
"exact_log2 (INTVAL (operands[1])) >= 0
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2)))
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
(define_peephole2
- [(set (match_operand:SI 0 "register_operand" "")
- (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")) 0))]
+ [(set (match_operand:SI 0 "register_operand")
+ (subreg:SI (mult:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "const_int_operand")) 0))]
"TARGET_64BIT
&& exact_log2 (INTVAL (operands[2])) >= 0
&& REGNO (operands[0]) == REGNO (operands[1])
;; alternative when no register is available later.
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)"
+ && INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)"
[(clobber (match_dup 1))
- (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
+ (parallel [(set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))
(clobber (mem:BLK (scratch)))])])
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)"
+ && INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)"
[(clobber (match_dup 1))
- (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
- (parallel [(set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
+ (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))
+ (parallel [(set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))
(clobber (mem:BLK (scratch)))])])
;; Convert esp subtractions to push.
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_SINGLE_PUSH || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == -GET_MODE_SIZE (Pmode)"
+ && INTVAL (operands[0]) == -GET_MODE_SIZE (word_mode)"
[(clobber (match_dup 1))
- (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
+ (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_DOUBLE_PUSH || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == -2*GET_MODE_SIZE (Pmode)"
+ && INTVAL (operands[0]) == -2*GET_MODE_SIZE (word_mode)"
[(clobber (match_dup 1))
- (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))
- (set (mem:P (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
+ (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))
+ (set (mem:W (pre_dec:P (reg:P SP_REG))) (match_dup 1))])
;; Convert epilogue deallocator to pop.
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_SINGLE_POP || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)"
- [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
+ && INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)"
+ [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
(clobber (mem:BLK (scratch)))])])
;; Two pops case is tricky, since pop causes dependency
;; on destination register. We use two registers if available.
(define_peephole2
- [(match_scratch:P 1 "r")
- (match_scratch:P 2 "r")
+ [(match_scratch:W 1 "r")
+ (match_scratch:W 2 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"(TARGET_DOUBLE_POP || optimize_insn_for_size_p ())
- && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
- [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
+ && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
+ [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
(clobber (mem:BLK (scratch)))])
- (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))])
+ (set (match_dup 2) (mem:W (post_inc:P (reg:P SP_REG))))])
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))
(clobber (mem:BLK (scratch)))])]
"optimize_insn_for_size_p ()
- && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
- [(parallel [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
+ && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
+ [(parallel [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
(clobber (mem:BLK (scratch)))])
- (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
+ (set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))])
;; Convert esp additions to pop.
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
- "INTVAL (operands[0]) == GET_MODE_SIZE (Pmode)"
- [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
+ "INTVAL (operands[0]) == GET_MODE_SIZE (word_mode)"
+ [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))])
;; Two pops case is tricky, since pop causes dependency
;; on destination register. We use two registers if available.
(define_peephole2
- [(match_scratch:P 1 "r")
- (match_scratch:P 2 "r")
+ [(match_scratch:W 1 "r")
+ (match_scratch:W 2 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
- "INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
- [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
- (set (match_dup 2) (mem:P (post_inc:P (reg:P SP_REG))))])
+ "INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
+ [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
+ (set (match_dup 2) (mem:W (post_inc:P (reg:P SP_REG))))])
(define_peephole2
- [(match_scratch:P 1 "r")
+ [(match_scratch:W 1 "r")
(parallel [(set (reg:P SP_REG)
(plus:P (reg:P SP_REG)
- (match_operand:P 0 "const_int_operand" "")))
+ (match_operand:P 0 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])]
"optimize_insn_for_size_p ()
- && INTVAL (operands[0]) == 2*GET_MODE_SIZE (Pmode)"
- [(set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))
- (set (match_dup 1) (mem:P (post_inc:P (reg:P SP_REG))))])
+ && INTVAL (operands[0]) == 2*GET_MODE_SIZE (word_mode)"
+ [(set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))
+ (set (match_dup 1) (mem:W (post_inc:P (reg:P SP_REG))))])
\f
;; Convert compares with 1 to shorter inc/dec operations when CF is not
;; required and register dies. Similarly for 128 to -128.
(define_peephole2
- [(set (match_operand 0 "flags_reg_operand" "")
+ [(set (match_operand 0 "flags_reg_operand")
(match_operator 1 "compare_operator"
- [(match_operand 2 "register_operand" "")
- (match_operand 3 "const_int_operand" "")]))]
+ [(match_operand 2 "register_operand")
+ (match_operand 3 "const_int_operand")]))]
"(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
&& incdec_operand (operands[3], GET_MODE (operands[3])))
|| (!TARGET_FUSE_CMP_AND_BRANCH
;; Convert imul by three, five and nine into lea
(define_peephole2
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "register_operand" "")
- (match_operand:SWI48 2 "const359_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "register_operand")
+ (match_operand:SWI48 2 "const359_operand")))
(clobber (reg:CC FLAGS_REG))])]
"!TARGET_PARTIAL_REG_STALL
|| <MODE>mode == SImode
(define_peephole2
[(parallel
- [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
- (match_operand:SWI48 2 "const359_operand" "")))
+ [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+ (match_operand:SWI48 2 "const359_operand")))
(clobber (reg:CC FLAGS_REG))])]
"optimize_insn_for_speed_p ()
&& (!TARGET_PARTIAL_REG_STALL || <MODE>mode == SImode)"
;; imul $32bit_imm, reg, reg is direct decoded.
(define_peephole2
[(match_scratch:SWI48 3 "r")
- (parallel [(set (match_operand:SWI48 0 "register_operand" "")
- (mult:SWI48 (match_operand:SWI48 1 "memory_operand" "")
- (match_operand:SWI48 2 "immediate_operand" "")))
+ (parallel [(set (match_operand:SWI48 0 "register_operand")
+ (mult:SWI48 (match_operand:SWI48 1 "memory_operand")
+ (match_operand:SWI48 2 "immediate_operand")))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
&& !satisfies_constraint_K (operands[2])"
(define_peephole2
[(match_scratch:SI 3 "r")
- (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (parallel [(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
- (mult:SI (match_operand:SI 1 "memory_operand" "")
- (match_operand:SI 2 "immediate_operand" ""))))
+ (mult:SI (match_operand:SI 1 "memory_operand")
+ (match_operand:SI 2 "immediate_operand"))))
(clobber (reg:CC FLAGS_REG))])]
"TARGET_64BIT
&& TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
;; It would be better to force assembler to encode instruction using long
;; immediate, but there is apparently no way to do so.
(define_peephole2
- [(parallel [(set (match_operand:SWI248 0 "register_operand" "")
+ [(parallel [(set (match_operand:SWI248 0 "register_operand")
(mult:SWI248
- (match_operand:SWI248 1 "nonimmediate_operand" "")
- (match_operand:SWI248 2 "const_int_operand" "")))
+ (match_operand:SWI248 1 "nonimmediate_operand")
+ (match_operand:SWI248 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SWI248 3 "r")]
"TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
;; leal (%edx,%eax,4), %eax
(define_peephole2
- [(match_scratch:P 5 "r")
- (parallel [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")))
+ [(match_scratch:W 5 "r")
+ (parallel [(set (match_operand 0 "register_operand")
+ (ashift (match_operand 1 "register_operand")
+ (match_operand 2 "const_int_operand")))
(clobber (reg:CC FLAGS_REG))])
- (parallel [(set (match_operand 3 "register_operand" "")
+ (parallel [(set (match_operand 3 "register_operand")
(plus (match_dup 0)
- (match_operand 4 "x86_64_general_operand" "")))
+ (match_operand 4 "x86_64_general_operand")))
(clobber (reg:CC FLAGS_REG))])]
"IN_RANGE (INTVAL (operands[2]), 1, 3)
/* Validate MODE for lea. */
enum machine_mode op1mode = GET_MODE (operands[1]);
enum machine_mode mode = op1mode == DImode ? DImode : SImode;
int scale = 1 << INTVAL (operands[2]);
- rtx index = gen_lowpart (Pmode, operands[1]);
- rtx base = gen_lowpart (Pmode, operands[5]);
+ rtx index = gen_lowpart (word_mode, operands[1]);
+ rtx base = gen_lowpart (word_mode, operands[5]);
rtx dest = gen_lowpart (mode, operands[3]);
- operands[1] = gen_rtx_PLUS (Pmode, base,
- gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
+ operands[1] = gen_rtx_PLUS (word_mode, base,
+ gen_rtx_MULT (word_mode, index, GEN_INT (scale)));
operands[5] = base;
- if (mode != Pmode)
+ if (mode != word_mode)
operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
- if (op1mode != Pmode)
+ if (op1mode != word_mode)
operands[5] = gen_rtx_SUBREG (op1mode, operands[5], 0);
operands[0] = dest;
})
[(set_attr "length" "2")])
(define_expand "prefetch"
- [(prefetch (match_operand 0 "address_operand" "")
- (match_operand:SI 1 "const_int_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))]
+ [(prefetch (match_operand 0 "address_operand")
+ (match_operand:SI 1 "const_int_operand")
+ (match_operand:SI 2 "const_int_operand"))]
"TARGET_PREFETCH_SSE || TARGET_3DNOW"
{
int rw = INTVAL (operands[1]);
(define_insn "*prefetch_sse_<mode>"
[(prefetch (match_operand:P 0 "address_operand" "p")
(const_int 0)
- (match_operand:SI 1 "const_int_operand" ""))]
+ (match_operand:SI 1 "const_int_operand"))]
"TARGET_PREFETCH_SSE"
{
static const char * const patterns[4] = {
(set_attr "memory" "none")])
(define_expand "stack_protect_set"
- [(match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" "")]
+ [(match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand")]
""
{
rtx (*insn)(rtx, rtx);
[(set_attr "type" "multi")])
(define_expand "stack_protect_test"
- [(match_operand 0 "memory_operand" "")
- (match_operand 1 "memory_operand" "")
- (match_operand 2 "" "")]
+ [(match_operand 0 "memory_operand")
+ (match_operand 1 "memory_operand")
+ (match_operand 2)]
""
{
rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
})
(define_insn "stack_protect_test_<mode>"
- [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ [(set (match_operand:CCZ 0 "flags_reg_operand")
(unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "memory_operand" "m")]
UNSPEC_SP_TEST))
[(set_attr "type" "multi")])
(define_insn "stack_tls_protect_test_<mode>"
- [(set (match_operand:CCZ 0 "flags_reg_operand" "")
+ [(set (match_operand:CCZ 0 "flags_reg_operand")
(unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
(match_operand:PTR 2 "const_int_operand" "i")]
UNSPEC_SP_TLS_TEST))
(set_attr "prefix_rep" "1")
(set_attr "prefix_extra" "1")
(set (attr "prefix_data16")
- (if_then_else (match_operand:HI 2 "" "")
+ (if_then_else (match_operand:HI 2)
(const_string "1")
(const_string "*")))
(set (attr "prefix_rex")
- (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+ (if_then_else (match_operand:QI 2 "ext_QIreg_operand")
(const_string "1")
(const_string "*")))
(set_attr "mode" "SI")])
(set_attr "mode" "DI")])
(define_expand "rdpmc"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:SI 1 "register_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:SI 1 "register_operand")]
""
{
rtx reg = gen_reg_rtx (DImode);
(set_attr "length" "2")])
(define_expand "rdtsc"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(unspec_volatile:DI [(const_int 0)] UNSPECV_RDTSC))]
""
{
(set_attr "length" "2")])
(define_expand "rdtscp"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:SI 1 "memory_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:SI 1 "memory_operand")]
""
{
rtx di = gen_rtx_UNSPEC_VOLATILE (DImode,
{
rtx (*insn)(rtx);
- insn = (TARGET_64BIT
+ insn = (Pmode == DImode
? gen_lwp_slwpcbdi
: gen_lwp_slwpcbsi);
(set (attr "length")
(symbol_ref "ix86_attr_length_address_default (insn) + 9"))])
-(define_insn "rdfsbase<mode>"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDFSBASE))]
- "TARGET_64BIT && TARGET_FSGSBASE"
- "rdfsbase %0"
- [(set_attr "type" "other")
- (set_attr "prefix_extra" "2")])
+(define_int_iterator RDFSGSBASE
+ [UNSPECV_RDFSBASE
+ UNSPECV_RDGSBASE])
-(define_insn "rdgsbase<mode>"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
- (unspec_volatile:SWI48 [(const_int 0)] UNSPECV_RDGSBASE))]
- "TARGET_64BIT && TARGET_FSGSBASE"
- "rdgsbase %0"
- [(set_attr "type" "other")
- (set_attr "prefix_extra" "2")])
+(define_int_iterator WRFSGSBASE
+ [UNSPECV_WRFSBASE
+ UNSPECV_WRGSBASE])
-(define_insn "wrfsbase<mode>"
- [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
- UNSPECV_WRFSBASE)]
+(define_int_attr fsgs
+ [(UNSPECV_RDFSBASE "fs")
+ (UNSPECV_RDGSBASE "gs")
+ (UNSPECV_WRFSBASE "fs")
+ (UNSPECV_WRGSBASE "gs")])
+
+(define_insn "rd<fsgs>base<mode>"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+ (unspec_volatile:SWI48 [(const_int 0)] RDFSGSBASE))]
"TARGET_64BIT && TARGET_FSGSBASE"
- "wrfsbase %0"
+ "rd<fsgs>base\t%0"
[(set_attr "type" "other")
(set_attr "prefix_extra" "2")])
-(define_insn "wrgsbase<mode>"
+(define_insn "wr<fsgs>base<mode>"
[(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")]
- UNSPECV_WRGSBASE)]
+ WRFSGSBASE)]
"TARGET_64BIT && TARGET_FSGSBASE"
- "wrgsbase %0"
+ "wr<fsgs>base\t%0"
[(set_attr "type" "other")
(set_attr "prefix_extra" "2")])
(define_insn "rdrand<mode>_1"
[(set (match_operand:SWI248 0 "register_operand" "=r")
- (unspec:SWI248 [(const_int 0)] UNSPEC_RDRAND))
+ (unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
(set (reg:CCC FLAGS_REG)
- (unspec:CCC [(const_int 0)] UNSPEC_RDRAND))]
+ (unspec_volatile:CCC [(const_int 0)] UNSPECV_RDRAND))]
"TARGET_RDRND"
"rdrand\t%0"
[(set_attr "type" "other")
;; Use "rep; nop", instead of "pause", to support older assemblers.
;; They have the same encoding.
(define_insn "*pause"
- [(set (match_operand:BLK 0 "" "")
+ [(set (match_operand:BLK 0)
(unspec:BLK [(match_dup 0)] UNSPEC_PAUSE))]
""
- "rep; nop"
+ "rep%; nop"
[(set_attr "length" "2")
(set_attr "memory" "unknown")])
+(define_expand "xbegin"
+ [(set (match_operand:SI 0 "register_operand")
+ (unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))]
+ "TARGET_RTM"
+{
+ rtx label = gen_label_rtx ();
+
+ operands[1] = force_reg (SImode, constm1_rtx);
+
+ emit_jump_insn (gen_xbegin_1 (operands[1], label));
+
+ emit_label (label);
+ LABEL_NUSES (label) = 1;
+
+ emit_move_insn (operands[0], operands[1]);
+
+ DONE;
+})
+
+(define_insn "xbegin_1"
+ [(set (pc)
+ (if_then_else (ne (unspec [(const_int 0)] UNSPEC_XBEGIN_ABORT)
+ (const_int 0))
+ (label_ref (match_operand 1))
+ (pc)))
+ (set (match_operand:SI 0 "register_operand" "+a")
+ (unspec_volatile:SI [(match_dup 0)] UNSPECV_XBEGIN))]
+ "TARGET_RTM"
+ "xbegin\t%l1"
+ [(set_attr "type" "other")
+ (set_attr "length" "6")])
+
+(define_insn "xend"
+ [(unspec_volatile [(const_int 0)] UNSPECV_XEND)]
+ "TARGET_RTM"
+ "xend"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
+(define_insn "xabort"
+ [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")]
+ UNSPECV_XABORT)]
+ "TARGET_RTM"
+ "xabort\t%0"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
+(define_expand "xtest"
+ [(set (match_operand:QI 0 "register_operand")
+ (unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))]
+ "TARGET_RTM"
+{
+ emit_insn (gen_xtest_1 ());
+
+ ix86_expand_setcc (operands[0], NE,
+ gen_rtx_REG (CCZmode, FLAGS_REG), const0_rtx);
+ DONE;
+})
+
+(define_insn "xtest_1"
+ [(set (reg:CCZ FLAGS_REG)
+ (unspec_volatile:CCZ [(const_int 0)] UNSPECV_XTEST))]
+ "TARGET_RTM"
+ "xtest"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
+
(include "mmx.md")
(include "sse.md")
(include "sync.md")
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