;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-;; 2001, 2002, 2003, 2004
+;; 2001, 2002, 2003, 2004, 2005
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
; For SSE/MMX support:
(UNSPEC_FIX 30)
+ (UNSPEC_FIX_NOTRUNC 31)
(UNSPEC_MASKMOV 32)
(UNSPEC_MOVMSK 33)
(UNSPEC_MOVNT 34)
push,pop,call,callv,leave,
str,cld,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint,
- sselog,sseiadd,sseishft,sseimul,
+ sselog,sselog1,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
(const_string "other"))
;; Main data type used by the insn
(define_attr "mode"
- "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
+ "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
(const_string "unknown"))
;; The CPU unit operations uses.
(define_attr "unit" "integer,i387,sse,mmx,unknown"
(cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,frndint")
(const_string "i387")
- (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
+ (eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
(const_string "sse")
(eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
(if_then_else (match_operand 1 "constant_call_address_operand" "")
(const_string "none")
(const_string "load"))
- (and (eq_attr "type" "alu1,negnot,ishift1")
+ (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
(match_operand 1 "memory_operand" ""))
(const_string "both")
(and (match_operand 0 "memory_operand" "")
"!alu1,negnot,ishift1,
imov,imovx,icmp,test,
fmov,fcmp,fsgn,
- sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
+ sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,sselog1,
mmx,mmxmov,mmxcmp,mmxcvt")
(match_operand 2 "memory_operand" ""))
(const_string "load")
(set_attr "length_immediate" "1")])
(define_insn "*movsi_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
- (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand"
+ "=r ,m ,!*y,!rm,!*y,!*x,!rm,!*x")
+ (match_operand:SI 1 "general_operand"
+ "rinm,rin,*y ,*y ,rm ,*x ,*x ,rm"))]
"(TARGET_INTER_UNIT_MOVES || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
(set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
(define_insn "*movsi_1_nointernunit"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
- (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand"
+ "=r ,m ,!*y,!m,!*y,!*x,!m,!*x")
+ (match_operand:SI 1 "general_operand"
+ "rinm,rin,*y ,*y,m ,*x ,*x,m"))]
"(!TARGET_INTER_UNIT_MOVES && !optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
""
"xchg{l}\t%1, %0"
[(set_attr "type" "imov")
- (set_attr "pent_pair" "np")
- (set_attr "athlon_decode" "vector")
(set_attr "mode" "SI")
- (set_attr "modrm" "0")])
+ (set_attr "pent_pair" "np")
+ (set_attr "athlon_decode" "vector")])
(define_expand "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
- "TARGET_PARTIAL_REG_STALL"
- "xchg{w}\t%1, %0"
+ "!TARGET_PARTIAL_REG_STALL || optimize_size"
+ "xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
+ (set_attr "mode" "SI")
(set_attr "pent_pair" "np")
- (set_attr "mode" "HI")
- (set_attr "modrm" "0")])
+ (set_attr "athlon_decode" "vector")])
(define_insn "*swaphi_2"
[(set (match_operand:HI 0 "register_operand" "+r")
(match_operand:HI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
- "! TARGET_PARTIAL_REG_STALL"
- "xchg{l}\t%k1, %k0"
+ "TARGET_PARTIAL_REG_STALL"
+ "xchg{w}\t%1, %0"
[(set_attr "type" "imov")
+ (set_attr "mode" "HI")
(set_attr "pent_pair" "np")
- (set_attr "mode" "SI")
- (set_attr "modrm" "0")])
+ (set_attr "athlon_decode" "vector")])
(define_expand "movstricthi"
[(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
(eq_attr "type" "imovx")
(const_string "SI")
(and (eq_attr "type" "imov")
- (and (eq_attr "alternative" "0,1,2")
+ (and (eq_attr "alternative" "0,1")
(ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
(const_int 0))))
(const_string "SI")
;; Avoid partial register stalls when not using QImode arithmetic
(and (eq_attr "type" "imov")
- (and (eq_attr "alternative" "0,1,2")
+ (and (eq_attr "alternative" "0,1")
(and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
(const_int 0))
(eq (symbol_ref "TARGET_QIMODE_MATH")
DONE;
})
-(define_insn "*swapqi"
+(define_insn "*swapqi_1"
[(set (match_operand:QI 0 "register_operand" "+r")
(match_operand:QI 1 "register_operand" "+r"))
(set (match_dup 1)
(match_dup 0))]
- ""
- "xchg{b}\t%1, %0"
+ "!TARGET_PARTIAL_REG_STALL || optimize_size"
+ "xchg{l}\t%k1, %k0"
[(set_attr "type" "imov")
+ (set_attr "mode" "SI")
(set_attr "pent_pair" "np")
+ (set_attr "athlon_decode" "vector")])
+
+(define_insn "*swapqi_2"
+ [(set (match_operand:QI 0 "register_operand" "+q")
+ (match_operand:QI 1 "register_operand" "+q"))
+ (set (match_dup 1)
+ (match_dup 0))]
+ "TARGET_PARTIAL_REG_STALL"
+ "xchg{b}\t%1, %0"
+ [(set_attr "type" "imov")
(set_attr "mode" "QI")
- (set_attr "modrm" "0")])
+ (set_attr "pent_pair" "np")
+ (set_attr "athlon_decode" "vector")])
(define_expand "movstrictqi"
[(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
"!TARGET_64BIT"
"#")
-(define_insn "pushdi2_rex64"
+(define_insn "*pushdi2_rex64"
[(set (match_operand:DI 0 "push_operand" "=<,!<")
(match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
"TARGET_64BIT"
(set_attr "length_immediate" "1")])
(define_insn "*movdi_2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
- (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=r ,o ,m*y,*y,m ,*Y,*Y,m ,*x,*x")
+ (match_operand:DI 1 "general_operand"
+ "riFo,riF,*y ,m ,*Y,*Y,m ,*x,*x,m "))]
"!TARGET_64BIT
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"@
movq\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
- (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
+ movq\t{%1, %0|%0, %1}
+ movlps\t{%1, %0|%0, %1}
+ movaps\t{%1, %0|%0, %1}
+ movlps\t{%1, %0|%0, %1}"
+ [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
+ (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,V2SF,V4SF,V2SF")])
(define_split
[(set (match_operand:DI 0 "push_operand" "")
"ix86_split_long_move (operands); DONE;")
(define_insn "*movdi_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y,!*Y,!*y")
- (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm,*y,*Y"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=r,r ,r,mr,!mr,!*y,!rm,!*y,!*x,!rm,!*x,!*x,!*y")
+ (match_operand:DI 1 "general_operand"
+ "Z ,rem,i,re,n ,*y ,*y ,rm ,*x ,*x ,rm ,*y ,*x"))]
"TARGET_64BIT
&& (TARGET_INTER_UNIT_MOVES || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
(set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI,DI,DI")])
(define_insn "*movdi_1_rex64_nointerunit"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
- (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=r,r ,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
+ (match_operand:DI 1 "general_operand"
+ "Z,rem,i,re,n ,*y ,*y,m ,*Y ,*Y,m"))]
"TARGET_64BIT
&& (!TARGET_INTER_UNIT_MOVES && !optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"TARGET_64BIT"
"xchg{q}\t%1, %0"
[(set_attr "type" "imov")
- (set_attr "pent_pair" "np")
- (set_attr "athlon_decode" "vector")
(set_attr "mode" "DI")
- (set_attr "modrm" "0")])
+ (set_attr "pent_pair" "np")
+ (set_attr "athlon_decode" "vector")])
+
+(define_expand "movti"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (match_operand:TI 1 "nonimmediate_operand" ""))]
+ "TARGET_SSE || TARGET_64BIT"
+{
+ if (TARGET_64BIT)
+ ix86_expand_move (TImode, operands);
+ else
+ ix86_expand_vector_move (TImode, operands);
+ DONE;
+})
+
+(define_insn "*movti_internal"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
+ (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
+ "TARGET_SSE && !TARGET_64BIT
+ && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "xorps\t%0, %0";
+ else
+ return "pxor\t%0, %0";
+ case 1:
+ case 2:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "movaps\t{%1, %0|%0, %1}";
+ else
+ return "movdqa\t{%1, %0|%0, %1}";
+ default:
+ abort ();
+ }
+}
+ [(set_attr "type" "ssemov,ssemov,ssemov")
+ (set (attr "mode")
+ (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (const_string "V4SF")
+
+ (eq_attr "alternative" "0,1")
+ (if_then_else
+ (ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (const_string "TI"))
+ (eq_attr "alternative" "2")
+ (if_then_else
+ (ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (const_string "TI"))]
+ (const_string "TI")))])
+
+(define_insn "*movti_rex64"
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
+ (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
+ "TARGET_64BIT
+ && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return "#";
+ case 2:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "xorps\t%0, %0";
+ else
+ return "pxor\t%0, %0";
+ case 3:
+ case 4:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "movaps\t{%1, %0|%0, %1}";
+ else
+ return "movdqa\t{%1, %0|%0, %1}";
+ default:
+ abort ();
+ }
+}
+ [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "2,3")
+ (if_then_else
+ (ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (const_string "TI"))
+ (eq_attr "alternative" "4")
+ (if_then_else
+ (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
+ (const_int 0))
+ (ne (symbol_ref "optimize_size")
+ (const_int 0)))
+ (const_string "V4SF")
+ (const_string "TI"))]
+ (const_string "DI")))])
+
+(define_split
+ [(set (match_operand:TI 0 "nonimmediate_operand" "")
+ (match_operand:TI 1 "general_operand" ""))]
+ "reload_completed && !SSE_REG_P (operands[0])
+ && !SSE_REG_P (operands[1])"
+ [(const_int 0)]
+ "ix86_split_long_move (operands); DONE;")
-
(define_expand "movsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:SF 1 "general_operand" ""))]
(set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
(define_insn "*movsf_1"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
- (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand"
+ "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!rm,!*y")
+ (match_operand:SF 1 "general_operand"
+ "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,rm ,*y ,*y"))]
"(TARGET_INTER_UNIT_MOVES || optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& (reload_in_progress || reload_completed
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(const_int 0))
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+ (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
(const_int 0)))
(const_string "V4SF")
(const_string "SF"))
(const_string "SF")))])
(define_insn "*movsf_1_nointerunit"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
- (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand"
+ "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!m,!*y")
+ (match_operand:SF 1 "general_operand"
+ "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,m ,*y,*y"))]
"(!TARGET_INTER_UNIT_MOVES && !optimize_size)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& (reload_in_progress || reload_completed
(if_then_else
(ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
(const_int 0))
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+ (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
(const_int 0)))
(const_string "V4SF")
(const_string "SF"))
(const_string "SF")))])
(define_insn "*swapsf"
- [(set (match_operand:SF 0 "register_operand" "+f")
- (match_operand:SF 1 "register_operand" "+f"))
+ [(set (match_operand:SF 0 "fp_register_operand" "+f")
+ (match_operand:SF 1 "fp_register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
- "reload_completed || !TARGET_SSE"
+ "reload_completed || TARGET_80387"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
;; when optimizing for size.
(define_insn "*movdf_nointeger"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
- (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand"
+ "=f#Y,m ,f#Y,*r ,o ,Y#f*x,Y#f*x,Y#f*x ,m ")
+ (match_operand:DF 1 "general_operand"
+ "fm#Y,f#Y,G ,*roF,F*r,C ,Y#f*x,HmY#f*x,Y#f*x"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
&& (reload_in_progress || reload_completed
abort ();
}
case 6:
+ case 7:
+ case 8:
switch (get_attr_mode (insn))
{
case MODE_V4SF:
return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
return "movapd\t{%1, %0|%0, %1}";
+ case MODE_TI:
+ return "movdqa\t{%1, %0|%0, %1}";
+ case MODE_DI:
+ return "movq\t{%1, %0|%0, %1}";
case MODE_DF:
return "movsd\t{%1, %0|%0, %1}";
+ case MODE_V1DF:
+ return "movlpd\t{%1, %0|%0, %1}";
+ case MODE_V2SF:
+ return "movlps\t{%1, %0|%0, %1}";
default:
abort ();
}
- case 7:
- if (get_attr_mode (insn) == MODE_V2DF)
- return "movlpd\t{%1, %0|%0, %1}";
- else
- return "movsd\t{%1, %0|%0, %1}";
- case 8:
- return "movsd\t{%1, %0|%0, %1}";
default:
abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set (attr "mode")
- (cond [(eq_attr "alternative" "3,4")
+ (cond [(eq_attr "alternative" "0,1,2")
+ (const_string "DF")
+ (eq_attr "alternative" "3,4")
(const_string "SI")
+
+ /* For SSE1, we have many fewer alternatives. */
+ (eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (cond [(eq_attr "alternative" "5,6")
+ (const_string "V4SF")
+ ]
+ (const_string "V2SF"))
+
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
(cond [(ne (symbol_ref "optimize_size")
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
(const_int 0))
- (const_string "TI")]
+ (const_string "TI")
+ ]
(const_string "V2DF"))
+
/* For architectures resolving dependencies on
whole SSE registers use APD move to break dependency
chains, otherwise use short move to avoid extra work.
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
- (const_string "V2DF")]
+ [(ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+ (const_int 0))
+ (const_string "V2DF")
+ ]
(const_string "DF"))
/* For architectures resolving dependencies on register
parts we may avoid extra work to zero out upper part
of register. */
(eq_attr "alternative" "7")
(if_then_else
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+ (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
(const_int 0))
- (const_string "V2DF")
- (const_string "DF"))]
- (const_string "DF")))])
+ (const_string "V1DF")
+ (const_string "DF"))
+ ]
+ (const_string "DF")))])
(define_insn "*movdf_integer"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
- (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand"
+ "=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf*x,Y#rf*x,Y#rf*x,m")
+ (match_operand:DF 1 "general_operand"
+ "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf*x,m ,Y#rf*x"))]
"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
&& ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
&& (reload_in_progress || reload_completed
abort ();
}
case 6:
+ case 7:
+ case 8:
switch (get_attr_mode (insn))
{
case MODE_V4SF:
return "movaps\t{%1, %0|%0, %1}";
case MODE_V2DF:
return "movapd\t{%1, %0|%0, %1}";
+ case MODE_TI:
+ return "movdqa\t{%1, %0|%0, %1}";
+ case MODE_DI:
+ return "movq\t{%1, %0|%0, %1}";
case MODE_DF:
return "movsd\t{%1, %0|%0, %1}";
+ case MODE_V1DF:
+ return "movlpd\t{%1, %0|%0, %1}";
+ case MODE_V2SF:
+ return "movlps\t{%1, %0|%0, %1}";
default:
abort ();
}
- case 7:
- if (get_attr_mode (insn) == MODE_V2DF)
- return "movlpd\t{%1, %0|%0, %1}";
- else
- return "movsd\t{%1, %0|%0, %1}";
- case 8:
- return "movsd\t{%1, %0|%0, %1}";
default:
abort();
}
[(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set (attr "mode")
- (cond [(eq_attr "alternative" "3,4")
+ (cond [(eq_attr "alternative" "0,1,2")
+ (const_string "DF")
+ (eq_attr "alternative" "3,4")
(const_string "SI")
+
+ /* For SSE1, we have many fewer alternatives. */
+ (eq (symbol_ref "TARGET_SSE2") (const_int 0))
+ (cond [(eq_attr "alternative" "5,6")
+ (const_string "V4SF")
+ ]
+ (const_string "V2SF"))
+
/* xorps is one byte shorter. */
(eq_attr "alternative" "5")
(cond [(ne (symbol_ref "optimize_size")
(const_string "V4SF")
(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
(const_int 0))
- (const_string "TI")]
+ (const_string "TI")
+ ]
(const_string "V2DF"))
+
/* For architectures resolving dependencies on
whole SSE registers use APD move to break dependency
- chains, otherwise use short move to avoid extra work.
+ chains, otherwise use short move to avoid extra work.
movaps encodes one byte shorter. */
(eq_attr "alternative" "6")
(cond
- [(ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
- (const_int 0))
- (const_string "V2DF")]
+ [(ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
+ (const_int 0))
+ (const_string "V2DF")
+ ]
(const_string "DF"))
/* For architectures resolving dependencies on register
parts we may avoid extra work to zero out upper part
of register. */
(eq_attr "alternative" "7")
(if_then_else
- (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+ (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
(const_int 0))
- (const_string "V2DF")
- (const_string "DF"))]
- (const_string "DF")))])
+ (const_string "V1DF")
+ (const_string "DF"))
+ ]
+ (const_string "DF")))])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
"ix86_split_long_move (operands); DONE;")
(define_insn "*swapdf"
- [(set (match_operand:DF 0 "register_operand" "+f")
- (match_operand:DF 1 "register_operand" "+f"))
+ [(set (match_operand:DF 0 "fp_register_operand" "+f")
+ (match_operand:DF 1 "fp_register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
- "reload_completed || !TARGET_SSE2"
+ "reload_completed || TARGET_80387"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
(match_operand:XF 1 "register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
- ""
+ "TARGET_80387"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
}
[(set_attr "type" "fxch")
(set_attr "mode" "XF")])
+
+(define_expand "movtf"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "")
+ (match_operand:TF 1 "nonimmediate_operand" ""))]
+ "TARGET_64BIT"
+{
+ ix86_expand_move (TFmode, operands);
+ DONE;
+})
+
+(define_insn "*movtf_internal"
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
+ (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
+ "TARGET_64BIT
+ && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return "#";
+ case 2:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "xorps\t%0, %0";
+ else
+ return "pxor\t%0, %0";
+ case 3:
+ case 4:
+ if (get_attr_mode (insn) == MODE_V4SF)
+ return "movaps\t{%1, %0|%0, %1}";
+ else
+ return "movdqa\t{%1, %0|%0, %1}";
+ default:
+ abort ();
+ }
+}
+ [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
+ (set (attr "mode")
+ (cond [(eq_attr "alternative" "2,3")
+ (if_then_else
+ (ne (symbol_ref "optimize_size")
+ (const_int 0))
+ (const_string "V4SF")
+ (const_string "TI"))
+ (eq_attr "alternative" "4")
+ (if_then_else
+ (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
+ (const_int 0))
+ (ne (symbol_ref "optimize_size")
+ (const_int 0)))
+ (const_string "V4SF")
+ (const_string "TI"))]
+ (const_string "DI")))])
+
+(define_split
+ [(set (match_operand:TF 0 "nonimmediate_operand" "")
+ (match_operand:TF 1 "general_operand" ""))]
+ "reload_completed && !SSE_REG_P (operands[0])
+ && !SSE_REG_P (operands[1])"
+ [(const_int 0)]
+ "ix86_split_long_move (operands); DONE;")
\f
;; Zero extension instructions
(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_extend:DF (match_operand:SF 1 "general_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
/* ??? Needed for compress_float_constant since all fp constants
are LEGITIMATE_CONSTANT_P. */
operands[1] = force_reg (SFmode, operands[1]);
})
-(define_insn "*extendsfdf2_1"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
+(define_insn "*extendsfdf2_mixed"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m#fY,Y#f")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
- "(TARGET_80387 || TARGET_SSE2)
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
[(set_attr "type" "fmov,fmov,ssecvt")
(set_attr "mode" "SF,XF,DF")])
-(define_insn "*extendsfdf2_1_sse_only"
+(define_insn "*extendsfdf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
- "!TARGET_80387 && TARGET_SSE2
+ "TARGET_SSE2 && TARGET_SSE_MATH
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"cvtss2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
-(define_expand "extendsfxf2"
- [(set (match_operand:XF 0 "nonimmediate_operand" "")
- (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
- "TARGET_80387"
-{
- /* ??? Needed for compress_float_constant since all fp constants
- are LEGITIMATE_CONSTANT_P. */
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
- operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
- operands[1] = force_reg (SFmode, operands[1]);
-})
-
-(define_insn "*extendsfxf2_1"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
- (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
+(define_insn "*extendsfdf2_i387"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
return output_387_reg_move (insn, operands);
case 1:
- /* There is no non-popping store to memory for XFmode. So if
- we need one, follow the store with a load. */
- if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0\n\tfld%z0\t%y0";
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
else
+ return "fst%z0\t%y0";
+
+ default:
+ abort ();
+ }
+}
+ [(set_attr "type" "fmov")
+ (set_attr "mode" "SF,XF")])
+
+(define_expand "extendsfxf2"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "")
+ (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
+ "TARGET_80387"
+{
+ /* ??? Needed for compress_float_constant since all fp constants
+ are LEGITIMATE_CONSTANT_P. */
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
+ if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ operands[1] = force_reg (SFmode, operands[1]);
+})
+
+(define_insn "*extendsfxf2_i387"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
+ (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
+ "TARGET_80387
+ && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ return output_387_reg_move (insn, operands);
+
+ case 1:
+ /* There is no non-popping store to memory for XFmode. So if
+ we need one, follow the store with a load. */
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
+ else
+ return "fstp%z0\t%y0\n\tfld%z0\t%y0";
default:
abort ();
operands[1] = force_reg (DFmode, operands[1]);
})
-(define_insn "*extenddfxf2_1"
+(define_insn "*extenddfxf2_i387"
[(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
"TARGET_80387
;; insn. So we pretend we can output to a reg in order to get better
;; register preferencing, but we really use a stack slot.
-(define_expand "truncdfsf2"
- [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (float_truncate:SF
- (match_operand:DF 1 "register_operand" "")))
- (clobber (match_dup 2))])]
- "TARGET_80387 || TARGET_SSE2"
- "
- if (!TARGET_80387)
- {
- emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
- DONE;
- }
- else if (flag_unsafe_math_optimizations)
- {
- rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
- emit_insn (gen_truncdfsf2_noop (reg, operands[1]));
- if (reg != operands[0])
- emit_move_insn (operands[0], reg);
- DONE;
- }
- else
- operands[2] = assign_386_stack_local (SFmode, 0);
-")
-
-(define_insn "truncdfsf2_noop"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_80387 && flag_unsafe_math_optimizations"
-{
- return output_387_reg_move (insn, operands);
-}
- [(set_attr "type" "fmov")
- (set_attr "mode" "SF")])
+;; Conversion from DFmode to SFmode.
-(define_insn "*truncdfsf2_1"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
+(define_expand "truncdfsf2"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
(float_truncate:SF
- (match_operand:DF 1 "register_operand" "f,f,f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
- "TARGET_80387 && !TARGET_SSE2"
+ (match_operand:DF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
- switch (which_alternative)
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
+ operands[1] = force_reg (DFmode, operands[1]);
+
+ if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
+ ;
+ else if (flag_unsafe_math_optimizations)
+ ;
+ else
{
- case 0:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
- default:
- abort ();
+ rtx temp = assign_386_stack_local (SFmode, 0);
+ emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
+ DONE;
}
-}
- [(set_attr "type" "fmov,multi,multi,multi")
- (set_attr "mode" "SF,SF,SF,SF")])
+})
-(define_insn "*truncdfsf2_1_sse"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
- (float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
- "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
+(define_expand "truncdfsf2_with_temp"
+ [(parallel [(set (match_operand:SF 0 "" "")
+ (float_truncate:SF (match_operand:DF 1 "" "")))
+ (clobber (match_operand:SF 2 "" ""))])]
+ "")
+
+(define_insn "*truncdfsf_fast_mixed"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f,Y")
+ (float_truncate:SF
+ (match_operand:DF 1 "nonimmediate_operand" "f ,f,Ym")))]
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
{
switch (which_alternative)
{
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
- case 4:
- return "#";
+ case 1:
+ return output_387_reg_move (insn, operands);
+ case 2:
+ return "cvtsd2ss\t{%1, %0|%0, %1}";
default:
abort ();
}
}
- [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
- (set_attr "mode" "SF,SF,SF,SF,DF")])
+ [(set_attr "type" "fmov,fmov,ssecvt")
+ (set_attr "mode" "SF")])
+
+;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
+;; because nothing we do here is unsafe.
+(define_insn "*truncdfsf_fast_sse"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=Y")
+ (float_truncate:SF
+ (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
+ "TARGET_SSE2 && TARGET_SSE_MATH"
+ "cvtsd2ss\t{%1, %0|%0, %1}"
+ [(set_attr "type" "ssecvt")
+ (set_attr "mode" "SF")])
+
+(define_insn "*truncdfsf_fast_i387"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
+ (float_truncate:SF
+ (match_operand:DF 1 "nonimmediate_operand" "f")))]
+ "TARGET_80387 && flag_unsafe_math_optimizations"
+ "* return output_387_reg_move (insn, operands);"
+ [(set_attr "type" "fmov")
+ (set_attr "mode" "SF")])
-(define_insn "*truncdfsf2_1_sse_nooverlap"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
+(define_insn "*truncdfsf_mixed"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
+ (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ym")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
+ "TARGET_MIX_SSE_I387"
{
switch (which_alternative)
{
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
- case 4:
- return "#";
- default:
- abort ();
- }
-}
- [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
- (set_attr "mode" "SF,SF,SF,SF,DF")])
-
-(define_insn "*truncdfsf2_2"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
- (float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
- "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
case 1:
- return "cvtsd2ss\t{%1, %0|%0, %1}";
+ return "#";
case 2:
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
+ return "cvtsd2ss\t{%1, %0|%0, %1}";
default:
abort ();
}
}
- [(set_attr "type" "ssecvt,ssecvt,fmov")
- (set_attr "athlon_decode" "vector,double,*")
- (set_attr "mode" "SF,SF,SF")])
+ [(set_attr "type" "fmov,multi,ssecvt")
+ (set_attr "mode" "SF")])
-(define_insn "*truncdfsf2_2_nooverlap"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
+(define_insn "*truncdfsf_i387"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
+ (match_operand:DF 1 "nonimmediate_operand" "f,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
+ "TARGET_80387"
{
switch (which_alternative)
{
case 0:
- return "#";
- case 1:
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
return "fstp%z0\t%y0";
else
return "fst%z0\t%y0";
+ case 1:
+ return "#";
default:
abort ();
}
}
- [(set_attr "type" "ssecvt,fmov")
- (set_attr "mode" "DF,SF")])
-
-(define_insn "*truncdfsf2_3"
- [(set (match_operand:SF 0 "memory_operand" "=m")
- (float_truncate:SF
- (match_operand:DF 1 "register_operand" "f")))]
- "TARGET_80387"
-{
- if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
- return "fstp%z0\t%y0";
- else
- return "fst%z0\t%y0";
-}
- [(set_attr "type" "fmov")
- (set_attr "mode" "SF")])
-
-(define_insn "truncdfsf2_sse_only"
- [(set (match_operand:SF 0 "register_operand" "=Y,Y")
- (float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
- "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
- "cvtsd2ss\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "athlon_decode" "vector,double")
+ [(set_attr "type" "fmov,multi")
(set_attr "mode" "SF")])
-(define_insn "*truncdfsf2_sse_only_nooverlap"
- [(set (match_operand:SF 0 "register_operand" "=&Y")
- (float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "mY")))]
- "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
- "#"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
-
-(define_split
- [(set (match_operand:SF 0 "memory_operand" "")
- (float_truncate:SF
- (match_operand:DF 1 "register_operand" "")))
- (clobber (match_operand:SF 2 "memory_operand" ""))]
- "TARGET_80387"
- [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
- "")
-
-; Avoid possible reformatting penalty on the destination by first
-; zeroing it out
(define_split
[(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))
+ (match_operand:DF 1 "fp_register_operand" "")))
(clobber (match_operand 2 "" ""))]
- "TARGET_80387 && reload_completed
- && SSE_REG_P (operands[0])
- && !STACK_REG_P (operands[1])"
- [(const_int 0)]
-{
- rtx src, dest;
- if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
- emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
- else
- {
- dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
- /* simplify_gen_subreg refuses to widen memory references. */
- if (GET_CODE (src) == SUBREG)
- alter_subreg (&src);
- if (reg_overlap_mentioned_p (operands[0], operands[1]))
- abort ();
- emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
- emit_insn (gen_cvtsd2ss (dest, dest, src));
- }
- DONE;
-})
-
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF
- (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_80387 && reload_completed
- && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
- [(const_int 0)]
+ "reload_completed"
+ [(set (match_dup 2) (match_dup 1))
+ (set (match_dup 0) (match_dup 2))]
{
- rtx src, dest;
- dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
- /* simplify_gen_subreg refuses to widen memory references. */
- if (GET_CODE (src) == SUBREG)
- alter_subreg (&src);
- if (reg_overlap_mentioned_p (operands[0], operands[1]))
- abort ();
- emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
- emit_insn (gen_cvtsd2ss (dest, dest, src));
- DONE;
+ operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
})
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (float_truncate:SF
- (match_operand:DF 1 "fp_register_operand" "")))
- (clobber (match_operand:SF 2 "memory_operand" ""))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
- (set (match_dup 0) (match_dup 2))]
- "")
+;; Conversion from XFmode to SFmode.
(define_expand "truncxfsf2"
[(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
(match_operand:XF 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_80387"
- "
+{
if (flag_unsafe_math_optimizations)
{
rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
- emit_insn (gen_truncxfsf2_noop (reg, operands[1]));
+ emit_insn (gen_truncxfsf2_i387_noop (reg, operands[1]));
if (reg != operands[0])
emit_move_insn (operands[0], reg);
DONE;
}
else
operands[2] = assign_386_stack_local (SFmode, 0);
- ")
+})
+
+(define_insn "*truncxfsf2_mixed"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
+ (float_truncate:SF
+ (match_operand:XF 1 "register_operand" "f,f,f,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
+ "TARGET_MIX_SSE_I387"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
+ default:
+ abort();
+ }
+}
+ [(set_attr "type" "fmov,multi,multi,multi")
+ (set_attr "mode" "SF")])
-(define_insn "truncxfsf2_noop"
+(define_insn "truncxfsf2_i387_noop"
[(set (match_operand:SF 0 "register_operand" "=f")
(float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
"TARGET_80387 && flag_unsafe_math_optimizations"
[(set_attr "type" "fmov")
(set_attr "mode" "SF")])
-(define_insn "*truncxfsf2_1"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
+(define_insn "*truncxfsf2_i387"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
(float_truncate:SF
- (match_operand:XF 1 "register_operand" "f,f,f,f")))
- (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
+ (match_operand:XF 1 "register_operand" "f,f,f")))
+ (clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]
"TARGET_80387"
{
switch (which_alternative)
else
return "fst%z0\t%y0";
default:
- abort();
+ abort ();
}
}
- [(set_attr "type" "fmov,multi,multi,multi")
+ [(set_attr "type" "fmov,multi,multi")
(set_attr "mode" "SF")])
-(define_insn "*truncxfsf2_2"
+(define_insn "*truncxfsf2_i387_1"
[(set (match_operand:SF 0 "memory_operand" "=m")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "f")))]
(set_attr "mode" "SF")])
(define_split
- [(set (match_operand:SF 0 "memory_operand" "")
+ [(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))]
- "TARGET_80387"
- [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
+ "TARGET_80387 && reload_completed"
+ [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
+ (set (match_dup 0) (match_dup 2))]
"")
(define_split
- [(set (match_operand:SF 0 "register_operand" "")
+ [(set (match_operand:SF 0 "memory_operand" "")
(float_truncate:SF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:SF 2 "memory_operand" ""))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
- (set (match_dup 0) (match_dup 2))]
+ "TARGET_80387"
+ [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
"")
+;; Conversion from XFmode to DFmode.
+
(define_expand "truncxfdf2"
[(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
(float_truncate:DF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_80387"
- "
+{
if (flag_unsafe_math_optimizations)
{
rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
- emit_insn (gen_truncxfdf2_noop (reg, operands[1]));
+ emit_insn (gen_truncxfdf2_i387_noop (reg, operands[1]));
if (reg != operands[0])
emit_move_insn (operands[0], reg);
DONE;
}
else
operands[2] = assign_386_stack_local (DFmode, 0);
- ")
-
-(define_insn "truncxfdf2_noop"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
- "TARGET_80387 && flag_unsafe_math_optimizations"
-{
- return output_387_reg_move (insn, operands);
-}
- [(set_attr "type" "fmov")
- (set_attr "mode" "DF")])
+})
-(define_insn "*truncxfdf2_1"
+(define_insn "*truncxfdf2_mixed"
[(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
(float_truncate:DF
(match_operand:XF 1 "register_operand" "f,f,f,f")))
(clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
- "TARGET_80387"
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387"
{
switch (which_alternative)
{
[(set_attr "type" "fmov,multi,multi,multi")
(set_attr "mode" "DF")])
-(define_insn "*truncxfdf2_2"
- [(set (match_operand:DF 0 "memory_operand" "=m")
+(define_insn "truncxfdf2_i387_noop"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
+ "TARGET_80387 && flag_unsafe_math_optimizations"
+{
+ return output_387_reg_move (insn, operands);
+}
+ [(set_attr "type" "fmov")
+ (set_attr "mode" "DF")])
+
+(define_insn "*truncxfdf2_i387"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
(float_truncate:DF
- (match_operand:XF 1 "register_operand" "f")))]
+ (match_operand:XF 1 "register_operand" "f,f,f")))
+ (clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]
+ "TARGET_80387"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
+ return "fstp%z0\t%y0";
+ else
+ return "fst%z0\t%y0";
+ default:
+ abort ();
+ }
+}
+ [(set_attr "type" "fmov,multi,multi")
+ (set_attr "mode" "DF")])
+
+(define_insn "*truncxfdf2_i387_1"
+ [(set (match_operand:DF 0 "memory_operand" "=m")
+ (float_truncate:DF
+ (match_operand:XF 1 "register_operand" "f")))]
"TARGET_80387"
{
if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
(set_attr "mode" "DF")])
(define_split
- [(set (match_operand:DF 0 "memory_operand" "")
+ [(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:DF 2 "memory_operand" ""))]
- "TARGET_80387"
- [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
+ "TARGET_80387 && reload_completed"
+ [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
+ (set (match_dup 0) (match_dup 2))]
"")
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
+ [(set (match_operand:DF 0 "memory_operand" "")
(float_truncate:DF
(match_operand:XF 1 "register_operand" "")))
(clobber (match_operand:DF 2 "memory_operand" ""))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
- (set (match_dup 0) (match_dup 2))]
+ "TARGET_80387"
+ [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
"")
-
\f
;; %%% Break up all these bad boys.
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:DF 1 "register_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2)"
{
if (TARGET_64BIT && TARGET_SSE2)
{
[(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
(fix:DI (match_operand:SF 1 "register_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE)"
{
- if (TARGET_SSE && TARGET_64BIT)
+ if (TARGET_64BIT && TARGET_SSE)
{
rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
;; of the machinery.
-(define_insn_and_split "*fix_truncdi_1"
+(define_insn_and_split "*fix_truncdi_i387"
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
(fix:DI (match_operand 1 "register_operand" "f,f")))
(clobber (reg:CC FLAGS_REG))]
;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
;; of the machinery.
-(define_insn_and_split "*fix_truncsi_1"
+(define_insn_and_split "*fix_truncsi_i387"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
(fix:SI (match_operand 1 "register_operand" "f,f")))
(clobber (reg:CC FLAGS_REG))]
;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
;; of the machinery.
-(define_insn_and_split "*fix_trunchi_1"
+(define_insn_and_split "*fix_trunchi_i387"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
(fix:HI (match_operand 1 "register_operand" "f,f")))
(clobber (reg:CC FLAGS_REG))]
(define_expand "floathisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE || TARGET_80387"
+ "TARGET_80387 || TARGET_SSE_MATH"
{
- if (TARGET_SSE && TARGET_SSE_MATH)
+ if (TARGET_SSE_MATH)
{
emit_insn (gen_floatsisf2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
}
})
-(define_insn "*floathisf2_1"
+(define_insn "*floathisf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
- (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
+ (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
"@
fild%z1\t%1
#"
(define_expand "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE || TARGET_80387"
+ "TARGET_80387 || TARGET_SSE_MATH"
"")
-(define_insn "*floatsisf2_i387"
+(define_insn "*floatsisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+ "TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatsisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE"
+ "TARGET_SSE_MATH"
"cvtsi2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "vector,double")
(set_attr "fp_int_src" "true")])
-; Avoid possible reformatting penalty on the destination by first
-; zeroing it out
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
- && SSE_REG_P (operands[0])"
- [(const_int 0)]
-{
- rtx dest;
- dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
- emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
- DONE;
-})
-
-(define_expand "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
- "")
-
-(define_insn "*floatdisf2_i387_only"
- [(set (match_operand:SF 0 "register_operand" "=f,?f")
- (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
+(define_insn "*floatsisf2_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
"@
fild%z1\t%1
#"
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
-(define_insn "*floatdisf2_i387"
+(define_expand "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "")
+ (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
+ "")
+
+(define_insn "*floatdisf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+ "TARGET_64BIT && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatdisf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x,x")
(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_64BIT && TARGET_SSE"
+ "TARGET_64BIT && TARGET_SSE_MATH"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "vector,double")
(set_attr "fp_int_src" "true")])
-; Avoid possible reformatting penalty on the destination by first
-; zeroing it out
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
- && SSE_REG_P (operands[0])"
- [(const_int 0)]
-{
- rtx dest;
- dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
- emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
- DONE;
-})
+(define_insn "*floatdisf2_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
+ "@
+ fild%z1\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "SF")
+ (set_attr "fp_int_src" "true")])
(define_expand "floathidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_SSE2 || TARGET_80387"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
- if (TARGET_SSE && TARGET_SSE_MATH)
+ if (TARGET_SSE2 && TARGET_SSE_MATH)
{
emit_insn (gen_floatsidf2 (operands[0],
convert_to_mode (SImode, operands[1], 0)));
}
})
-(define_insn "*floathidf2_1"
+(define_insn "*floathidf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
- (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
+ (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
"@
fild%z1\t%1
#"
(define_expand "floatsidf2"
[(set (match_operand:DF 0 "register_operand" "")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
- "TARGET_80387 || TARGET_SSE2"
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
-(define_insn "*floatsidf2_i387"
+(define_insn "*floatsidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatsidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE2"
+ "TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")])
-(define_expand "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
- "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
- "")
-
-(define_insn "*floatdidf2_i387_only"
- [(set (match_operand:DF 0 "register_operand" "=f,?f")
- (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
+(define_insn "*floatsidf2_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
"@
fild%z1\t%1
#"
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
-(define_insn "*floatdidf2_i387"
+(define_expand "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "")
+ (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
+ "")
+
+(define_insn "*floatdidf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
- "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fild%z1\t%1
#
(define_insn "*floatdidf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y,Y")
(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
- "TARGET_SSE2"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
[(set_attr "type" "sseicvt")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "double,direct")
(set_attr "fp_int_src" "true")])
+(define_insn "*floatdidf2_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+ "TARGET_80387"
+ "@
+ fild%z1\t%1
+ #"
+ [(set_attr "type" "fmov,multi")
+ (set_attr "mode" "DF")
+ (set_attr "fp_int_src" "true")])
+
(define_insn "floathixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_insn "floatsixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_insn "floatdixf2"
[(set (match_operand:XF 0 "register_operand" "=f,f")
- (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
+ (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
"TARGET_80387"
"@
fild%z1\t%1
(define_split
[(set (match_operand 0 "fp_register_operand" "")
(float (match_operand 1 "register_operand" "")))]
- "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
+ "reload_completed
+ && TARGET_80387
+ && FLOAT_MODE_P (GET_MODE (operands[0]))"
[(const_int 0)]
{
operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
(define_expand "floatunssisf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SI 1 "register_operand" ""))]
- "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
+ "!TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
- "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
+ "TARGET_64BIT && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DI 1 "register_operand" ""))]
- "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
+ "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
\f
;; SSE extract/set expanders
-(define_expand "vec_setv2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:DF 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE2"
-{
- switch (INTVAL (operands[2]))
- {
- case 0:
- emit_insn (gen_sse2_movsd (operands[0], operands[0],
- simplify_gen_subreg (V2DFmode, operands[1],
- DFmode, 0)));
- break;
- case 1:
- {
- rtx op1 = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
-
- emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], op1));
- }
- break;
- default:
- abort ();
- }
- DONE;
-})
-
-(define_expand "vec_extractv2df"
- [(match_operand:DF 0 "register_operand" "")
- (match_operand:V2DF 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE2"
-{
- switch (INTVAL (operands[2]))
- {
- case 0:
- emit_move_insn (operands[0], gen_lowpart (DFmode, operands[1]));
- break;
- case 1:
- {
- rtx dest = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
-
- emit_insn (gen_sse2_unpckhpd (dest, operands[1], operands[1]));
- }
- break;
- default:
- abort ();
- }
- DONE;
-})
-
-(define_expand "vec_initv2df"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand 1 "" "")]
- "TARGET_SSE2"
-{
- ix86_expand_vector_init (operands[0], operands[1]);
- DONE;
-})
-
-(define_expand "vec_setv4sf"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:SF 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- switch (INTVAL (operands[2]))
- {
- case 0:
- emit_insn (gen_sse_movss (operands[0], operands[0],
- simplify_gen_subreg (V4SFmode, operands[1],
- SFmode, 0)));
- break;
- case 1:
- {
- rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[0]);
- emit_insn (gen_sse_unpcklps (operands[0], operands[0], operands[0]));
- emit_insn (gen_sse_movss (operands[0], operands[0], op1));
- emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
- GEN_INT (1 + (0<<2) + (2<<4) + (3<<6))));
- }
- break;
- case 2:
- {
- rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[0]);
- emit_insn (gen_sse_movss (tmp, tmp, op1));
- emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
- GEN_INT (0 + (1<<2) + (0<<4) + (3<<6))));
- }
- break;
- case 3:
- {
- rtx op1 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[0]);
- emit_insn (gen_sse_movss (tmp, tmp, op1));
- emit_insn (gen_sse_shufps (operands[0], operands[0], tmp,
- GEN_INT (0 + (1<<2) + (2<<4) + (0<<6))));
- }
- break;
- default:
- abort ();
- }
- DONE;
-})
-
-(define_expand "vec_extractv4sf"
- [(match_operand:SF 0 "register_operand" "")
- (match_operand:V4SF 1 "register_operand" "")
- (match_operand 2 "const_int_operand" "")]
- "TARGET_SSE"
-{
- switch (INTVAL (operands[2]))
- {
- case 0:
- emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
- break;
- case 1:
- {
- rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[1]);
- emit_insn (gen_sse_shufps (op0, tmp, tmp,
- const1_rtx));
- }
- break;
- case 2:
- {
- rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[1]);
- emit_insn (gen_sse_unpckhps (op0, tmp, tmp));
- }
- break;
- case 3:
- {
- rtx op0 = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- rtx tmp = gen_reg_rtx (V4SFmode);
-
- emit_move_insn (tmp, operands[1]);
- emit_insn (gen_sse_shufps (op0, tmp, tmp,
- GEN_INT (3)));
- }
- break;
- default:
- abort ();
- }
- DONE;
-})
-
-(define_expand "vec_initv4sf"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand 1 "" "")]
- "TARGET_SSE"
-{
- ix86_expand_vector_init (operands[0], operands[1]);
- DONE;
-})
\f
;; Add instructions
(define_insn_and_split "*lea_general_1"
[(set (match_operand 0 "register_operand" "=r")
- (plus (plus (match_operand 1 "index_register_operand" "r")
+ (plus (plus (match_operand 1 "index_register_operand" "l")
(match_operand 2 "register_operand" "r"))
(match_operand 3 "immediate_operand" "i")))]
"(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
(define_insn_and_split "*lea_general_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
+ (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
(match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 3 "immediate_operand" "i"))))]
"TARGET_64BIT"
(define_insn_and_split "*lea_general_2"
[(set (match_operand 0 "register_operand" "=r")
- (plus (mult (match_operand 1 "index_register_operand" "r")
+ (plus (mult (match_operand 1 "index_register_operand" "l")
(match_operand 2 "const248_operand" "i"))
(match_operand 3 "nonmemory_operand" "ri")))]
"(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
(define_insn_and_split "*lea_general_2_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
+ (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
(match_operand:SI 2 "const248_operand" "n"))
(match_operand:SI 3 "nonmemory_operand" "ri"))))]
"TARGET_64BIT"
(define_insn_and_split "*lea_general_3"
[(set (match_operand 0 "register_operand" "=r")
- (plus (plus (mult (match_operand 1 "index_register_operand" "r")
+ (plus (plus (mult (match_operand 1 "index_register_operand" "l")
(match_operand 2 "const248_operand" "i"))
(match_operand 3 "register_operand" "r"))
(match_operand 4 "immediate_operand" "i")))]
(define_insn_and_split "*lea_general_3_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
- (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
- (match_operand:SI 2 "const248_operand" "n"))
+ (plus:SI (plus:SI (mult:SI
+ (match_operand:SI 1 "index_register_operand" "l")
+ (match_operand:SI 2 "const248_operand" "n"))
(match_operand:SI 3 "register_operand" "r"))
(match_operand:SI 4 "immediate_operand" "i"))))]
"TARGET_64BIT"
(define_insn "*adddi_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
+ (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
{
(define_insn "*addsi_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
+ (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (PLUS, SImode, operands)"
{
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
- (match_operand:SI 2 "general_operand" "rmni,rni"))))
+ (match_operand:SI 2 "general_operand" "rmni,lni"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
{
(define_insn "*addhi_1_lea"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
- (match_operand:HI 2 "general_operand" "ri,rm,rni")))
+ (match_operand:HI 2 "general_operand" "ri,rm,lni")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, HImode, operands)"
(const_string "alu")))
(set_attr "mode" "HI")])
-; See comments above addsi_3_imm for details.
+; See comments above addsi_4 for details.
(define_insn "*addhi_4"
[(set (reg FLAGS_REG)
(compare (match_operand:HI 1 "nonimmediate_operand" "0")
(define_insn "*addqi_1_lea"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
(plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
- (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
+ (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
&& ix86_binary_operator_ok (PLUS, QImode, operands)"
(if_then_else (match_operand:QI 1 "incdec_operand" "")
(const_string "incdec")
(const_string "alu1")))
+ (set (attr "memory")
+ (if_then_else (match_operand 1 "memory_operand" "")
+ (const_string "load")
+ (const_string "none")))
(set_attr "mode" "QI")])
(define_insn "*addqi_2"
(const_string "alu")))
(set_attr "mode" "QI")])
-; See comments above addsi_3_imm for details.
+; See comments above addsi_4 for details.
(define_insn "*addqi_4"
[(set (reg FLAGS_REG)
(compare (match_operand:QI 1 "nonimmediate_operand" "0")
;; Changing of sign for FP values is doable using integer unit too.
(define_expand "negsf2"
- [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
- "if (TARGET_SSE)
- {
- /* In case operand is in memory, we will not use SSE. */
- if (memory_operand (operands[0], VOIDmode)
- && rtx_equal_p (operands[0], operands[1]))
- emit_insn (gen_negsf2_memory (operands[0], operands[1]));
- else
- {
- /* Using SSE is tricky, since we need bitwise negation of -0
- in register. */
- rtx reg = gen_reg_rtx (SFmode);
- rtx dest = operands[0];
- rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
-
- operands[1] = force_reg (SFmode, operands[1]);
- operands[0] = force_reg (SFmode, operands[0]);
- reg = force_reg (V4SFmode,
- gen_rtx_CONST_VECTOR (V4SFmode,
- gen_rtvec (4, imm, CONST0_RTX (SFmode),
- CONST0_RTX (SFmode),
- CONST0_RTX (SFmode))));
- emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
- if (dest != operands[0])
- emit_move_insn (dest, operands[0]);
- }
- DONE;
- }
- ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || TARGET_SSE_MATH"
+ "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
-(define_insn "negsf2_memory"
- [(set (match_operand:SF 0 "memory_operand" "=m")
- (neg:SF (match_operand:SF 1 "memory_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_unary_operator_ok (NEG, SFmode, operands)"
- "#")
+(define_expand "abssf2"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "")
+ (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || TARGET_SSE_MATH"
+ "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
-(define_insn "negsf2_ifs"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
- (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
- (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
+(define_insn "*absnegsf2_mixed"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
+ (match_operator:SF 3 "absneg_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#fr,0 ,0")]))
+ (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_SSE
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
+ "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
"#")
-(define_split
- [(set (match_operand:SF 0 "memory_operand" "")
- (neg:SF (match_operand:SF 1 "memory_operand" "")))
- (use (match_operand:SF 2 "" ""))
+(define_insn "*absnegsf2_sse"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=x#r,x#r,rm#x")
+ (match_operator:SF 3 "absneg_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#r,0")]))
+ (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X"))
(clobber (reg:CC FLAGS_REG))]
- ""
- [(parallel [(set (match_dup 0)
- (neg:SF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
+ "TARGET_SSE_MATH
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
+ "#")
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (neg:SF (match_operand:SF 1 "register_operand" "")))
- (use (match_operand:V4SF 2 "" ""))
+(define_insn "*absnegsf2_i387"
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
+ (match_operator:SF 3 "absneg_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "reload_completed && !SSE_REG_P (operands[0])"
- [(parallel [(set (match_dup 0)
- (neg:SF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
+ "#")
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (neg:SF (match_operand:SF 1 "register_operand" "")))
- (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && SSE_REG_P (operands[0])"
- [(set (match_dup 0)
- (xor:V4SF (match_dup 1)
- (match_dup 2)))]
-{
- operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- if (operands_match_p (operands[0], operands[2]))
- {
- rtx tmp;
- tmp = operands[1];
- operands[1] = operands[2];
- operands[2] = tmp;
- }
-})
+(define_expand "negdf2"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
+ (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
+ "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
+(define_expand "absdf2"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "")
+ (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
+ "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*negsf2_if"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
- (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
+(define_insn "*absnegdf2_mixed"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
+ (match_operator:DF 3 "absneg_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#fr,0 ,0")]))
+ (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && !TARGET_SSE
- && ix86_unary_operator_ok (NEG, SFmode, operands)"
+ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
"#")
-(define_split
- [(set (match_operand:SF 0 "fp_register_operand" "")
- (neg:SF (match_operand:SF 1 "register_operand" "")))
+(define_insn "*absnegdf2_sse"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#r,Y#r,rm#Y")
+ (match_operator:DF 3 "absneg_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#r,0")]))
+ (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X"))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (neg:SF (match_dup 1)))]
- "")
+ "TARGET_SSE2 && TARGET_SSE_MATH
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+ "#")
-(define_split
- [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
- (neg:SF (match_operand:SF 1 "register_operand" "")))
+(define_insn "*absnegdf2_i387"
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
+ (match_operator:DF 3 "absneg_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[1] = gen_int_mode (0x80000000, SImode);
- operands[0] = gen_lowpart (SImode, operands[0]);")
+ "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
+ "#")
-(define_split
- [(set (match_operand 0 "memory_operand" "")
- (neg (match_operand 1 "memory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
- [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
-{
- int size = GET_MODE_SIZE (GET_MODE (operands[1]));
-
- if (GET_MODE (operands[1]) == XFmode)
- size = 10;
- operands[0] = adjust_address (operands[0], QImode, size - 1);
- operands[1] = gen_int_mode (0x80, QImode);
-})
-
-(define_expand "negdf2"
- [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+(define_expand "negxf2"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "")
+ (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
"TARGET_80387"
- "if (TARGET_SSE2)
- {
- /* In case operand is in memory, we will not use SSE. */
- if (memory_operand (operands[0], VOIDmode)
- && rtx_equal_p (operands[0], operands[1]))
- emit_insn (gen_negdf2_memory (operands[0], operands[1]));
- else
- {
- /* Using SSE is tricky, since we need bitwise negation of -0
- in register. */
- rtx reg;
-#if HOST_BITS_PER_WIDE_INT >= 64
- rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
-#else
- rtx imm = immed_double_const (0, 0x80000000, DImode);
-#endif
- rtx dest = operands[0];
-
- operands[1] = force_reg (DFmode, operands[1]);
- operands[0] = force_reg (DFmode, operands[0]);
- imm = gen_lowpart (DFmode, imm);
- reg = force_reg (V2DFmode,
- gen_rtx_CONST_VECTOR (V2DFmode,
- gen_rtvec (2, imm, CONST0_RTX (DFmode))));
- emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
- if (dest != operands[0])
- emit_move_insn (dest, operands[0]);
- }
- DONE;
- }
- ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
-
-(define_insn "negdf2_memory"
- [(set (match_operand:DF 0 "memory_operand" "=m")
- (neg:DF (match_operand:DF 1 "memory_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_unary_operator_ok (NEG, DFmode, operands)"
- "#")
+ "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
-(define_insn "negdf2_ifs"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_SSE2
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
- "#")
+(define_expand "absxf2"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "")
+ (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
+ "TARGET_80387"
+ "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
-(define_insn "*negdf2_ifs_rex64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
+(define_insn "*absnegxf2_i387"
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
+ (match_operator:XF 3 "absneg_operator"
+ [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_SSE2
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
+ "TARGET_80387
+ && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
"#")
-(define_split
- [(set (match_operand:DF 0 "memory_operand" "")
- (neg:DF (match_operand:DF 1 "memory_operand" "")))
- (use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- ""
- [(parallel [(set (match_dup 0)
- (neg:DF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
-
-(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
- (use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && !SSE_REG_P (operands[0])
- && (!TARGET_64BIT || FP_REG_P (operands[0]))"
- [(parallel [(set (match_dup 0)
- (neg:DF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
+;; Splitters for fp abs and neg.
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
- (use (match_operand:V2DF 2 "" ""))
+ [(set (match_operand 0 "fp_register_operand" "")
+ (match_operator 1 "absneg_operator" [(match_dup 0)]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
- [(parallel [(set (match_dup 0)
- (xor:DI (match_dup 1) (match_dup 2)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[0] = gen_lowpart (DImode, operands[0]);
- operands[1] = gen_lowpart (DImode, operands[1]);
- operands[2] = gen_lowpart (DImode, operands[2]);")
+ "reload_completed"
+ [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
+ [(set (match_operand 0 "register_operand" "")
+ (match_operator 3 "absneg_operator"
+ [(match_operand 1 "register_operand" "")]))
+ (use (match_operand 2 "nonimmediate_operand" ""))
(clobber (reg:CC FLAGS_REG))]
"reload_completed && SSE_REG_P (operands[0])"
- [(set (match_dup 0)
- (xor:V2DF (match_dup 1)
- (match_dup 2)))]
+ [(set (match_dup 0) (match_dup 3))]
{
- operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
- operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
- /* Avoid possible reformatting on the operands. */
- if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
- emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
+ enum machine_mode mode = GET_MODE (operands[0]);
+ enum machine_mode vmode = GET_MODE (operands[2]);
+ rtx tmp;
+
+ operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
+ operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
if (operands_match_p (operands[0], operands[2]))
{
- rtx tmp;
tmp = operands[1];
operands[1] = operands[2];
operands[2] = tmp;
}
+ if (GET_CODE (operands[3]) == ABS)
+ tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
+ else
+ tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
+ operands[3] = tmp;
})
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*negdf2_if"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_80387
- && ix86_unary_operator_ok (NEG, DFmode, operands)"
- "#")
-
-;; FIXME: We should to allow integer registers here. Problem is that
-;; we need another scratch register to get constant from.
-;; Forcing constant to mem if no register available in peep2 should be
-;; safe even for PIC mode, because of RIP relative addressing.
-(define_insn "*negdf2_if_rex64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_80387
- && ix86_unary_operator_ok (NEG, DFmode, operands)"
- "#")
-
(define_split
- [(set (match_operand:DF 0 "fp_register_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
+ [(set (match_operand:SF 0 "register_operand" "")
+ (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
+ (use (match_operand:V4SF 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (neg:DF (match_dup 1)))]
- "")
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (match_dup 1))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ rtx tmp;
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ if (GET_CODE (operands[1]) == ABS)
+ {
+ tmp = gen_int_mode (0x7fffffff, SImode);
+ tmp = gen_rtx_AND (SImode, operands[0], tmp);
+ }
+ else
+ {
+ tmp = gen_int_mode (0x80000000, SImode);
+ tmp = gen_rtx_XOR (SImode, operands[0], tmp);
+ }
+ operands[1] = tmp;
+})
(define_split
- [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
- (neg:DF (match_operand:DF 1 "register_operand" "")))
+ [(set (match_operand:DF 0 "register_operand" "")
+ (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[4] = gen_int_mode (0x80000000, SImode);
- split_di (operands+0, 1, operands+2, operands+3);")
-
-(define_expand "negxf2"
- [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
- (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
- "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
+{
+ rtx tmp;
+ if (TARGET_64BIT)
+ {
+ tmp = gen_lowpart (DImode, operands[0]);
+ tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
+ operands[0] = tmp;
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*negxf2_if"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
- (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387
- && ix86_unary_operator_ok (NEG, XFmode, operands)"
- "#")
+ if (GET_CODE (operands[1]) == ABS)
+ tmp = const0_rtx;
+ else
+ tmp = gen_rtx_NOT (DImode, tmp);
+ }
+ else
+ {
+ operands[0] = gen_highpart (SImode, operands[0]);
+ if (GET_CODE (operands[1]) == ABS)
+ {
+ tmp = gen_int_mode (0x7fffffff, SImode);
+ tmp = gen_rtx_AND (SImode, operands[0], tmp);
+ }
+ else
+ {
+ tmp = gen_int_mode (0x80000000, SImode);
+ tmp = gen_rtx_XOR (SImode, operands[0], tmp);
+ }
+ }
+ operands[1] = tmp;
+})
(define_split
- [(set (match_operand:XF 0 "fp_register_operand" "")
- (neg:XF (match_operand:XF 1 "register_operand" "")))
+ [(set (match_operand:XF 0 "register_operand" "")
+ (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (neg:XF (match_dup 1)))]
- "")
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (match_dup 1))
+ (clobber (reg:CC FLAGS_REG))])]
+{
+ rtx tmp;
+ operands[0] = gen_rtx_REG (SImode,
+ true_regnum (operands[0])
+ + (TARGET_64BIT ? 1 : 2));
+ if (GET_CODE (operands[1]) == ABS)
+ {
+ tmp = GEN_INT (0x7fff);
+ tmp = gen_rtx_AND (SImode, operands[0], tmp);
+ }
+ else
+ {
+ tmp = GEN_INT (0x8000);
+ tmp = gen_rtx_XOR (SImode, operands[0], tmp);
+ }
+ operands[1] = tmp;
+})
(define_split
- [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
- (neg:XF (match_operand:XF 1 "register_operand" "")))
+ [(set (match_operand 0 "memory_operand" "")
+ (match_operator 1 "absneg_operator" [(match_dup 0)]))
+ (use (match_operand 2 "" ""))
(clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
+ "reload_completed"
+ [(parallel [(set (match_dup 0) (match_dup 1))
(clobber (reg:CC FLAGS_REG))])]
- "operands[1] = GEN_INT (0x8000);
- operands[0] = gen_rtx_REG (SImode,
- true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
+{
+ enum machine_mode mode = GET_MODE (operands[0]);
+ int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
+ rtx tmp;
+
+ operands[0] = adjust_address (operands[0], QImode, size - 1);
+ if (GET_CODE (operands[1]) == ABS)
+ {
+ tmp = gen_int_mode (0x7f, QImode);
+ tmp = gen_rtx_AND (QImode, operands[0], tmp);
+ }
+ else
+ {
+ tmp = gen_int_mode (0x80, QImode);
+ tmp = gen_rtx_XOR (QImode, operands[0], tmp);
+ }
+ operands[1] = tmp;
+})
-;; Conditionalize these after reload. If they matches before reload, we
+;; Conditionalize these after reload. If they match before reload, we
;; lose the clobber and ability to use integer instructions.
(define_insn "*negsf2_1"
[(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
-(define_insn "*negextendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (neg:DF (float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387"
+(define_insn "*negxf2_1"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (neg:XF (match_operand:XF 1 "register_operand" "0")))]
+ "TARGET_80387 && reload_completed"
"fchs"
[(set_attr "type" "fsgn")
+ (set_attr "mode" "XF")])
+
+(define_insn "*abssf2_1"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))]
+ "TARGET_80387 && reload_completed"
+ "fabs"
+ [(set_attr "type" "fsgn")
+ (set_attr "mode" "SF")])
+
+(define_insn "*absdf2_1"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (abs:DF (match_operand:DF 1 "register_operand" "0")))]
+ "TARGET_80387 && reload_completed"
+ "fabs"
+ [(set_attr "type" "fsgn")
(set_attr "mode" "DF")])
-(define_insn "*negxf2_1"
+(define_insn "*absxf2_1"
[(set (match_operand:XF 0 "register_operand" "=f")
- (neg:XF (match_operand:XF 1 "register_operand" "0")))]
+ (abs:XF (match_operand:XF 1 "register_operand" "0")))]
"TARGET_80387 && reload_completed"
+ "fabs"
+ [(set_attr "type" "fsgn")
+ (set_attr "mode" "DF")])
+
+(define_insn "*negextendsfdf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (neg:DF (float_extend:DF
+ (match_operand:SF 1 "register_operand" "0"))))]
+ "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
"fchs"
[(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
+ (set_attr "mode" "DF")])
(define_insn "*negextenddfxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
"fchs"
[(set_attr "type" "fsgn")
(set_attr "mode" "XF")])
-\f
-;; Absolute value instructions
-(define_expand "abssf2"
- [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
+(define_insn "*absextendsfdf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (abs:DF (float_extend:DF
+ (match_operand:SF 1 "register_operand" "0"))))]
+ "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
+ "fabs"
+ [(set_attr "type" "fsgn")
+ (set_attr "mode" "DF")])
+
+(define_insn "*absextenddfxf2"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (abs:XF (float_extend:XF
+ (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_80387"
- "if (TARGET_SSE)
- {
- /* In case operand is in memory, we will not use SSE. */
- if (memory_operand (operands[0], VOIDmode)
- && rtx_equal_p (operands[0], operands[1]))
- emit_insn (gen_abssf2_memory (operands[0], operands[1]));
- else
- {
- /* Using SSE is tricky, since we need bitwise negation of -0
- in register. */
- rtx reg = gen_reg_rtx (V4SFmode);
- rtx dest = operands[0];
- rtx imm;
-
- operands[1] = force_reg (SFmode, operands[1]);
- operands[0] = force_reg (SFmode, operands[0]);
- imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
- reg = force_reg (V4SFmode,
- gen_rtx_CONST_VECTOR (V4SFmode,
- gen_rtvec (4, imm, CONST0_RTX (SFmode),
- CONST0_RTX (SFmode),
- CONST0_RTX (SFmode))));
- emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
- if (dest != operands[0])
- emit_move_insn (dest, operands[0]);
- }
- DONE;
- }
- ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
+ "fabs"
+ [(set_attr "type" "fsgn")
+ (set_attr "mode" "XF")])
-(define_insn "abssf2_memory"
- [(set (match_operand:SF 0 "memory_operand" "=m")
- (abs:SF (match_operand:SF 1 "memory_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_unary_operator_ok (ABS, SFmode, operands)"
- "#")
+(define_insn "*absextendsfxf2"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (abs:XF (float_extend:XF
+ (match_operand:SF 1 "register_operand" "0"))))]
+ "TARGET_80387"
+ "fabs"
+ [(set_attr "type" "fsgn")
+ (set_attr "mode" "XF")])
+\f
+;; One complement instructions
-(define_insn "abssf2_ifs"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
- (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
- (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_SSE
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
- "#")
+(define_expand "one_cmpldi2"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
+ "TARGET_64BIT"
+ "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
-(define_split
- [(set (match_operand:SF 0 "memory_operand" "")
- (abs:SF (match_operand:SF 1 "memory_operand" "")))
- (use (match_operand:V4SF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- ""
- [(parallel [(set (match_dup 0)
- (abs:SF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
+(define_insn "*one_cmpldi2_1_rex64"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
+ "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
+ "not{q}\t%0"
+ [(set_attr "type" "negnot")
+ (set_attr "mode" "DI")])
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (abs:SF (match_operand:SF 1 "register_operand" "")))
- (use (match_operand:V4SF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && !SSE_REG_P (operands[0])"
- [(parallel [(set (match_dup 0)
- (abs:SF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
-
-(define_split
- [(set (match_operand:SF 0 "register_operand" "")
- (abs:SF (match_operand:SF 1 "register_operand" "")))
- (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && SSE_REG_P (operands[0])"
- [(set (match_dup 0)
- (and:V4SF (match_dup 1)
- (match_dup 2)))]
-{
- operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
- operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0);
- if (operands_match_p (operands[0], operands[2]))
- {
- rtx tmp;
- tmp = operands[1];
- operands[1] = operands[2];
- operands[2] = tmp;
- }
-})
-
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*abssf2_if"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
- (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
- "#")
-
-(define_split
- [(set (match_operand:SF 0 "fp_register_operand" "")
- (abs:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (abs:SF (match_dup 1)))]
- "")
-
-(define_split
- [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
- (abs:SF (match_operand:SF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[1] = gen_int_mode (~0x80000000, SImode);
- operands[0] = gen_lowpart (SImode, operands[0]);")
-
-(define_split
- [(set (match_operand 0 "memory_operand" "")
- (abs (match_operand 1 "memory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
- [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
-{
- int size = GET_MODE_SIZE (GET_MODE (operands[1]));
-
- if (GET_MODE (operands[1]) == XFmode)
- size = 10;
- operands[0] = adjust_address (operands[0], QImode, size - 1);
- operands[1] = gen_int_mode (~0x80, QImode);
-})
-
-(define_expand "absdf2"
- [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
- "if (TARGET_SSE2)
- {
- /* In case operand is in memory, we will not use SSE. */
- if (memory_operand (operands[0], VOIDmode)
- && rtx_equal_p (operands[0], operands[1]))
- emit_insn (gen_absdf2_memory (operands[0], operands[1]));
- else
- {
- /* Using SSE is tricky, since we need bitwise negation of -0
- in register. */
- rtx reg = gen_reg_rtx (V2DFmode);
-#if HOST_BITS_PER_WIDE_INT >= 64
- rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
-#else
- rtx imm = immed_double_const (~0, ~0x80000000, DImode);
-#endif
- rtx dest = operands[0];
-
- operands[1] = force_reg (DFmode, operands[1]);
- operands[0] = force_reg (DFmode, operands[0]);
-
- /* Produce LONG_DOUBLE with the proper immediate argument. */
- imm = gen_lowpart (DFmode, imm);
- reg = force_reg (V2DFmode,
- gen_rtx_CONST_VECTOR (V2DFmode,
- gen_rtvec (2, imm, CONST0_RTX (DFmode))));
- emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
- if (dest != operands[0])
- emit_move_insn (dest, operands[0]);
- }
- DONE;
- }
- ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
-
-(define_insn "absdf2_memory"
- [(set (match_operand:DF 0 "memory_operand" "=m")
- (abs:DF (match_operand:DF 1 "memory_operand" "0")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_unary_operator_ok (ABS, DFmode, operands)"
- "#")
-
-(define_insn "absdf2_ifs"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
- (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_SSE2
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
- "#")
-
-(define_insn "*absdf2_ifs_rex64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
- (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_SSE2
- && (reload_in_progress || reload_completed
- || (register_operand (operands[0], VOIDmode)
- && register_operand (operands[1], VOIDmode)))"
- "#")
-
-(define_split
- [(set (match_operand:DF 0 "memory_operand" "")
- (abs:DF (match_operand:DF 1 "memory_operand" "")))
- (use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- ""
- [(parallel [(set (match_dup 0)
- (abs:DF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
-
-(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (abs:DF (match_operand:DF 1 "register_operand" "")))
- (use (match_operand:V2DF 2 "" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && !SSE_REG_P (operands[0])"
- [(parallel [(set (match_dup 0)
- (abs:DF (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])])
-
-(define_split
- [(set (match_operand:DF 0 "register_operand" "")
- (abs:DF (match_operand:DF 1 "register_operand" "")))
- (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed && SSE_REG_P (operands[0])"
- [(set (match_dup 0)
- (and:V2DF (match_dup 1)
- (match_dup 2)))]
-{
- operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
- operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
- /* Avoid possible reformatting on the operands. */
- if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
- emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
- if (operands_match_p (operands[0], operands[2]))
- {
- rtx tmp;
- tmp = operands[1];
- operands[1] = operands[2];
- operands[2] = tmp;
- }
-})
-
-
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*absdf2_if"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
- (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_80387
- && ix86_unary_operator_ok (ABS, DFmode, operands)"
- "#")
-
-;; FIXME: We should to allow integer registers here. Problem is that
-;; we need another scratch register to get constant from.
-;; Forcing constant to mem if no register available in peep2 should be
-;; safe even for PIC mode, because of RIP relative addressing.
-(define_insn "*absdf2_if_rex64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
- (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && TARGET_80387
- && ix86_unary_operator_ok (ABS, DFmode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:DF 0 "fp_register_operand" "")
- (abs:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (abs:DF (match_dup 1)))]
- "")
-
-(define_split
- [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
- (abs:DF (match_operand:DF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[4] = gen_int_mode (~0x80000000, SImode);
- split_di (operands+0, 1, operands+2, operands+3);")
-
-(define_expand "absxf2"
- [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
- (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))])]
- "TARGET_80387"
- "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
-
-;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
-;; because of secondary memory needed to reload from class FLOAT_INT_REGS
-;; to itself.
-(define_insn "*absxf2_if"
- [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
- (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387
- && ix86_unary_operator_ok (ABS, XFmode, operands)"
- "#")
-
-(define_split
- [(set (match_operand:XF 0 "fp_register_operand" "")
- (abs:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(set (match_dup 0)
- (abs:XF (match_dup 1)))]
- "")
-
-(define_split
- [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
- (abs:XF (match_operand:XF 1 "register_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_80387 && reload_completed"
- [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
- (clobber (reg:CC FLAGS_REG))])]
- "operands[1] = GEN_INT (~0x8000);
- operands[0] = gen_rtx_REG (SImode,
- true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
-
-(define_insn "*abssf2_1"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (abs:SF (match_operand:SF 1 "register_operand" "0")))]
- "TARGET_80387 && reload_completed"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "SF")])
-
-(define_insn "*absdf2_1"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (match_operand:DF 1 "register_operand" "0")))]
- "TARGET_80387 && reload_completed"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "DF")])
-
-(define_insn "*absextendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (abs:DF (float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "DF")])
-
-(define_insn "*absxf2_1"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (match_operand:XF 1 "register_operand" "0")))]
- "TARGET_80387 && reload_completed"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "DF")])
-
-(define_insn "*absextenddfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-
-(define_insn "*absextendsfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (abs:XF (float_extend:XF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "fabs"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-\f
-;; One complement instructions
-
-(define_expand "one_cmpldi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
-
-(define_insn "*one_cmpldi2_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
- "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
- "not{q}\t%0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "DI")])
-
-(define_insn "*one_cmpldi2_2_rex64"
- [(set (reg FLAGS_REG)
- (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (not:DI (match_dup 1)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, DImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "DI")])
+(define_insn "*one_cmpldi2_2_rex64"
+ [(set (reg FLAGS_REG)
+ (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
+ (not:DI (match_dup 1)))]
+ "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
+ && ix86_unary_operator_ok (NOT, DImode, operands)"
+ "#"
+ [(set_attr "type" "alu1")
+ (set_attr "mode" "DI")])
(define_split
[(set (match_operand 0 "flags_reg_operand" "")
(define_insn "*ashldi3_1_rex64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
+ (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
(match_operand:QI 2 "nonmemory_operand" "cJ,M")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
;; Convert lea to the lea pattern to avoid flags dependency.
(define_split
[(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "register_operand" "")
+ (ashift:DI (match_operand:DI 1 "index_register_operand" "")
(match_operand:QI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && reload_completed
(define_insn "*ashlsi3_1"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
+ (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
(match_operand:QI 2 "nonmemory_operand" "cI,M")))
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (ASHIFT, SImode, operands)"
(match_operand:QI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))]
"reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
+ && true_regnum (operands[0]) != true_regnum (operands[1])
+ && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
[(const_int 0)]
{
rtx pat;
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[1] = gen_lowpart (Pmode, operands[1]);
+ enum machine_mode mode = GET_MODE (operands[0]);
+
+ if (GET_MODE_SIZE (mode) < 4)
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ if (mode != Pmode)
+ operands[1] = gen_lowpart (Pmode, operands[1]);
operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
+
pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
if (Pmode != SImode)
pat = gen_rtx_SUBREG (SImode, pat, 0);
(define_insn "*ashlsi3_1_zext"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
+ (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
(match_operand:QI 2 "nonmemory_operand" "cI,M"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
[(set (reg FLAGS_REG)
(compare
(ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashift:SI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(ashift:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
(define_insn "*ashlhi3_1_lea"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
+ (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
(match_operand:QI 2 "nonmemory_operand" "cI,M")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
[(set (reg FLAGS_REG)
(compare
(ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashift:HI (match_dup 1) (match_dup 2)))]
(define_insn "*ashlqi3_1_lea"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
+ (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
(match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_PARTIAL_REG_STALL
[(set (reg FLAGS_REG)
(compare
(ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashift:QI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
[(set (reg FLAGS_REG)
(compare
(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(ashiftrt:QI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r")
(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_dup 1) (match_dup 2)))]
[(set (reg FLAGS_REG)
(compare
(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_1_31_operand" "I"))
+ (match_operand:QI 2 "const_1_to_31_operand" "I"))
(const_int 0)))
(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(lshiftrt:QI (match_dup 1) (match_dup 2)))]
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so check it again here. */
- if (! register_operand (operands[1], VOIDmode))
+ if (! ext_register_operand (operands[1], VOIDmode))
FAIL;
})
/* From mips.md: extract_bit_field doesn't verify that our source
matches the predicate, so check it again here. */
- if (! register_operand (operands[1], VOIDmode))
+ if (! ext_register_operand (operands[1], VOIDmode))
FAIL;
})
/* From mips.md: insert_bit_field doesn't verify that our source
matches the predicate, so check it again here. */
- if (! register_operand (operands[0], VOIDmode))
+ if (! ext_register_operand (operands[0], VOIDmode))
FAIL;
if (TARGET_64BIT)
})
;; %%% bts, btr, btc, bt.
-\f
-;; Store-flag instructions.
+;; In general these instructions are *slow* when applied to memory,
+;; since they enforce atomic operation. When applied to registers,
+;; it depends on the cpu implementation. They're never faster than
+;; the corresponding and/ior/xor operations, so with 32-bit there's
+;; no point. But in 64-bit, we can't hold the relevant immediates
+;; within the instruction itself, so operating on bits in the high
+;; 32-bits of a register becomes easier.
+;;
+;; These are slow on Nocona, but fast on Athlon64. We do require the use
+;; of btrq and btcq for corner cases of post-reload expansion of absdf and
+;; negdf respectively, so they can never be disabled entirely.
+
+(define_insn "*btsq"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (const_int 1))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
+ "bts{q} %1,%0"
+ [(set_attr "type" "alu1")])
+
+(define_insn "*btrq"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (const_int 0))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
+ "btr{q} %1,%0"
+ [(set_attr "type" "alu1")])
-;; For all sCOND expanders, also expand the compare or test insn that
-;; generates cc0. Generate an equality comparison if `seq' or `sne'.
+(define_insn "*btcq"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
+ "btc{q} %1,%0"
+ [(set_attr "type" "alu1")])
-;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
-;; to avoid partial register stalls. Otherwise do things the setcc+movzx
-;; way, which can later delete the movzx if only QImode is needed.
+;; Allow Nocona to avoid these instructions if a register is available.
-(define_expand "seq"
- [(set (match_operand:QI 0 "register_operand" "")
- (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
+(define_peephole2
+ [(match_scratch:DI 2 "r")
+ (parallel [(set (zero_extract:DI
+ (match_operand:DI 0 "register_operand" "")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (const_int 1))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT && !TARGET_USE_BT"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
+ rtx op1;
-(define_expand "sne"
- [(set (match_operand:QI 0 "register_operand" "")
- (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
+ if (HOST_BITS_PER_WIDE_INT >= 64)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else if (i < HOST_BITS_PER_WIDE_INT)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else
+ lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
-(define_expand "sgt"
- [(set (match_operand:QI 0 "register_operand" "")
- (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
+ op1 = immed_double_const (lo, hi, DImode);
+ if (i >= 31)
+ {
+ emit_move_insn (operands[2], op1);
+ op1 = operands[2];
+ }
-(define_expand "sgtu"
- [(set (match_operand:QI 0 "register_operand" "")
- (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
+ emit_insn (gen_iordi3 (operands[0], operands[0], op1));
+ DONE;
+})
-(define_expand "slt"
- [(set (match_operand:QI 0 "register_operand" "")
- (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
- ""
- "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
+(define_peephole2
+ [(match_scratch:DI 2 "r")
+ (parallel [(set (zero_extract:DI
+ (match_operand:DI 0 "register_operand" "")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (const_int 0))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT && !TARGET_USE_BT"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
+ rtx op1;
+
+ if (HOST_BITS_PER_WIDE_INT >= 64)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else if (i < HOST_BITS_PER_WIDE_INT)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else
+ lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
+
+ op1 = immed_double_const (~lo, ~hi, DImode);
+ if (i >= 32)
+ {
+ emit_move_insn (operands[2], op1);
+ op1 = operands[2];
+ }
+
+ emit_insn (gen_anddi3 (operands[0], operands[0], op1));
+ DONE;
+})
+
+(define_peephole2
+ [(match_scratch:DI 2 "r")
+ (parallel [(set (zero_extract:DI
+ (match_operand:DI 0 "register_operand" "")
+ (const_int 1)
+ (match_operand:DI 1 "const_0_to_63_operand" ""))
+ (not:DI (zero_extract:DI
+ (match_dup 0) (const_int 1) (match_dup 1))))
+ (clobber (reg:CC FLAGS_REG))])]
+ "TARGET_64BIT && !TARGET_USE_BT"
+ [(const_int 0)]
+{
+ HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
+ rtx op1;
+
+ if (HOST_BITS_PER_WIDE_INT >= 64)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else if (i < HOST_BITS_PER_WIDE_INT)
+ lo = (HOST_WIDE_INT)1 << i, hi = 0;
+ else
+ lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
+
+ op1 = immed_double_const (lo, hi, DImode);
+ if (i >= 31)
+ {
+ emit_move_insn (operands[2], op1);
+ op1 = operands[2];
+ }
+
+ emit_insn (gen_xordi3 (operands[0], operands[0], op1));
+ DONE;
+})
+\f
+;; Store-flag instructions.
+
+;; For all sCOND expanders, also expand the compare or test insn that
+;; generates cc0. Generate an equality comparison if `seq' or `sne'.
+
+;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
+;; to avoid partial register stalls. Otherwise do things the setcc+movzx
+;; way, which can later delete the movzx if only QImode is needed.
+
+(define_expand "seq"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ ""
+ "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
+
+(define_expand "sne"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ ""
+ "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
+
+(define_expand "sgt"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ ""
+ "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
+
+(define_expand "sgtu"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ ""
+ "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
+
+(define_expand "slt"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
+ ""
+ "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
(define_expand "sltu"
[(set (match_operand:QI 0 "register_operand" "")
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
-(define_insn "*fop_sf_comm_nosse"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "%0")
- (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
- "TARGET_80387 && !TARGET_SSE_MATH
- && COMMUTATIVE_ARITH_P (operands[3])
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
- (const_string "fmul")
- (const_string "fop")))
- (set_attr "mode" "SF")])
-(define_insn "*fop_sf_comm"
+(define_insn "*fop_sf_comm_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "%0,0")
(match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
- "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+ "TARGET_MIX_SSE_I387
&& COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "%0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3])
+ "TARGET_SSE_MATH
+ && COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(const_string "sseadd")))
(set_attr "mode" "SF")])
-(define_insn "*fop_df_comm_nosse"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+(define_insn "*fop_sf_comm_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "%0")
+ (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387
&& COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop")))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_comm"
- [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
- (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
- "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
- && COMMUTATIVE_ARITH_P (operands[3])
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (eq_attr "alternative" "1")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
- (const_string "ssemul")
- (const_string "sseadd"))
- (if_then_else (match_operand:SF 3 "mult_operator" "")
- (const_string "fmul")
- (const_string "fop"))))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_df_comm_sse"
- [(set (match_operand:DF 0 "register_operand" "=Y")
- (match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "%0")
- (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
- "TARGET_SSE2 && TARGET_SSE_MATH
- && COMMUTATIVE_ARITH_P (operands[3])
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (match_operand:SF 3 "mult_operator" "")
- (const_string "ssemul")
- (const_string "sseadd")))
- (set_attr "mode" "DF")])
-
-(define_insn "*fop_xf_comm"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (match_operator:XF 3 "binary_fp_operator"
- [(match_operand:XF 1 "register_operand" "%0")
- (match_operand:XF 2 "register_operand" "f")]))]
- "TARGET_80387
- && COMMUTATIVE_ARITH_P (operands[3])"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (if_then_else (match_operand:XF 3 "mult_operator" "")
- (const_string "fmul")
- (const_string "fop")))
- (set_attr "mode" "XF")])
-
-(define_insn "*fop_sf_1_nosse"
- [(set (match_operand:SF 0 "register_operand" "=f,f")
- (match_operator:SF 3 "binary_fp_operator"
- [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
- (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
- "TARGET_80387 && !TARGET_SSE_MATH
- && !COMMUTATIVE_ARITH_P (operands[3])
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "* return output_387_binary_op (insn, operands);"
- [(set (attr "type")
- (cond [(match_operand:SF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:SF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_sf_1"
+(define_insn "*fop_sf_1_mixed"
[(set (match_operand:SF 0 "register_operand" "=f,f,x")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
- "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+ "TARGET_MIX_SSE_I387
&& !COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
(const_string "sseadd")))
(set_attr "mode" "SF")])
+;; This pattern is not fully shadowed by the pattern above.
+(define_insn "*fop_sf_1_i387"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && !COMMUTATIVE_ARITH_P (operands[3])
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:SF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "SF")])
+
+
;; ??? Add SSE splitters for these!
-(define_insn "*fop_sf_2"
+(define_insn "*fop_sf_2_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_fp_operator"
[(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_sf_3"
+(define_insn "*fop_sf_3_i387"
[(set (match_operand:SF 0 "register_operand" "=f,f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0,0")
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_df_1_nosse"
- [(set (match_operand:DF 0 "register_operand" "=f,f")
+(define_insn "*fop_df_comm_mixed"
+ [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
- [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
- (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
- && !COMMUTATIVE_ARITH_P (operands[3])
+ [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
+ "TARGET_SSE2 && TARGET_MIX_SSE_I387
+ && COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
- (cond [(match_operand:DF 3 "mult_operator" "")
- (const_string "fmul")
- (match_operand:DF 3 "div_operator" "")
- (const_string "fdiv")
- ]
- (const_string "fop")))
+ (if_then_else (eq_attr "alternative" "1")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "ssemul")
+ (const_string "sseadd"))
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop"))))
+ (set_attr "mode" "DF")])
+
+(define_insn "*fop_df_comm_sse"
+ [(set (match_operand:DF 0 "register_operand" "=Y")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "%0")
+ (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
+ "TARGET_SSE2 && TARGET_SSE_MATH
+ && COMMUTATIVE_ARITH_P (operands[3])
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "ssemul")
+ (const_string "sseadd")))
(set_attr "mode" "DF")])
+(define_insn "*fop_df_comm_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "%0")
+ (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387
+ && COMMUTATIVE_ARITH_P (operands[3])
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
-(define_insn "*fop_df_1"
+(define_insn "*fop_df_1_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
- "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+ "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& !COMMUTATIVE_ARITH_P (operands[3])
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
]
(const_string "sseadd")))])
+;; This pattern is not fully shadowed by the pattern above.
+(define_insn "*fop_df_1_i387"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
+ && !COMMUTATIVE_ARITH_P (operands[3])
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:DF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:DF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
+
;; ??? Add SSE splitters for these!
-(define_insn "*fop_df_2"
+(define_insn "*fop_df_2_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_df_3"
+(define_insn "*fop_df_3_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,0")
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_df_4"
+(define_insn "*fop_df_4_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
(match_operand:DF 2 "register_operand" "0,f")]))]
- "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_df_5"
+(define_insn "*fop_df_5_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,f")
(const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_df_6"
+(define_insn "*fop_df_6_i387"
[(set (match_operand:DF 0 "register_operand" "=f,f")
(match_operator:DF 3 "binary_fp_operator"
[(float_extend:DF
(const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_xf_1"
+(define_insn "*fop_xf_comm_i387"
+ [(set (match_operand:XF 0 "register_operand" "=f")
+ (match_operator:XF 3 "binary_fp_operator"
+ [(match_operand:XF 1 "register_operand" "%0")
+ (match_operand:XF 2 "register_operand" "f")]))]
+ "TARGET_80387
+ && COMMUTATIVE_ARITH_P (operands[3])"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:XF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "XF")])
+
+(define_insn "*fop_xf_1_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,f")
(const_string "fop")))
(set_attr "mode" "XF")])
-(define_insn "*fop_xf_2"
+(define_insn "*fop_xf_2_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_xf_3"
+(define_insn "*fop_xf_3_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,0")
(set_attr "fp_int_src" "true")
(set_attr "mode" "SI")])
-(define_insn "*fop_xf_4"
+(define_insn "*fop_xf_4_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
(const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_xf_5"
+(define_insn "*fop_xf_5_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(match_operand:XF 1 "register_operand" "0,f")
(const_string "fop")))
(set_attr "mode" "SF")])
-(define_insn "*fop_xf_6"
+(define_insn "*fop_xf_6_i387"
[(set (match_operand:XF 0 "register_operand" "=f,f")
(match_operator:XF 3 "binary_fp_operator"
[(float_extend:XF
operands[1] = force_reg (SFmode, operands[1]);
})
-(define_insn "sqrtsf2_1"
+(define_insn "*sqrtsf2_mixed"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
- "TARGET_USE_FANCY_MATH_387
- && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
+ "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
"@
fsqrt
sqrtss\t{%1, %0|%0, %1}"
(set_attr "mode" "SF,SF")
(set_attr "athlon_decode" "direct,*")])
-(define_insn "sqrtsf2_1_sse_only"
+(define_insn "*sqrtsf2_sse"
[(set (match_operand:SF 0 "register_operand" "=x")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+ "TARGET_SSE_MATH"
"sqrtss\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "athlon_decode" "*")])
-(define_insn "sqrtsf2_i387"
+(define_insn "*sqrtsf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
- "TARGET_USE_FANCY_MATH_387
- && !TARGET_SSE_MATH"
+ "TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
- "TARGET_USE_FANCY_MATH_387
- || (TARGET_SSE2 && TARGET_SSE_MATH)"
+ "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
- if (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ if (!(TARGET_SSE2 && TARGET_SSE_MATH))
operands[1] = force_reg (DFmode, operands[1]);
})
-(define_insn "sqrtdf2_1"
+(define_insn "*sqrtdf2_mixed"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
- "TARGET_USE_FANCY_MATH_387
- && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
+ "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
"@
fsqrt
sqrtsd\t{%1, %0|%0, %1}"
(set_attr "mode" "DF,DF")
(set_attr "athlon_decode" "direct,*")])
-(define_insn "sqrtdf2_1_sse_only"
+(define_insn "*sqrtdf2_sse"
[(set (match_operand:DF 0 "register_operand" "=Y")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
- "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+ "TARGET_SSE2 && TARGET_SSE_MATH"
"sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "*")])
-(define_insn "sqrtdf2_i387"
+(define_insn "*sqrtdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
- "TARGET_USE_FANCY_MATH_387
- && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
+ "TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
(set_attr "athlon_decode" "direct")])
-(define_insn "*sqrtextendsfdf2"
+(define_insn "*sqrtextendsfdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
"TARGET_USE_FANCY_MATH_387
- && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+ && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
-(define_insn "*sqrtextenddfxf2"
+(define_insn "*sqrtextendsfxf2_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
+ (match_operand:SF 1 "register_operand" "0"))))]
"TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
(set_attr "athlon_decode" "direct")])
-(define_insn "*sqrtextendsfxf2"
+(define_insn "*sqrtextenddfxf2_i387"
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
- (match_operand:SF 1 "register_operand" "0"))))]
+ (match_operand:DF 1 "register_operand" "0"))))]
"TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
- emit_insn (gen_truncxfsf2_noop (operands[0], op1));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
DONE;
})
emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
- emit_insn (gen_truncxfdf2_noop (operands[0], op1));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
DONE;
})
emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
- emit_insn (gen_truncxfsf2_noop (operands[0], op1));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
DONE;
})
emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
ix86_emit_fp_unordered_jump (label);
- emit_insn (gen_truncxfdf2_noop (operands[0], op1));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
DONE;
})
(set_attr "mode" "XF")])
(define_expand "log1psf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:SF 0 "register_operand" ""))
+ (use (match_operand:SF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
emit_insn (gen_extendsfxf2 (op1, operands[1]));
ix86_emit_i387_log1p (op0, op1);
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
(define_expand "log1pdf2"
- [(use (match_operand:XF 0 "register_operand" ""))
- (use (match_operand:XF 1 "register_operand" ""))]
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "register_operand" ""))]
"TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
emit_insn (gen_extenddfxf2 (op1, operands[1]));
ix86_emit_i387_log1p (op0, op1);
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extenddfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2 (op0, op1));
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extendsfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2 (op0, op1));
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extenddfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extendsfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_floor (op0, op1, op2, op3));
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extenddfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extendsfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_ceil (op0, op1, op2, op3));
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extenddfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extendsfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_trunc (op0, op1, op2, op3));
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extenddfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
- emit_insn (gen_truncxfdf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
DONE;
})
emit_insn (gen_extendsfxf2 (op1, operands[1]));
emit_insn (gen_frndintxf2_mask_pm (op0, op1, op2, op3));
- emit_insn (gen_truncxfsf2_noop (operands[0], op0));
+ emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
DONE;
})
(clobber (match_operand 6 "" ""))
(clobber (reg:CC FLAGS_REG))]
"!SSE_REG_P (operands[0]) && reload_completed
- && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
+ && (GET_MODE (operands[0]) == SFmode
+ || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))"
[(const_int 0)]
{
ix86_compare_op0 = operands[5];
;; or op2, op0 - get the nonzero one into the result.
(define_split
[(set (match_operand:SF 0 "register_operand" "")
- (if_then_else (match_operator:SF 1 "sse_comparison_operator"
- [(match_operand:SF 4 "register_operand" "")
- (match_operand:SF 5 "nonimmediate_operand" "")])
- (match_operand:SF 2 "register_operand" "")
- (match_operand:SF 3 "register_operand" "")))
+ (if_then_else:SF (match_operator:SF 1 "sse_comparison_operator"
+ [(match_operand:SF 4 "register_operand" "")
+ (match_operand:SF 5 "nonimmediate_operand" "")])
+ (match_operand:SF 2 "register_operand" "")
+ (match_operand:SF 3 "register_operand" "")))
(clobber (match_operand 6 "" ""))
(clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed"
(define_split
[(set (match_operand:DF 0 "register_operand" "")
- (if_then_else (match_operator:DF 1 "sse_comparison_operator"
- [(match_operand:DF 4 "register_operand" "")
- (match_operand:DF 5 "nonimmediate_operand" "")])
- (match_operand:DF 2 "register_operand" "")
- (match_operand:DF 3 "register_operand" "")))
+ (if_then_else:DF (match_operator:DF 1 "sse_comparison_operator"
+ [(match_operand:DF 4 "register_operand" "")
+ (match_operand:DF 5 "nonimmediate_operand" "")])
+ (match_operand:DF 2 "register_operand" "")
+ (match_operand:DF 3 "register_operand" "")))
(clobber (match_operand 6 "" ""))
(clobber (reg:CC FLAGS_REG))]
"SSE_REG_P (operands[0]) && reload_completed"
(set (match_dup 0) (ior:V2DF (match_dup 6)
(match_dup 7)))]
{
- if (GET_MODE (operands[2]) == DFmode
- && TARGET_SSE_PARTIAL_REGS && !optimize_size)
+ if (TARGET_SSE_SPLIT_REGS && !optimize_size)
{
rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
emit_insn (gen_sse2_unpcklpd (op, op, op));
(define_split
[(set (match_operand:SF 0 "register_operand" "")
- (if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:SF 4 "nonimmediate_operand" "")
- (match_operand:SF 5 "nonimmediate_operand" "")])
- (match_operand:SF 2 "nonmemory_operand" "")
- (match_operand:SF 3 "nonmemory_operand" "")))]
+ (if_then_else:SF (match_operator 1 "comparison_operator"
+ [(match_operand:SF 4 "nonimmediate_operand" "")
+ (match_operand:SF 5 "nonimmediate_operand" "")])
+ (match_operand:SF 2 "nonmemory_operand" "")
+ (match_operand:SF 3 "nonmemory_operand" "")))]
"SSE_REG_P (operands[0]) && reload_completed
&& (const0_operand (operands[2], GET_MODE (operands[0]))
|| const0_operand (operands[3], GET_MODE (operands[0])))"
(define_split
[(set (match_operand:DF 0 "register_operand" "")
- (if_then_else (match_operator 1 "comparison_operator"
- [(match_operand:DF 4 "nonimmediate_operand" "")
- (match_operand:DF 5 "nonimmediate_operand" "")])
- (match_operand:DF 2 "nonmemory_operand" "")
- (match_operand:DF 3 "nonmemory_operand" "")))]
+ (if_then_else:DF (match_operator 1 "comparison_operator"
+ [(match_operand:DF 4 "nonimmediate_operand" "")
+ (match_operand:DF 5 "nonimmediate_operand" "")])
+ (match_operand:DF 2 "nonmemory_operand" "")
+ (match_operand:DF 3 "nonmemory_operand" "")))]
"SSE_REG_P (operands[0]) && reload_completed
&& (const0_operand (operands[2], GET_MODE (operands[0]))
|| const0_operand (operands[3], GET_MODE (operands[0])))"
[(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
(set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
{
- if (TARGET_SSE_PARTIAL_REGS && !optimize_size
- && GET_MODE (operands[2]) == DFmode)
+ if (TARGET_SSE_SPLIT_REGS && !optimize_size)
{
if (REG_P (operands[2]))
{
RET;
})
- ;; Pentium III SIMD instructions.
-
-;; Moves for SSE/MMX regs.
-
-(define_insn "movv4sf_internal"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE"
- "@
- xorps\t%0, %0
- movaps\t{%1, %0|%0, %1}
- movaps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V4SF")])
-
-(define_split
- [(set (match_operand:V4SF 0 "register_operand" "")
- (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
- "TARGET_SSE"
- [(set (match_dup 0)
- (vec_merge:V4SF
- (vec_duplicate:V4SF (match_dup 1))
- (match_dup 2)
- (const_int 1)))]
-{
- operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
- operands[2] = CONST0_RTX (V4SFmode);
-})
+(define_expand "sse_prologue_save"
+ [(parallel [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(reg:DI 21)
+ (reg:DI 22)
+ (reg:DI 23)
+ (reg:DI 24)
+ (reg:DI 25)
+ (reg:DI 26)
+ (reg:DI 27)
+ (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (use (match_operand:DI 1 "register_operand" ""))
+ (use (match_operand:DI 2 "immediate_operand" ""))
+ (use (label_ref:DI (match_operand 3 "" "")))])]
+ "TARGET_64BIT"
+ "")
-(define_insn "movv4si_internal"
- [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE"
+(define_insn "*sse_prologue_save_insn"
+ [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
+ (match_operand:DI 4 "const_int_operand" "n")))
+ (unspec:BLK [(reg:DI 21)
+ (reg:DI 22)
+ (reg:DI 23)
+ (reg:DI 24)
+ (reg:DI 25)
+ (reg:DI 26)
+ (reg:DI 27)
+ (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+ (use (match_operand:DI 1 "register_operand" "r"))
+ (use (match_operand:DI 2 "const_int_operand" "i"))
+ (use (label_ref:DI (match_operand 3 "" "X")))]
+ "TARGET_64BIT
+ && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
+ && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
+ "*
{
- switch (which_alternative)
+ int i;
+ operands[0] = gen_rtx_MEM (Pmode,
+ gen_rtx_PLUS (Pmode, operands[0], operands[4]));
+ output_asm_insn (\"jmp\\t%A1\", operands);
+ for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
{
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
+ operands[4] = adjust_address (operands[0], DImode, i*16);
+ operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
+ PUT_MODE (operands[4], TImode);
+ if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
+ output_asm_insn (\"rex\", operands);
+ output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
}
+ (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+ CODE_LABEL_NUMBER (operands[3]));
+ RET;
}
- [(set_attr "type" "ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
+ "
+ [(set_attr "type" "other")
+ (set_attr "length_immediate" "0")
+ (set_attr "length_address" "0")
+ (set_attr "length" "135")
+ (set_attr "memory" "store")
+ (set_attr "modrm" "0")
+ (set_attr "mode" "DI")])
-(define_insn "movv2di_internal"
- [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE"
+(define_expand "prefetch"
+ [(prefetch (match_operand 0 "address_operand" "")
+ (match_operand:SI 1 "const_int_operand" "")
+ (match_operand:SI 2 "const_int_operand" ""))]
+ "TARGET_PREFETCH_SSE || TARGET_3DNOW"
{
- switch (which_alternative)
- {
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
+ int rw = INTVAL (operands[1]);
+ int locality = INTVAL (operands[2]);
-(define_split
- [(set (match_operand:V2DF 0 "register_operand" "")
- (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
- "TARGET_SSE2"
- [(set (match_dup 0)
- (vec_merge:V2DF
- (vec_duplicate:V2DF (match_dup 1))
- (match_dup 2)
- (const_int 1)))]
-{
- operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
- operands[2] = CONST0_RTX (V2DFmode);
+ if (rw != 0 && rw != 1)
+ abort ();
+ if (locality < 0 || locality > 3)
+ abort ();
+ if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
+ abort ();
+
+ /* Use 3dNOW prefetch in case we are asking for write prefetch not
+ suported by SSE counterpart or the SSE prefetch is not available
+ (K6 machines). Otherwise use SSE prefetch as it allows specifying
+ of locality. */
+ if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
+ operands[2] = GEN_INT (3);
+ else
+ operands[1] = const0_rtx;
})
-(define_insn "movv8qi_internal"
- [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
- (match_operand:V8QI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
- "TARGET_MMX
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "@
- pxor\t%0, %0
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
- (set_attr "mode" "DI")])
+(define_insn "*prefetch_sse"
+ [(prefetch (match_operand:SI 0 "address_operand" "p")
+ (const_int 0)
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "TARGET_PREFETCH_SSE && !TARGET_64BIT"
+{
+ static const char * const patterns[4] = {
+ "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+ };
-(define_insn "movv4hi_internal"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
- (match_operand:V4HI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
- "TARGET_MMX
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "@
- pxor\t%0, %0
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
- (set_attr "mode" "DI")])
+ int locality = INTVAL (operands[1]);
+ if (locality < 0 || locality > 3)
+ abort ();
-(define_insn "*movv2si_internal"
- [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*Y,?m")
- (match_operand:V2SI 1 "vector_move_operand" "C,ym,y,*Y,y,*Ym,*Y"))]
- "TARGET_MMX
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "@
- pxor\t%0, %0
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
- (set_attr "mode" "DI")])
+ return patterns[locality];
+}
+ [(set_attr "type" "sse")
+ (set_attr "memory" "none")])
-(define_insn "movv2sf_internal"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m,!y,!*Y,?*x,?m")
- (match_operand:V2SF 1 "vector_move_operand" "C,ym,y,*Y,y,*xm,*x"))]
- "TARGET_3DNOW
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "@
- pxor\t%0, %0
- movq\t{%1, %0|%0, %1}
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- movlps\t{%1, %0|%0, %1}
- movlps\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov")
- (set_attr "mode" "DI,DI,DI,DI,DI,V2SF,V2SF")])
+(define_insn "*prefetch_sse_rex"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (const_int 0)
+ (match_operand:SI 1 "const_int_operand" ""))]
+ "TARGET_PREFETCH_SSE && TARGET_64BIT"
+{
+ static const char * const patterns[4] = {
+ "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+ };
-(define_expand "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE || TARGET_64BIT"
+ int locality = INTVAL (operands[1]);
+ if (locality < 0 || locality > 3)
+ abort ();
+
+ return patterns[locality];
+}
+ [(set_attr "type" "sse")
+ (set_attr "memory" "none")])
+
+(define_insn "*prefetch_3dnow"
+ [(prefetch (match_operand:SI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (const_int 3))]
+ "TARGET_3DNOW && !TARGET_64BIT"
{
- if (TARGET_64BIT)
- ix86_expand_move (TImode, operands);
+ if (INTVAL (operands[1]) == 0)
+ return "prefetch\t%a0";
else
- ix86_expand_vector_move (TImode, operands);
- DONE;
-})
+ return "prefetchw\t%a0";
+}
+ [(set_attr "type" "mmx")
+ (set_attr "memory" "none")])
-(define_expand "movtf"
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "nonimmediate_operand" ""))]
- "TARGET_64BIT"
+(define_insn "*prefetch_3dnow_rex"
+ [(prefetch (match_operand:DI 0 "address_operand" "p")
+ (match_operand:SI 1 "const_int_operand" "n")
+ (const_int 3))]
+ "TARGET_3DNOW && TARGET_64BIT"
{
- if (TARGET_64BIT)
- ix86_expand_move (TFmode, operands);
+ if (INTVAL (operands[1]) == 0)
+ return "prefetch\t%a0";
else
- ix86_expand_vector_move (TFmode, operands);
- DONE;
-})
+ return "prefetchw\t%a0";
+}
+ [(set_attr "type" "mmx")
+ (set_attr "memory" "none")])
-(define_insn "movv2df_internal"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "xorpd\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movapd\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "V2DF"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "V2DF"))]
- (const_string "V2DF")))])
-
-(define_insn "movv8hi_internal"
- [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
-
-(define_insn "movv16qi_internal"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
-
-(define_expand "movv2df"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
- (match_operand:V2DF 1 "nonimmediate_operand" ""))]
- "TARGET_SSE2"
-{
- ix86_expand_vector_move (V2DFmode, operands);
- DONE;
-})
-
-(define_expand "movv8hi"
- [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
- (match_operand:V8HI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE2"
-{
- ix86_expand_vector_move (V8HImode, operands);
- DONE;
-})
-
-(define_expand "movv16qi"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
- (match_operand:V16QI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE2"
-{
- ix86_expand_vector_move (V16QImode, operands);
- DONE;
-})
-
-(define_expand "movv4sf"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
- (match_operand:V4SF 1 "nonimmediate_operand" ""))]
- "TARGET_SSE"
-{
- ix86_expand_vector_move (V4SFmode, operands);
- DONE;
-})
-
-(define_expand "movv4si"
- [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
- (match_operand:V4SI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE"
-{
- ix86_expand_vector_move (V4SImode, operands);
- DONE;
-})
-
-(define_expand "movv2di"
- [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
- (match_operand:V2DI 1 "nonimmediate_operand" ""))]
- "TARGET_SSE"
-{
- ix86_expand_vector_move (V2DImode, operands);
- DONE;
-})
-
-(define_expand "movv2si"
- [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
- (match_operand:V2SI 1 "nonimmediate_operand" ""))]
- "TARGET_MMX"
-{
- ix86_expand_vector_move (V2SImode, operands);
- DONE;
-})
-
-(define_expand "movv4hi"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
- (match_operand:V4HI 1 "nonimmediate_operand" ""))]
- "TARGET_MMX"
-{
- ix86_expand_vector_move (V4HImode, operands);
- DONE;
-})
-
-(define_expand "movv8qi"
- [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
- (match_operand:V8QI 1 "nonimmediate_operand" ""))]
- "TARGET_MMX"
-{
- ix86_expand_vector_move (V8QImode, operands);
- DONE;
-})
-
-(define_expand "movv2sf"
- [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
- (match_operand:V2SF 1 "nonimmediate_operand" ""))]
- "TARGET_3DNOW"
-{
- ix86_expand_vector_move (V2SFmode, operands);
- DONE;
-})
-
-(define_insn "*pushti"
- [(set (match_operand:TI 0 "push_operand" "=<")
- (match_operand:TI 1 "register_operand" "x"))]
- "TARGET_SSE"
- "#")
-
-(define_insn "*pushv2df"
- [(set (match_operand:V2DF 0 "push_operand" "=<")
- (match_operand:V2DF 1 "register_operand" "x"))]
- "TARGET_SSE"
- "#")
-
-(define_insn "*pushv2di"
- [(set (match_operand:V2DI 0 "push_operand" "=<")
- (match_operand:V2DI 1 "register_operand" "x"))]
- "TARGET_SSE2"
- "#")
-
-(define_insn "*pushv8hi"
- [(set (match_operand:V8HI 0 "push_operand" "=<")
- (match_operand:V8HI 1 "register_operand" "x"))]
- "TARGET_SSE2"
- "#")
-
-(define_insn "*pushv16qi"
- [(set (match_operand:V16QI 0 "push_operand" "=<")
- (match_operand:V16QI 1 "register_operand" "x"))]
- "TARGET_SSE2"
- "#")
-
-(define_insn "*pushv4sf"
- [(set (match_operand:V4SF 0 "push_operand" "=<")
- (match_operand:V4SF 1 "register_operand" "x"))]
- "TARGET_SSE"
- "#")
-
-(define_insn "*pushv4si"
- [(set (match_operand:V4SI 0 "push_operand" "=<")
- (match_operand:V4SI 1 "register_operand" "x"))]
- "TARGET_SSE2"
- "#")
-
-(define_insn "*pushv2si"
- [(set (match_operand:V2SI 0 "push_operand" "=<")
- (match_operand:V2SI 1 "register_operand" "y"))]
- "TARGET_MMX"
- "#")
-
-(define_insn "*pushv4hi"
- [(set (match_operand:V4HI 0 "push_operand" "=<")
- (match_operand:V4HI 1 "register_operand" "y"))]
- "TARGET_MMX"
- "#")
-
-(define_insn "*pushv8qi"
- [(set (match_operand:V8QI 0 "push_operand" "=<")
- (match_operand:V8QI 1 "register_operand" "y"))]
- "TARGET_MMX"
- "#")
-
-(define_insn "*pushv2sf"
- [(set (match_operand:V2SF 0 "push_operand" "=<")
- (match_operand:V2SF 1 "register_operand" "y"))]
- "TARGET_3DNOW"
- "#")
-
-(define_split
- [(set (match_operand 0 "push_operand" "")
- (match_operand 1 "register_operand" ""))]
- "!TARGET_64BIT && reload_completed
- && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
- [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 3)))
- (set (match_dup 2) (match_dup 1))]
- "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
- stack_pointer_rtx);
- operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
-
-(define_split
- [(set (match_operand 0 "push_operand" "")
- (match_operand 1 "register_operand" ""))]
- "TARGET_64BIT && reload_completed
- && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
- [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 3)))
- (set (match_dup 2) (match_dup 1))]
- "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
- stack_pointer_rtx);
- operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
-
-
-(define_insn "movti_internal"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
- (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
- "TARGET_SSE && !TARGET_64BIT
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 1:
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "ssemov,ssemov,ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "0,1")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "2")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "TI")))])
-
-(define_insn "*movti_rex64"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
- (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
- "TARGET_64BIT
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- case 1:
- return "#";
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 3:
- case 4:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "2,3")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "4")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
-
-(define_insn "*movtf_rex64"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
- (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
- "TARGET_64BIT
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
-{
- switch (which_alternative)
- {
- case 0:
- case 1:
- return "#";
- case 2:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "xorps\t%0, %0";
- else
- return "pxor\t%0, %0";
- case 3:
- case 4:
- if (get_attr_mode (insn) == MODE_V4SF)
- return "movaps\t{%1, %0|%0, %1}";
- else
- return "movdqa\t{%1, %0|%0, %1}";
- default:
- abort ();
- }
-}
- [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
- (set (attr "mode")
- (cond [(eq_attr "alternative" "2,3")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI"))
- (eq_attr "alternative" "4")
- (if_then_else
- (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
- (const_int 0))
- (ne (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "V4SF")
- (const_string "TI"))]
- (const_string "DI")))])
-
-(define_split
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
- "reload_completed && !SSE_REG_P (operands[0])
- && !SSE_REG_P (operands[1])"
- [(const_int 0)]
- "ix86_split_long_move (operands); DONE;")
-
-(define_split
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "general_operand" ""))]
- "reload_completed && !SSE_REG_P (operands[0])
- && !SSE_REG_P (operands[1])"
- [(const_int 0)]
- "ix86_split_long_move (operands); DONE;")
-
-;; These two patterns are useful for specifying exactly whether to use
-;; movaps or movups
-(define_expand "sse_movaps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
- UNSPEC_MOVA))]
- "TARGET_SSE"
-{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
- {
- rtx tmp = gen_reg_rtx (V4SFmode);
- emit_insn (gen_sse_movaps (tmp, operands[1]));
- emit_move_insn (operands[0], tmp);
- DONE;
- }
-})
-
-(define_insn "*sse_movaps_1"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVA))]
- "TARGET_SSE
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movaps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov,ssemov")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_movups"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
- UNSPEC_MOVU))]
- "TARGET_SSE"
-{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
- {
- rtx tmp = gen_reg_rtx (V4SFmode);
- emit_insn (gen_sse_movups (tmp, operands[1]));
- emit_move_insn (operands[0], tmp);
- DONE;
- }
-})
-
-(define_insn "*sse_movups_1"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
- "TARGET_SSE
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movups\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt,ssecvt")
- (set_attr "mode" "V4SF")])
-
-;; SSE Strange Moves.
-
-(define_insn "sse_movmskps"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
- "TARGET_SSE"
- "movmskps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "mmx_pmovmskb"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
- UNSPEC_MOVMSK))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pmovmskb\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-
-(define_insn "mmx_maskmovq"
- [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
- (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
- UNSPEC_MASKMOV))]
- "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
- ;; @@@ check ordering of operands in intel/nonintel syntax
- "maskmovq\t{%2, %1|%1, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_maskmovq_rex"
- [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
- (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
- (match_operand:V8QI 2 "register_operand" "y")]
- UNSPEC_MASKMOV))]
- "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
- ;; @@@ check ordering of operands in intel/nonintel syntax
- "maskmovq\t{%2, %1|%1, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "sse_movntv4sf"
- [(set (match_operand:V4SF 0 "memory_operand" "=m")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "TARGET_SSE"
- "movntps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse_movntdi"
- [(set (match_operand:DI 0 "memory_operand" "=m")
- (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
- UNSPEC_MOVNT))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "movntq\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxmov")
- (set_attr "mode" "DI")])
-
-(define_insn "sse_movhlps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0")
- (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
- (parallel [(const_int 2)
- (const_int 3)
- (const_int 0)
- (const_int 1)]))
- (const_int 3)))]
- "TARGET_SSE"
- "movhlps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse_movlhps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0")
- (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
- (parallel [(const_int 2)
- (const_int 3)
- (const_int 0)
- (const_int 1)]))
- (const_int 12)))]
- "TARGET_SSE"
- "movlhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse_movhps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
- (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
- (const_int 12)))]
- "TARGET_SSE
- && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
- "movhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse_movlps"
- [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
- (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
- (const_int 3)))]
- "TARGET_SSE
- && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
- "movlps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_loadss"
- [(match_operand:V4SF 0 "register_operand" "")
- (match_operand:SF 1 "memory_operand" "")]
- "TARGET_SSE"
-{
- emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
- CONST0_RTX (V4SFmode)));
- DONE;
-})
-
-(define_insn "sse_loadss_1"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
- (match_operand:V4SF 2 "const0_operand" "X")
- (const_int 1)))]
- "TARGET_SSE"
- "movss\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_movss"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "register_operand" "x")
- (const_int 14)))]
- "TARGET_SSE"
- "movss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_storess"
- [(set (match_operand:SF 0 "memory_operand" "=m")
- (vec_select:SF
- (match_operand:V4SF 1 "register_operand" "x")
- (parallel [(const_int 0)])))]
- "TARGET_SSE"
- "movss\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_shufps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "immediate_operand" "i")]
- UNSPEC_SHUFFLE))]
- "TARGET_SSE"
- ;; @@@ check operand order for intel/nonintel syntax
- "shufps\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-
-;; SSE arithmetic
-
-(define_insn "addv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "addps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmaddv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "addss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-(define_insn "subv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "subps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmsubv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "subss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "SF")])
-
-;; ??? Should probably be done by generic code instead.
-(define_expand "negv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
- (match_dup 2)))]
- "TARGET_SSE"
-{
- rtx m0 = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
- rtx vm0 = gen_rtx_CONST_VECTOR (V4SFmode, gen_rtvec (4, m0, m0, m0, m0));
- operands[2] = force_reg (V4SFmode, vm0);
-})
-
-(define_insn "mulv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "mulps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmmulv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "mulss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "mode" "SF")])
-
-(define_insn "divv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "divps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmdivv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "divss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "mode" "SF")])
-
-
-;; SSE square root/reciprocal
-
-(define_insn "rcpv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
- "TARGET_SSE"
- "rcpps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmrcpv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_RCP)
- (match_operand:V4SF 2 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE"
- "rcpss\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-(define_insn "rsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
- "TARGET_SSE"
- "rsqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmrsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_RSQRT)
- (match_operand:V4SF 2 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE"
- "rsqrtss\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-(define_insn "sqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "sqrtps\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmsqrtv4sf2"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
- (match_operand:V4SF 2 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE"
- "sqrtss\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-;; SSE logical operations.
-
-;; SSE defines logical operations on floating point values. This brings
-;; interesting challenge to RTL representation where logicals are only valid
-;; on integral types. We deal with this by representing the floating point
-;; logical as logical on arguments casted to TImode as this is what hardware
-;; really does. Unfortunately hardware requires the type information to be
-;; present and thus we must avoid subregs from being simplified and eliminated
-;; in later compilation phases.
-;;
-;; We have following variants from each instruction:
-;; sse_andsf3 - the operation taking V4SF vector operands
-;; and doing TImode cast on them
-;; *sse_andsf3_memory - the operation taking one memory operand casted to
-;; TImode, since backend insist on eliminating casts
-;; on memory operands
-;; sse_andti3_sf_1 - the operation taking SF scalar operands.
-;; We cannot accept memory operand here as instruction reads
-;; whole scalar. This is generated only post reload by GCC
-;; scalar float operations that expands to logicals (fabs)
-;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
-;; memory operand. Eventually combine can be able
-;; to synthesize these using splitter.
-;; sse2_anddf3, *sse2_anddf3_memory
-;;
-;;
-;; These are not called andti3 etc. because we really really don't want
-;; the compiler to widen DImode ands to TImode ands and then try to move
-;; into DImode subregs of SSE registers, and them together, and move out
-;; of DImode subregs again!
-;; SSE1 single precision floating point logical operation
-(define_expand "sse_andv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (and:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "")
-
-(define_insn "*sse_andv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "andps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_nandv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" ""))
- (match_operand:V4SF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "")
-
-(define_insn "*sse_nandv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "andnps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_iorv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (ior:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "")
-
-(define_insn "*sse_iorv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "orps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-(define_expand "sse_xorv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "")
- (xor:V4SF (match_operand:V4SF 1 "register_operand" "")
- (match_operand:V4SF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE"
- "")
-
-(define_insn "*sse_xorv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "xorps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V4SF")])
-
-;; SSE2 double precision floating point logical operation
-
-(define_expand "sse2_andv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "")
- (and:V2DF (match_operand:V2DF 1 "register_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "")
-
-(define_insn "*sse2_andv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "andpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V2DF")])
-
-(define_expand "sse2_nandv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "")
- (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" ""))
- (match_operand:V2DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "")
-
-(define_insn "*sse2_nandv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "andnpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V2DF")])
-
-(define_expand "sse2_iorv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "")
- (ior:V2DF (match_operand:V2DF 1 "register_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "")
-
-(define_insn "*sse2_iorv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "orpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V2DF")])
-
-(define_expand "sse2_xorv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "")
- (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
- (match_operand:V2DF 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2"
- "")
-
-(define_insn "*sse2_xorv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "xorpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "V2DF")])
-
-;; SSE2 integral logicals. These patterns must always come after floating
-;; point ones since we don't want compiler to use integer opcodes on floating
-;; point SSE values to avoid matching of subregs in the match_operand.
-(define_insn "*sse2_andti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
- (match_operand:TI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_andv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse2_nandti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
- (match_operand:TI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_nandv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse2_iorti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
- (match_operand:TI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "por\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_iorv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "por\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "*sse2_xorti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
- (match_operand:TI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "pxor\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_xorv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2
- && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
- "pxor\t{%2, %0|%0, %2}"
- [(set_attr "type" "sselog")
- (set_attr "mode" "TI")])
-
-;; Use xor, but don't show input operands so they aren't live before
-;; this insn.
-(define_insn "sse_clrv4sf"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (match_operand:V4SF 1 "const0_operand" "X"))]
- "TARGET_SSE"
-{
- if (get_attr_mode (insn) == MODE_TI)
- return "pxor\t{%0, %0|%0, %0}";
- else
- return "xorps\t{%0, %0|%0, %0}";
-}
- [(set_attr "type" "sselog")
- (set_attr "memory" "none")
- (set (attr "mode")
- (if_then_else
- (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
- (const_int 0))
- (ne (symbol_ref "TARGET_SSE2")
- (const_int 0)))
- (eq (symbol_ref "optimize_size")
- (const_int 0)))
- (const_string "TI")
- (const_string "V4SF")))])
-
-;; Use xor, but don't show input operands so they aren't live before
-;; this insn.
-(define_insn "sse_clrv2df"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
- "TARGET_SSE2"
- "xorpd\t{%0, %0|%0, %0}"
- [(set_attr "type" "sselog")
- (set_attr "memory" "none")
- (set_attr "mode" "V4SF")])
-
-;; SSE mask-generating compares
-
-(define_insn "maskcmpv4sf3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (match_operator:V4SI 3 "sse_comparison_operator"
- [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "register_operand" "x")]))]
- "TARGET_SSE"
- "cmp%D3ps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "V4SF")])
-
-(define_insn "maskncmpv4sf3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (not:V4SI
- (match_operator:V4SI 3 "sse_comparison_operator"
- [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "register_operand" "x")])))]
- "TARGET_SSE"
-{
- if (GET_CODE (operands[3]) == UNORDERED)
- return "cmpordps\t{%2, %0|%0, %2}";
- else
- return "cmpn%D3ps\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmmaskcmpv4sf3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (match_operator:V4SI 3 "sse_comparison_operator"
- [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "register_operand" "x")])
- (subreg:V4SI (match_dup 1) 0)
- (const_int 1)))]
- "TARGET_SSE"
- "cmp%D3ss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "SF")])
-
-(define_insn "vmmaskncmpv4sf3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (not:V4SI
- (match_operator:V4SI 3 "sse_comparison_operator"
- [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "register_operand" "x")]))
- (subreg:V4SI (match_dup 1) 0)
- (const_int 1)))]
- "TARGET_SSE"
-{
- if (GET_CODE (operands[3]) == UNORDERED)
- return "cmpordss\t{%2, %0|%0, %2}";
- else
- return "cmpn%D3ss\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_comi"
- [(set (reg:CCFP FLAGS_REG)
- (compare:CCFP (vec_select:SF
- (match_operand:V4SF 0 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SF
- (match_operand:V4SF 1 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE"
- "comiss\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "mode" "SF")])
-
-(define_insn "sse_ucomi"
- [(set (reg:CCFPU FLAGS_REG)
- (compare:CCFPU (vec_select:SF
- (match_operand:V4SF 0 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:SF
- (match_operand:V4SF 1 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE"
- "ucomiss\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "mode" "SF")])
-
-
-;; SSE unpack
-
-(define_insn "sse_unpckhps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (const_int 5)))]
- "TARGET_SSE"
- "unpckhps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse_unpcklps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (const_int 5)))]
- "TARGET_SSE"
- "unpcklps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-
-;; SSE min/max
-
-(define_insn "smaxv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "maxps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmsmaxv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "maxss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-(define_insn "sminv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE"
- "minps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "vmsminv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE"
- "minss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-;; SSE <-> integer/MMX conversions
-
-(define_insn "cvtpi2ps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0")
- (vec_duplicate:V4SF
- (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
- (const_int 12)))]
- "TARGET_SSE"
- "cvtpi2ps\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "cvtps2pi"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
- (parallel [(const_int 0) (const_int 1)])))]
- "TARGET_SSE"
- "cvtps2pi\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "cvttps2pi"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_FIX)
- (parallel [(const_int 0) (const_int 1)])))]
- "TARGET_SSE"
- "cvttps2pi\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "SF")])
-
-(define_insn "cvtsi2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0,0")
- (vec_duplicate:V4SF
- (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
- (const_int 14)))]
- "TARGET_SSE"
- "cvtsi2ss\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "mode" "SF")])
-
-(define_insn "cvtsi2ssq"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
- (vec_merge:V4SF
- (match_operand:V4SF 1 "register_operand" "0,0")
- (vec_duplicate:V4SF
- (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
- (const_int 14)))]
- "TARGET_SSE && TARGET_64BIT"
- "cvtsi2ssq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "mode" "SF")])
-
-(define_insn "cvtss2si"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (vec_select:SI
- (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
- (parallel [(const_int 0)])))]
- "TARGET_SSE"
- "cvtss2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "mode" "SI")])
-
-(define_insn "cvtss2siq"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (vec_select:DI
- (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
- (parallel [(const_int 0)])))]
- "TARGET_SSE"
- "cvtss2siq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "mode" "DI")])
-
-(define_insn "cvttss2si"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (vec_select:SI
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
- UNSPEC_FIX)
- (parallel [(const_int 0)])))]
- "TARGET_SSE"
- "cvttss2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "SF")
- (set_attr "athlon_decode" "double,vector")])
-
-(define_insn "cvttss2siq"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (vec_select:DI
- (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
- UNSPEC_FIX)
- (parallel [(const_int 0)])))]
- "TARGET_SSE && TARGET_64BIT"
- "cvttss2siq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "SF")
- (set_attr "athlon_decode" "double,vector")])
-
-
-;; MMX insns
-
-;; MMX arithmetic
-
-(define_insn "addv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "addv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "addv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_adddi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(plus:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "paddq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "ssaddv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddsb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "ssaddv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "usaddv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddusb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "usaddv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "paddusw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "subv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "subv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "subv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_subdi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(minus:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "psubq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "sssubv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubsb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "sssubv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "ussubv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubusb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "ussubv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "psubusw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "mulv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pmullw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
-
-(define_insn "smulv4hi3_highpart"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (mult:V4SI (sign_extend:V4SI
- (match_operand:V4HI 1 "register_operand" "0"))
- (sign_extend:V4SI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
- (const_int 16))))]
- "TARGET_MMX"
- "pmulhw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
-
-(define_insn "umulv4hi3_highpart"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (mult:V4SI (zero_extend:V4SI
- (match_operand:V4HI 1 "register_operand" "0"))
- (zero_extend:V4SI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
- (const_int 16))))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pmulhuw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_pmaddwd"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (plus:V2SI
- (mult:V2SI
- (sign_extend:V2SI
- (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 0) (const_int 2)])))
- (sign_extend:V2SI
- (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0) (const_int 2)]))))
- (mult:V2SI
- (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)]))))))]
- "TARGET_MMX"
- "pmaddwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
-
-
-;; MMX logical operations
-;; Note we don't want to declare these as regular iordi3 insns to prevent
-;; normal code that also wants to use the FPU from getting broken.
-;; The UNSPECs are there to prevent the combiner from getting overly clever.
-(define_insn "mmx_iordi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(ior:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "por\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_xordi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(xor:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "pxor\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")
- (set_attr "memory" "none")])
-
-;; Same as pxor, but don't show input operands so that we don't think
-;; they are live.
-(define_insn "mmx_clrdi"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(const_int 0)] UNSPEC_NOP))]
- "TARGET_MMX"
- "pxor\t{%0, %0|%0, %0}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")
- (set_attr "memory" "none")])
-
-(define_insn "mmx_anddi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(and:DI (match_operand:DI 1 "register_operand" "%0")
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "pand\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_nanddi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
- (match_operand:DI 2 "nonimmediate_operand" "ym"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "pandn\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-
-;; MMX unsigned averages/sum of absolute differences
-
-(define_insn "mmx_uavgv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (ashiftrt:V8QI
- (plus:V8QI (plus:V8QI
- (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
- (const_vector:V8QI [(const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)]))
- (const_int 1)))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pavgb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_uavgv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ashiftrt:V4HI
- (plus:V4HI (plus:V4HI
- (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
- (const_vector:V4HI [(const_int 1)
- (const_int 1)
- (const_int 1)
- (const_int 1)]))
- (const_int 1)))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pavgw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_psadbw"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
- UNSPEC_PSADBW))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "psadbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-
-;; MMX insert/extract/shuffle
-
-(define_insn "mmx_pinsrw"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (vec_duplicate:V4HI
- (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:SI 3 "const_0_to_15_operand" "N")))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pinsrw\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_pextrw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
- (parallel
- [(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pextrw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_pshufw"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (unspec:V4HI [(match_operand:V4HI 1 "nonimmediate_operand" "ym")
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_SHUFFLE))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pshufw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-
-;; MMX mask-generating comparisons
-
-(define_insn "eqv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpeqb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-(define_insn "eqv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpeqw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-(define_insn "eqv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpeqd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-(define_insn "gtv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpgtb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-(define_insn "gtv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpgtw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-(define_insn "gtv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
- "TARGET_MMX"
- "pcmpgtd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "DI")])
-
-
-;; MMX max/min insns
-
-(define_insn "umaxv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pmaxub\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "smaxv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pmaxsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "uminv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pminub\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-(define_insn "sminv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "pminsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
-
-
-;; MMX shifts
-
-(define_insn "ashrv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "psraw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "ashrv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "psrad\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "lshrv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "psrlw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "lshrv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "psrld\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-;; See logical MMX insns.
-(define_insn "mmx_lshrdi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "psrlq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "ashlv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "psllw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "ashlv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi")))]
- "TARGET_MMX"
- "pslld\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-;; See logical MMX insns.
-(define_insn "mmx_ashldi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (unspec:DI
- [(ashift:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "nonmemory_operand" "yi"))]
- UNSPEC_NOP))]
- "TARGET_MMX"
- "psllq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-
-;; MMX pack/unpack insns.
-
-(define_insn "mmx_packsswb"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
- (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
- "TARGET_MMX"
- "packsswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_packssdw"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_concat:V4HI
- (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
- (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
- "TARGET_MMX"
- "packssdw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_packuswb"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_concat:V8QI
- (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
- (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
- "TARGET_MMX"
- "packuswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpckhbw"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_merge:V8QI
- (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (parallel [(const_int 4)
- (const_int 0)
- (const_int 5)
- (const_int 1)
- (const_int 6)
- (const_int 2)
- (const_int 7)
- (const_int 3)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 1)
- (const_int 5)
- (const_int 2)
- (const_int 6)
- (const_int 3)
- (const_int 7)]))
- (const_int 85)))]
- "TARGET_MMX"
- "punpckhbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpckhwd"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_merge:V4HI
- (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (const_int 5)))]
- "TARGET_MMX"
- "punpckhwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpckhdq"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_merge:V2SI
- (match_operand:V2SI 1 "register_operand" "0")
- (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
- (parallel [(const_int 1)
- (const_int 0)]))
- (const_int 1)))]
- "TARGET_MMX"
- "punpckhdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpcklbw"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (vec_merge:V8QI
- (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 1)
- (const_int 5)
- (const_int 2)
- (const_int 6)
- (const_int 3)
- (const_int 7)]))
- (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
- (parallel [(const_int 4)
- (const_int 0)
- (const_int 5)
- (const_int 1)
- (const_int 6)
- (const_int 2)
- (const_int 7)
- (const_int 3)]))
- (const_int 85)))]
- "TARGET_MMX"
- "punpcklbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpcklwd"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (vec_merge:V4HI
- (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
- (parallel [(const_int 2)
- (const_int 0)
- (const_int 3)
- (const_int 1)]))
- (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 1)
- (const_int 3)]))
- (const_int 5)))]
- "TARGET_MMX"
- "punpcklwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-(define_insn "mmx_punpckldq"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_merge:V2SI
- (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
- (parallel [(const_int 1)
- (const_int 0)]))
- (match_operand:V2SI 2 "register_operand" "y")
- (const_int 1)))]
- "TARGET_MMX"
- "punpckldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "DI")])
-
-
-;; Miscellaneous stuff
-
-(define_insn "emms"
- [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
- (clobber (reg:XF 8))
- (clobber (reg:XF 9))
- (clobber (reg:XF 10))
- (clobber (reg:XF 11))
- (clobber (reg:XF 12))
- (clobber (reg:XF 13))
- (clobber (reg:XF 14))
- (clobber (reg:XF 15))
- (clobber (reg:DI 29))
- (clobber (reg:DI 30))
- (clobber (reg:DI 31))
- (clobber (reg:DI 32))
- (clobber (reg:DI 33))
- (clobber (reg:DI 34))
- (clobber (reg:DI 35))
- (clobber (reg:DI 36))]
- "TARGET_MMX"
- "emms"
- [(set_attr "type" "mmx")
- (set_attr "memory" "unknown")])
-
-(define_insn "ldmxcsr"
- [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
- UNSPECV_LDMXCSR)]
- "TARGET_SSE"
- "ldmxcsr\t%0"
- [(set_attr "type" "sse")
- (set_attr "memory" "load")])
-
-(define_insn "stmxcsr"
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
- "TARGET_SSE"
- "stmxcsr\t%0"
- [(set_attr "type" "sse")
- (set_attr "memory" "store")])
-
-(define_expand "sfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
- "TARGET_SSE || TARGET_3DNOW_A"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*sfence_insn"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
- "TARGET_SSE || TARGET_3DNOW_A"
- "sfence"
- [(set_attr "type" "sse")
- (set_attr "memory" "unknown")])
-
-(define_expand "sse_prologue_save"
- [(parallel [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
- (use (match_operand:DI 1 "register_operand" ""))
- (use (match_operand:DI 2 "immediate_operand" ""))
- (use (label_ref:DI (match_operand 3 "" "")))])]
- "TARGET_64BIT"
- "")
-
-(define_insn "*sse_prologue_save_insn"
- [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
- (match_operand:DI 4 "const_int_operand" "n")))
- (unspec:BLK [(reg:DI 21)
- (reg:DI 22)
- (reg:DI 23)
- (reg:DI 24)
- (reg:DI 25)
- (reg:DI 26)
- (reg:DI 27)
- (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
- (use (match_operand:DI 1 "register_operand" "r"))
- (use (match_operand:DI 2 "const_int_operand" "i"))
- (use (label_ref:DI (match_operand 3 "" "X")))]
- "TARGET_64BIT
- && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
- && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
- "*
-{
- int i;
- operands[0] = gen_rtx_MEM (Pmode,
- gen_rtx_PLUS (Pmode, operands[0], operands[4]));
- output_asm_insn (\"jmp\\t%A1\", operands);
- for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
- {
- operands[4] = adjust_address (operands[0], DImode, i*16);
- operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
- PUT_MODE (operands[4], TImode);
- if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
- output_asm_insn (\"rex\", operands);
- output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
- }
- (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
- CODE_LABEL_NUMBER (operands[3]));
- RET;
-}
- "
- [(set_attr "type" "other")
- (set_attr "length_immediate" "0")
- (set_attr "length_address" "0")
- (set_attr "length" "135")
- (set_attr "memory" "store")
- (set_attr "modrm" "0")
- (set_attr "mode" "DI")])
-
-;; 3Dnow! instructions
-
-(define_insn "addv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfadd\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "subv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfsub\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "subrv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
- (match_operand:V2SF 1 "register_operand" "0")))]
- "TARGET_3DNOW"
- "pfsubr\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "gtv2sf3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfcmpgt\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "V2SF")])
-
-(define_insn "gev2sf3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfcmpge\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "V2SF")])
-
-(define_insn "eqv2sf3"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfcmpeq\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxcmp")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pfmaxv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfmax\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pfminv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfmin\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "mulv2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pfmul\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "V2SF")])
-
-(define_insn "femms"
- [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
- (clobber (reg:XF 8))
- (clobber (reg:XF 9))
- (clobber (reg:XF 10))
- (clobber (reg:XF 11))
- (clobber (reg:XF 12))
- (clobber (reg:XF 13))
- (clobber (reg:XF 14))
- (clobber (reg:XF 15))
- (clobber (reg:DI 29))
- (clobber (reg:DI 30))
- (clobber (reg:DI 31))
- (clobber (reg:DI 32))
- (clobber (reg:DI 33))
- (clobber (reg:DI 34))
- (clobber (reg:DI 35))
- (clobber (reg:DI 36))]
- "TARGET_3DNOW"
- "femms"
- [(set_attr "type" "mmx")
- (set_attr "memory" "none")])
-
-(define_insn "pf2id"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pf2id\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pf2iw"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (sign_extend:V2SI
- (ss_truncate:V2HI
- (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
- "TARGET_3DNOW_A"
- "pf2iw\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pfacc"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (vec_concat:V2SF
- (plus:SF
- (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)])))
- (plus:SF
- (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 1)])))))]
- "TARGET_3DNOW"
- "pfacc\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pfnacc"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (vec_concat:V2SF
- (minus:SF
- (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)])))
- (minus:SF
- (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 1)])))))]
- "TARGET_3DNOW_A"
- "pfnacc\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pfpnacc"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (vec_concat:V2SF
- (minus:SF
- (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 1)
- (parallel [(const_int 1)])))
- (plus:SF
- (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
- (parallel [(const_int 0)]))
- (vec_select:SF (match_dup 2)
- (parallel [(const_int 1)])))))]
- "TARGET_3DNOW_A"
- "pfpnacc\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "V2SF")])
-
-(define_insn "pi2fw"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (float:V2SF
- (vec_concat:V2SI
- (sign_extend:SI
- (truncate:HI
- (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)]))))
- (sign_extend:SI
- (truncate:HI
- (vec_select:SI (match_dup 1)
- (parallel [(const_int 1)])))))))]
- "TARGET_3DNOW_A"
- "pi2fw\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "V2SF")])
-
-(define_insn "floatv2si2"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW"
- "pi2fd\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "V2SF")])
-
-;; This insn is identical to pavgb in operation, but the opcode is
-;; different. To avoid accidentally matching pavgb, use an unspec.
-
-(define_insn "pavgusb"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
- (unspec:V8QI
- [(match_operand:V8QI 1 "register_operand" "0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
- UNSPEC_PAVGUSB))]
- "TARGET_3DNOW"
- "pavgusb\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxshft")
- (set_attr "mode" "TI")])
-
-;; 3DNow reciprocal and sqrt
-
-(define_insn "pfrcpv2sf2"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
- UNSPEC_PFRCP))]
- "TARGET_3DNOW"
- "pfrcp\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmx")
- (set_attr "mode" "TI")])
-
-(define_insn "pfrcpit1v2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
- UNSPEC_PFRCPIT1))]
- "TARGET_3DNOW"
- "pfrcpit1\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmx")
- (set_attr "mode" "TI")])
-
-(define_insn "pfrcpit2v2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
- UNSPEC_PFRCPIT2))]
- "TARGET_3DNOW"
- "pfrcpit2\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmx")
- (set_attr "mode" "TI")])
-
-(define_insn "pfrsqrtv2sf2"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
- UNSPEC_PFRSQRT))]
- "TARGET_3DNOW"
- "pfrsqrt\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmx")
- (set_attr "mode" "TI")])
-
-(define_insn "pfrsqit1v2sf3"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
- (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
- UNSPEC_PFRSQIT1))]
- "TARGET_3DNOW"
- "pfrsqit1\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmx")
- (set_attr "mode" "TI")])
-
-(define_insn "pmulhrwv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
- (truncate:V4HI
- (lshiftrt:V4SI
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (match_operand:V4HI 1 "register_operand" "0"))
- (sign_extend:V4SI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
- (const_vector:V4SI [(const_int 32768)
- (const_int 32768)
- (const_int 32768)
- (const_int 32768)]))
- (const_int 16))))]
- "TARGET_3DNOW"
- "pmulhrw\\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "TI")])
-
-(define_insn "pswapdv2si2"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
- (parallel [(const_int 1) (const_int 0)])))]
- "TARGET_3DNOW_A"
- "pswapd\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "TI")])
-
-(define_insn "pswapdv2sf2"
- [(set (match_operand:V2SF 0 "register_operand" "=y")
- (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
- (parallel [(const_int 1) (const_int 0)])))]
- "TARGET_3DNOW_A"
- "pswapd\\t{%1, %0|%0, %1}"
- [(set_attr "type" "mmxcvt")
- (set_attr "mode" "TI")])
-
-(define_expand "prefetch"
- [(prefetch (match_operand 0 "address_operand" "")
- (match_operand:SI 1 "const_int_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))]
- "TARGET_PREFETCH_SSE || TARGET_3DNOW"
-{
- int rw = INTVAL (operands[1]);
- int locality = INTVAL (operands[2]);
-
- if (rw != 0 && rw != 1)
- abort ();
- if (locality < 0 || locality > 3)
- abort ();
- if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
- abort ();
-
- /* Use 3dNOW prefetch in case we are asking for write prefetch not
- suported by SSE counterpart or the SSE prefetch is not available
- (K6 machines). Otherwise use SSE prefetch as it allows specifying
- of locality. */
- if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
- operands[2] = GEN_INT (3);
- else
- operands[1] = const0_rtx;
-})
-
-(define_insn "*prefetch_sse"
- [(prefetch (match_operand:SI 0 "address_operand" "p")
- (const_int 0)
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_PREFETCH_SSE && !TARGET_64BIT"
-{
- static const char * const patterns[4] = {
- "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
- };
-
- int locality = INTVAL (operands[1]);
- if (locality < 0 || locality > 3)
- abort ();
-
- return patterns[locality];
-}
- [(set_attr "type" "sse")
- (set_attr "memory" "none")])
-
-(define_insn "*prefetch_sse_rex"
- [(prefetch (match_operand:DI 0 "address_operand" "p")
- (const_int 0)
- (match_operand:SI 1 "const_int_operand" ""))]
- "TARGET_PREFETCH_SSE && TARGET_64BIT"
-{
- static const char * const patterns[4] = {
- "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
- };
-
- int locality = INTVAL (operands[1]);
- if (locality < 0 || locality > 3)
- abort ();
-
- return patterns[locality];
-}
- [(set_attr "type" "sse")
- (set_attr "memory" "none")])
-
-(define_insn "*prefetch_3dnow"
- [(prefetch (match_operand:SI 0 "address_operand" "p")
- (match_operand:SI 1 "const_int_operand" "n")
- (const_int 3))]
- "TARGET_3DNOW && !TARGET_64BIT"
-{
- if (INTVAL (operands[1]) == 0)
- return "prefetch\t%a0";
- else
- return "prefetchw\t%a0";
-}
- [(set_attr "type" "mmx")
- (set_attr "memory" "none")])
-
-(define_insn "*prefetch_3dnow_rex"
- [(prefetch (match_operand:DI 0 "address_operand" "p")
- (match_operand:SI 1 "const_int_operand" "n")
- (const_int 3))]
- "TARGET_3DNOW && TARGET_64BIT"
-{
- if (INTVAL (operands[1]) == 0)
- return "prefetch\t%a0";
- else
- return "prefetchw\t%a0";
-}
- [(set_attr "type" "mmx")
- (set_attr "memory" "none")])
-
-;; SSE2 support
-
-(define_insn "addv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "addpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmaddv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "addsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-
-(define_insn "subv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "subpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmsubv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "subsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-
-(define_insn "mulv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "mulpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmmulv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "mulsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssemul")
- (set_attr "mode" "DF")])
-
-(define_insn "divv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "divpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmdivv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "divsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssediv")
- (set_attr "mode" "DF")])
-
-;; SSE min/max
-
-(define_insn "smaxv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "maxpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmsmaxv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "maxsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-
-(define_insn "sminv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "minpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmsminv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE2"
- "minsd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "DF")])
-;; SSE2 square root. There doesn't appear to be an extension for the
-;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
-
-(define_insn "sqrtv2df2"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
- "TARGET_SSE2"
- "sqrtpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmsqrtv2df2"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
- (match_operand:V2DF 2 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE2"
- "sqrtsd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "SF")])
-
-;; SSE mask-generating compares
-
-(define_insn "maskcmpv2df3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (match_operator:V2DI 3 "sse_comparison_operator"
- [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
- "TARGET_SSE2"
- "cmp%D3pd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "V2DF")])
-
-(define_insn "maskncmpv2df3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (not:V2DI
- (match_operator:V2DI 3 "sse_comparison_operator"
- [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
- "TARGET_SSE2"
-{
- if (GET_CODE (operands[3]) == UNORDERED)
- return "cmpordps\t{%2, %0|%0, %2}";
- else
- return "cmpn%D3pd\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "V2DF")])
-
-(define_insn "vmmaskcmpv2df3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (match_operator:V2DI 3 "sse_comparison_operator"
- [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "x")])
- (subreg:V2DI (match_dup 1) 0)
- (const_int 1)))]
- "TARGET_SSE2"
- "cmp%D3sd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "DF")])
-
-(define_insn "vmmaskncmpv2df3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (not:V2DI
- (match_operator:V2DI 3 "sse_comparison_operator"
- [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
- (subreg:V2DI (match_dup 1) 0)
- (const_int 1)))]
- "TARGET_SSE2"
-{
- if (GET_CODE (operands[3]) == UNORDERED)
- return "cmpordsd\t{%2, %0|%0, %2}";
- else
- return "cmpn%D3sd\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "DF")])
-
-(define_insn "sse2_comi"
- [(set (reg:CCFP FLAGS_REG)
- (compare:CCFP (vec_select:DF
- (match_operand:V2DF 0 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:DF
- (match_operand:V2DF 1 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE2"
- "comisd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "mode" "DF")])
-
-(define_insn "sse2_ucomi"
- [(set (reg:CCFPU FLAGS_REG)
- (compare:CCFPU (vec_select:DF
- (match_operand:V2DF 0 "register_operand" "x")
- (parallel [(const_int 0)]))
- (vec_select:DF
- (match_operand:V2DF 1 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE2"
- "ucomisd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "mode" "DF")])
-
-;; SSE Strange Moves.
-
-(define_insn "sse2_movmskpd"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
- "TARGET_SSE2"
- "movmskpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_pmovmskb"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
- UNSPEC_MOVMSK))]
- "TARGET_SSE2"
- "pmovmskb\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_maskmovdqu"
- [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "register_operand" "x")]
- UNSPEC_MASKMOV))]
- "TARGET_SSE2"
- ;; @@@ check ordering of operands in intel/nonintel syntax
- "maskmovdqu\t{%2, %1|%1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_maskmovdqu_rex64"
- [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
- (match_operand:V16QI 2 "register_operand" "x")]
- UNSPEC_MASKMOV))]
- "TARGET_SSE2"
- ;; @@@ check ordering of operands in intel/nonintel syntax
- "maskmovdqu\t{%2, %1|%1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movntv2df"
- [(set (match_operand:V2DF 0 "memory_operand" "=m")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "TARGET_SSE2"
- "movntpd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_movntv2di"
- [(set (match_operand:V2DI 0 "memory_operand" "=m")
- (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
- UNSPEC_MOVNT))]
- "TARGET_SSE2"
- "movntdq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movntsi"
- [(set (match_operand:SI 0 "memory_operand" "=m")
- (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
- UNSPEC_MOVNT))]
- "TARGET_SSE2"
- "movnti\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-;; SSE <-> integer/MMX conversions
-
-;; Conversions between SI and SF
-
-(define_insn "cvtdq2ps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "cvtdq2ps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "cvtps2dq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "cvtps2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "cvttps2dq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
- UNSPEC_FIX))]
- "TARGET_SSE2"
- "cvttps2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-;; Conversions between SI and DF
-
-(define_insn "cvtdq2pd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (float:V2DF (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel
- [(const_int 0)
- (const_int 1)]))))]
- "TARGET_SSE2"
- "cvtdq2pd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "cvtpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_concat:V4SI
- (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
- (const_vector:V2SI [(const_int 0) (const_int 0)])))]
- "TARGET_SSE2"
- "cvtpd2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "cvttpd2dq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_concat:V4SI
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
- UNSPEC_FIX)
- (const_vector:V2SI [(const_int 0) (const_int 0)])))]
- "TARGET_SSE2"
- "cvttpd2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "cvtpd2pi"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "cvtpd2pi\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "cvttpd2pi"
- [(set (match_operand:V2SI 0 "register_operand" "=y")
- (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
- UNSPEC_FIX))]
- "TARGET_SSE2"
- "cvttpd2pi\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "cvtpi2pd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
- "TARGET_SSE2"
- "cvtpi2pd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-;; Conversions between SI and DF
-
-(define_insn "cvtsd2si"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE2"
- "cvtsd2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "mode" "SI")])
-
-(define_insn "cvtsd2siq"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE2 && TARGET_64BIT"
- "cvtsd2siq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "athlon_decode" "double,vector")
- (set_attr "mode" "DI")])
-
-(define_insn "cvttsd2si"
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
- (parallel [(const_int 0)]))] UNSPEC_FIX))]
- "TARGET_SSE2"
- "cvttsd2si\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "SI")
- (set_attr "athlon_decode" "double,vector")])
-
-(define_insn "cvttsd2siq"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
- (parallel [(const_int 0)]))] UNSPEC_FIX))]
- "TARGET_SSE2 && TARGET_64BIT"
- "cvttsd2siq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DI")
- (set_attr "athlon_decode" "double,vector")])
-
-(define_insn "cvtsi2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x")
- (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
- (vec_duplicate:V2DF
- (float:DF
- (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
- (const_int 2)))]
- "TARGET_SSE2"
- "cvtsi2sd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,direct")])
-
-(define_insn "cvtsi2sdq"
- [(set (match_operand:V2DF 0 "register_operand" "=x,x")
- (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
- (vec_duplicate:V2DF
- (float:DF
- (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
- (const_int 2)))]
- "TARGET_SSE2 && TARGET_64BIT"
- "cvtsi2sdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseicvt")
- (set_attr "mode" "DF")
- (set_attr "athlon_decode" "double,direct")])
-
-;; Conversions between SF and DF
-
-(define_insn "cvtsd2ss"
- [(set (match_operand:V4SF 0 "register_operand" "=x,x")
- (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
- (vec_duplicate:V4SF
- (float_truncate:V2SF
- (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
- (const_int 14)))]
- "TARGET_SSE2"
- "cvtsd2ss\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "athlon_decode" "vector,double")
- (set_attr "mode" "SF")])
-
-(define_insn "cvtss2sd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)])))
- (const_int 2)))]
- "TARGET_SSE2"
- "cvtss2sd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
-
-(define_insn "cvtpd2ps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (subreg:V4SF
- (vec_concat:V4SI
- (subreg:V2SI (float_truncate:V2SF
- (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
- (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
- "TARGET_SSE2"
- "cvtpd2ps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "cvtps2pd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (float_extend:V2DF
- (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 1)]))))]
- "TARGET_SSE2"
- "cvtps2pd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-;; SSE2 variants of MMX insns
-
-;; MMX arithmetic
-
-(define_insn "addv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "addv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "addv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "addv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "ssaddv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddsb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "ssaddv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "usaddv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddusb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "usaddv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "paddusw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "subv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "subv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "subv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "subv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "sssubv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubsb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "sssubv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "ussubv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubusb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "ussubv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "psubusw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "mulv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pmullw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "mode" "TI")])
-
-(define_insn "smulv8hi3_highpart"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
- (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
- (const_int 16))))]
- "TARGET_SSE2"
- "pmulhw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "mode" "TI")])
-
-(define_insn "umulv8hi3_highpart"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (truncate:V8HI
- (lshiftrt:V8SI
- (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
- (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
- (const_int 16))))]
- "TARGET_SSE2"
- "pmulhuw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_umulsidi3"
- [(set (match_operand:DI 0 "register_operand" "=y")
- (mult:DI (zero_extend:DI (vec_select:SI
- (match_operand:V2SI 1 "register_operand" "0")
- (parallel [(const_int 0)])))
- (zero_extend:DI (vec_select:SI
- (match_operand:V2SI 2 "nonimmediate_operand" "ym")
- (parallel [(const_int 0)])))))]
- "TARGET_SSE2"
- "pmuludq\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxmul")
- (set_attr "mode" "DI")])
-
-(define_insn "sse2_umulv2siv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (mult:V2DI (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "register_operand" "0")
- (parallel [(const_int 0) (const_int 2)])))
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0) (const_int 2)])))))]
- "TARGET_SSE2"
- "pmuludq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseimul")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_pmaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))))]
- "TARGET_SSE2"
- "pmaddwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-;; Same as pxor, but don't show input operands so that we don't think
-;; they are live.
-(define_insn "sse2_clrti"
- [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
- "TARGET_SSE2"
-{
- if (get_attr_mode (insn) == MODE_TI)
- return "pxor\t%0, %0";
- else
- return "xorps\t%0, %0";
-}
- [(set_attr "type" "ssemov")
- (set_attr "memory" "none")
- (set (attr "mode")
- (if_then_else
- (ne (symbol_ref "optimize_size")
- (const_int 0))
- (const_string "V4SF")
- (const_string "TI")))])
-
-;; MMX unsigned averages/sum of absolute differences
-
-(define_insn "sse2_uavgv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (ashiftrt:V16QI
- (plus:V16QI (plus:V16QI
- (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
- (const_vector:V16QI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1)))]
- "TARGET_SSE2"
- "pavgb\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_uavgv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ashiftrt:V8HI
- (plus:V8HI (plus:V8HI
- (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
- (const_vector:V8HI [(const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)
- (const_int 1) (const_int 1)]))
- (const_int 1)))]
- "TARGET_SSE2"
- "pavgw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-;; @@@ this isn't the right representation.
-(define_insn "sse2_psadbw"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
- UNSPEC_PSADBW))]
- "TARGET_SSE2"
- "psadbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-
-;; MMX insert/extract/shuffle
-
-(define_insn "sse2_pinsrw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (vec_duplicate:V8HI
- (truncate:HI
- (match_operand:SI 2 "nonimmediate_operand" "rm")))
- (match_operand:SI 3 "const_0_to_255_operand" "N")))]
- "TARGET_SSE2"
- "pinsrw\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_pextrw"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (zero_extend:SI
- (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
- (parallel
- [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
- "TARGET_SSE2"
- "pextrw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_pshufd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (unspec:V4SI [(match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_SHUFFLE))]
- "TARGET_SSE2"
- "pshufd\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_pshuflw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_PSHUFLW))]
- "TARGET_SSE2"
- "pshuflw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_pshufhw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "immediate_operand" "i")]
- UNSPEC_PSHUFHW))]
- "TARGET_SSE2"
- "pshufhw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-;; MMX mask-generating comparisons
-
-(define_insn "eqv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpeqb\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-(define_insn "eqv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpeqw\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-(define_insn "eqv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpeqd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-(define_insn "gtv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpgtb\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-(define_insn "gtv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpgtw\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-(define_insn "gtv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pcmpgtd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecmp")
- (set_attr "mode" "TI")])
-
-
-;; MMX max/min insns
-
-(define_insn "umaxv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pmaxub\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "smaxv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pmaxsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "uminv16qi3"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pminub\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-(define_insn "sminv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2"
- "pminsw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
- (set_attr "mode" "TI")])
-
-
-;; MMX shifts
-
-(define_insn "ashrv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psraw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashrv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psrad\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psrlw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psrld\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psrlq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv8hi3"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psllw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "pslld\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv2di3"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "xi")))]
- "TARGET_SSE2"
- "psllq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashrv8hi3_ti"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psraw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashrv4si3_ti"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psrad\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv8hi3_ti"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psrlw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv4si3_ti"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psrld\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "lshrv2di3_ti"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psrlq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv8hi3_ti"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psllw\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv4si3_ti"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "pslld\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "ashlv2di3_ti"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
- (subreg:SI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
- "TARGET_SSE2"
- "psllq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-;; See logical MMX insns for the reason for the unspec. Strictly speaking
-;; we wouldn't need here it since we never generate TImode arithmetic.
-
-;; There has to be some kind of prize for the weirdest new instruction...
-(define_insn "sse2_ashlti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (unspec:TI
- [(ashift:TI (match_operand:TI 1 "register_operand" "0")
- (mult:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int 8)))] UNSPEC_NOP))]
- "TARGET_SSE2"
- "pslldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_lshrti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (unspec:TI
- [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (mult:SI (match_operand:SI 2 "immediate_operand" "i")
- (const_int 8)))] UNSPEC_NOP))]
- "TARGET_SSE2"
- "psrldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "mode" "TI")])
-
-;; SSE unpack
-
-(define_insn "sse2_unpckhpd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_concat:V2DF
- (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
- (parallel [(const_int 1)]))
- (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
- (parallel [(const_int 1)]))))]
- "TARGET_SSE2"
- "unpckhpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_unpcklpd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_concat:V2DF
- (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
- (parallel [(const_int 0)]))
- (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE2"
- "unpcklpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-;; MMX pack/unpack insns.
-
-(define_insn "sse2_packsswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_concat:V16QI
- (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
- (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
- "TARGET_SSE2"
- "packsswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_packssdw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_concat:V8HI
- (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
- (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
- "TARGET_SSE2"
- "packssdw\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_packuswb"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_concat:V16QI
- (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
- (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
- "TARGET_SSE2"
- "packuswb\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpckhbw"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_merge:V16QI
- (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (parallel [(const_int 8) (const_int 0)
- (const_int 9) (const_int 1)
- (const_int 10) (const_int 2)
- (const_int 11) (const_int 3)
- (const_int 12) (const_int 4)
- (const_int 13) (const_int 5)
- (const_int 14) (const_int 6)
- (const_int 15) (const_int 7)]))
- (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
- (parallel [(const_int 0) (const_int 8)
- (const_int 1) (const_int 9)
- (const_int 2) (const_int 10)
- (const_int 3) (const_int 11)
- (const_int 4) (const_int 12)
- (const_int 5) (const_int 13)
- (const_int 6) (const_int 14)
- (const_int 7) (const_int 15)]))
- (const_int 21845)))]
- "TARGET_SSE2"
- "punpckhbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpckhwd"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_merge:V8HI
- (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (parallel [(const_int 4) (const_int 0)
- (const_int 5) (const_int 1)
- (const_int 6) (const_int 2)
- (const_int 7) (const_int 3)]))
- (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)
- (const_int 2) (const_int 6)
- (const_int 3) (const_int 7)]))
- (const_int 85)))]
- "TARGET_SSE2"
- "punpckhwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpckhdq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (parallel [(const_int 2) (const_int 0)
- (const_int 3) (const_int 1)]))
- (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
- (parallel [(const_int 0) (const_int 2)
- (const_int 1) (const_int 3)]))
- (const_int 5)))]
- "TARGET_SSE2"
- "punpckhdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpcklbw"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (vec_merge:V16QI
- (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
- (parallel [(const_int 0) (const_int 8)
- (const_int 1) (const_int 9)
- (const_int 2) (const_int 10)
- (const_int 3) (const_int 11)
- (const_int 4) (const_int 12)
- (const_int 5) (const_int 13)
- (const_int 6) (const_int 14)
- (const_int 7) (const_int 15)]))
- (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
- (parallel [(const_int 8) (const_int 0)
- (const_int 9) (const_int 1)
- (const_int 10) (const_int 2)
- (const_int 11) (const_int 3)
- (const_int 12) (const_int 4)
- (const_int 13) (const_int 5)
- (const_int 14) (const_int 6)
- (const_int 15) (const_int 7)]))
- (const_int 21845)))]
- "TARGET_SSE2"
- "punpcklbw\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpcklwd"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (vec_merge:V8HI
- (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
- (parallel [(const_int 0) (const_int 4)
- (const_int 1) (const_int 5)
- (const_int 2) (const_int 6)
- (const_int 3) (const_int 7)]))
- (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
- (parallel [(const_int 4) (const_int 0)
- (const_int 5) (const_int 1)
- (const_int 6) (const_int 2)
- (const_int 7) (const_int 3)]))
- (const_int 85)))]
- "TARGET_SSE2"
- "punpcklwd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpckldq"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
- (parallel [(const_int 0) (const_int 2)
- (const_int 1) (const_int 3)]))
- (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
- (parallel [(const_int 2) (const_int 0)
- (const_int 3) (const_int 1)]))
- (const_int 5)))]
- "TARGET_SSE2"
- "punpckldq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpcklqdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
- (parallel [(const_int 1)
- (const_int 0)]))
- (match_operand:V2DI 1 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE2"
- "punpcklqdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_punpckhqdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_merge:V2DI
- (match_operand:V2DI 1 "register_operand" "0")
- (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
- (parallel [(const_int 1)
- (const_int 0)]))
- (const_int 1)))]
- "TARGET_SSE2"
- "punpckhqdq\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-;; SSE2 moves
-
-(define_insn "sse2_movapd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
- (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVA))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movapd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_movupd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
- (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movupd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_movdqa"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
- (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVA))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movdqa\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movdqu"
- [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
- (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
- UNSPEC_MOVU))]
- "TARGET_SSE2
- && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
- "movdqu\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movdq2q"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
- (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
- (parallel [(const_int 0)])))]
- "TARGET_SSE2 && !TARGET_64BIT"
- "@
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movdq2q_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
- (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
- (parallel [(const_int 0)])))]
- "TARGET_SSE2 && TARGET_64BIT"
- "@
- movq\t{%1, %0|%0, %1}
- movdq2q\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movq2dq"
- [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
- (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
- (const_int 0)))]
- "TARGET_SSE2 && !TARGET_64BIT"
- "@
- movq\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt,ssemov")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movq2dq_rex64"
- [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
- (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
- (const_int 0)))]
- "TARGET_SSE2 && TARGET_64BIT"
- "@
- movq\t{%1, %0|%0, %1}
- movq2dq\t{%1, %0|%0, %1}
- movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt,ssemov,ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (vec_concat:V2DI (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)]))
- (const_int 0)))]
- "TARGET_SSE2"
- "movq\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_loadd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (vec_merge:V4SI
- (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
- (const_vector:V4SI [(const_int 0)
- (const_int 0)
- (const_int 0)
- (const_int 0)])
- (const_int 1)))]
- "TARGET_SSE2"
- "movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_stored"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
- (vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x")
- (parallel [(const_int 0)])))]
- "TARGET_SSE2"
- "movd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssemov")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_movhpd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
- (vec_merge:V2DF
- (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
- (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
- (const_int 1)))]
- "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
- "movhpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_expand "sse2_loadsd"
- [(match_operand:V2DF 0 "register_operand" "")
- (match_operand:DF 1 "memory_operand" "")]
- "TARGET_SSE2"
-{
- emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
- CONST0_RTX (V2DFmode)));
- DONE;
-})
-
-(define_insn "sse2_loadsd_1"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_merge:V2DF
- (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
- (match_operand:V2DF 2 "const0_operand" "X")
- (const_int 1)))]
- "TARGET_SSE2"
- "movsd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
-
-(define_insn "sse2_movsd"
- [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
- (vec_merge:V2DF
- (match_operand:V2DF 1 "nonimmediate_operand" "0,0,0")
- (match_operand:V2DF 2 "nonimmediate_operand" "x,m,x")
- (const_int 2)))]
- "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
- "@movsd\t{%2, %0|%0, %2}
- movlpd\t{%2, %0|%0, %2}
- movlpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF,V2DF,V2DF")])
-
-(define_insn "sse2_storesd"
- [(set (match_operand:DF 0 "memory_operand" "=m")
- (vec_select:DF
- (match_operand:V2DF 1 "register_operand" "x")
- (parallel [(const_int 0)])))]
- "TARGET_SSE2"
- "movsd\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
-
-(define_insn "sse2_shufpd"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "immediate_operand" "i")]
- UNSPEC_SHUFFLE))]
- "TARGET_SSE2"
- ;; @@@ check operand order for intel/nonintel syntax
- "shufpd\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V2DF")])
-
-(define_insn "sse2_clflush"
- [(unspec_volatile [(match_operand 0 "address_operand" "p")]
- UNSPECV_CLFLUSH)]
- "TARGET_SSE2"
- "clflush\t%a0"
- [(set_attr "type" "sse")
- (set_attr "memory" "unknown")])
-
-(define_expand "sse2_mfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
- "TARGET_SSE2"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*mfence_insn"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
- "TARGET_SSE2"
- "mfence"
- [(set_attr "type" "sse")
- (set_attr "memory" "unknown")])
-
-(define_expand "sse2_lfence"
- [(set (match_dup 0)
- (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
- "TARGET_SSE2"
-{
- operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
- MEM_VOLATILE_P (operands[0]) = 1;
-})
-
-(define_insn "*lfence_insn"
- [(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
- "TARGET_SSE2"
- "lfence"
- [(set_attr "type" "sse")
- (set_attr "memory" "unknown")])
-
-;; SSE3
-
-(define_insn "mwait"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
- (match_operand:SI 1 "register_operand" "c")]
- UNSPECV_MWAIT)]
- "TARGET_SSE3"
- "mwait\t%0, %1"
- [(set_attr "length" "3")])
-
-(define_insn "monitor"
- [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
- (match_operand:SI 1 "register_operand" "c")
- (match_operand:SI 2 "register_operand" "d")]
- UNSPECV_MONITOR)]
- "TARGET_SSE3"
- "monitor\t%0, %1, %2"
- [(set_attr "length" "3")])
-
-;; SSE3 arithmetic
-
-(define_insn "addsubv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
- UNSPEC_ADDSUB))]
- "TARGET_SSE3"
- "addsubps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V4SF")])
-
-(define_insn "addsubv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
- UNSPEC_ADDSUB))]
- "TARGET_SSE3"
- "addsubpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "haddv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
- UNSPEC_HADD))]
- "TARGET_SSE3"
- "haddps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V4SF")])
-
-(define_insn "haddv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
- UNSPEC_HADD))]
- "TARGET_SSE3"
- "haddpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "hsubv4sf3"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
- (match_operand:V4SF 2 "nonimmediate_operand" "xm")]
- UNSPEC_HSUB))]
- "TARGET_SSE3"
- "hsubps\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V4SF")])
-
-(define_insn "hsubv2df3"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
- (match_operand:V2DF 2 "nonimmediate_operand" "xm")]
- UNSPEC_HSUB))]
- "TARGET_SSE3"
- "hsubpd\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseadd")
- (set_attr "mode" "V2DF")])
-
-(define_insn "movshdup"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))]
- "TARGET_SSE3"
- "movshdup\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "movsldup"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF
- [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))]
- "TARGET_SSE3"
- "movsldup\t{%1, %0|%0, %1}"
- [(set_attr "type" "sse")
- (set_attr "mode" "V4SF")])
-
-(define_insn "lddqu"
- [(set (match_operand:V16QI 0 "register_operand" "=x")
- (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
- UNSPEC_LDQQU))]
- "TARGET_SSE3"
- "lddqu\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "TI")])
-
-(define_insn "loadddup"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))]
- "TARGET_SSE3"
- "movddup\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
-
-(define_insn "movddup"
- [(set (match_operand:V2DF 0 "register_operand" "=x")
- (vec_duplicate:V2DF
- (vec_select:DF (match_operand:V2DF 1 "register_operand" "x")
- (parallel [(const_int 0)]))))]
- "TARGET_SSE3"
- "movddup\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "DF")])
+(include "sse.md")
+(include "mmx.md")
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