/* Definitions of target machine for GCC for IA-32.
Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+ 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
+ Inc.
This file is part of GCC.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
/* The purpose of this file is to define the characteristics of the i386,
independent of assembler syntax or operating system.
ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
that start with ASM_ or end in ASM_OP. */
+/* Redefines for option macros. */
+
+#define TARGET_64BIT OPTION_ISA_64BIT
+#define TARGET_MMX OPTION_ISA_MMX
+#define TARGET_3DNOW OPTION_ISA_3DNOW
+#define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
+#define TARGET_SSE OPTION_ISA_SSE
+#define TARGET_SSE2 OPTION_ISA_SSE2
+#define TARGET_SSE3 OPTION_ISA_SSE3
+#define TARGET_SSSE3 OPTION_ISA_SSSE3
+#define TARGET_SSE4_1 OPTION_ISA_SSE4_1
+#define TARGET_SSE4_2 OPTION_ISA_SSE4_2
+#define TARGET_SSE4A OPTION_ISA_SSE4A
+
+#include "config/vxworks-dummy.h"
+
+/* Algorithm to expand string function with. */
+enum stringop_alg
+{
+ no_stringop,
+ libcall,
+ rep_prefix_1_byte,
+ rep_prefix_4_byte,
+ rep_prefix_8_byte,
+ loop_1_byte,
+ loop,
+ unrolled_loop
+};
+
+#define NAX_STRINGOP_ALGS 4
+
+/* Specify what algorithm to use for stringops on known size.
+ When size is unknown, the UNKNOWN_SIZE alg is used. When size is
+ known at compile time or estimated via feedback, the SIZE array
+ is walked in order until MAX is greater then the estimate (or -1
+ means infinity). Corresponding ALG is used then.
+ For example initializer:
+ {{256, loop}, {-1, rep_prefix_4_byte}}
+ will use loop for blocks smaller or equal to 256 bytes, rep prefix will
+ be used otherwise. */
+struct stringop_algs
+{
+ const enum stringop_alg unknown_size;
+ const struct stringop_strategy {
+ const int max;
+ const enum stringop_alg alg;
+ } size [NAX_STRINGOP_ALGS];
+};
+
/* Define the specific costs for a given cpu */
struct processor_costs {
const int fabs; /* cost of FABS instruction. */
const int fchs; /* cost of FCHS instruction. */
const int fsqrt; /* cost of FSQRT instruction. */
+ /* Specify what algorithm
+ to use for stringops on unknown size. */
+ struct stringop_algs memcpy[2], memset[2];
};
extern const struct processor_costs *ix86_cost;
-/* Run-time compilation parameters selecting different hardware subsets. */
-
-extern int target_flags;
-
/* Macros used in the machine description to test the flags. */
/* configure can arrange to make this 2, to force a 486. */
#ifndef TARGET_CPU_DEFAULT
-#ifdef TARGET_64BIT_DEFAULT
-#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
-#else
-#define TARGET_CPU_DEFAULT 0
+#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
#endif
+
+#ifndef TARGET_FPMATH_DEFAULT
+#define TARGET_FPMATH_DEFAULT \
+ (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
#endif
-/* Masks for the -m switches */
-#define MASK_80387 0x00000001 /* Hardware floating point */
-#define MASK_RTD 0x00000002 /* Use ret that pops args */
-#define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
-#define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
-#define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
-#define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
-#define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
-#define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
-#define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
-#define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
-#define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
-#define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
-#define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
-#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
-#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
-#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
-#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
-#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
-#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
-#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
-#define MASK_64BIT 0x00100000 /* Produce 64bit code */
-#define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */
-#define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */
-
-/* Unused: 0x03e0000 */
-
-/* ... overlap with subtarget options starts by 0x04000000. */
-#define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
-
-/* Use the floating point instructions */
-#define TARGET_80387 (target_flags & MASK_80387)
-
-/* Compile using ret insn that pops args.
- This will not work unless you use prototypes at least
- for all functions that can take varying numbers of args. */
-#define TARGET_RTD (target_flags & MASK_RTD)
-
-/* Align doubles to a two word boundary. This breaks compatibility with
- the published ABI's for structures containing doubles, but produces
- faster code on the pentium. */
-#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
-
-/* Use push instructions to save outgoing args. */
-#define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
-
-/* Accumulate stack adjustments to prologue/epilogue. */
-#define TARGET_ACCUMULATE_OUTGOING_ARGS \
- (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
-
-/* Put uninitialized locals into bss, not data.
- Meaningful only on svr3. */
-#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
-
-/* Use IEEE floating point comparisons. These handle correctly the cases
- where the result of a comparison is unordered. Normally SIGFPE is
- generated in such cases, in which case this isn't needed. */
-#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
-
-/* Functions that return a floating point value may return that value
- in the 387 FPU or in 386 integer registers. If set, this flag causes
- the 387 to be used, which is compatible with most calling conventions. */
-#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
-
-/* Long double is 128bit instead of 96bit, even when only 80bits are used.
- This mode wastes cache, but avoid misaligned data accesses and simplifies
- address calculations. */
-#define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
-
-/* Disable generation of FP sin, cos and sqrt operations for 387.
- This is because FreeBSD lacks these in the math-emulator-code */
-#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
-
-/* Generate 387 floating point intrinsics for the current target. */
-#define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
-
-/* Don't create frame pointers for leaf functions */
-#define TARGET_OMIT_LEAF_FRAME_POINTER \
- (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
-
-/* Debug GO_IF_LEGITIMATE_ADDRESS */
-#define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
-
-/* Debug FUNCTION_ARG macros */
-#define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
+#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
/* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
compile-time constant. */
#ifdef IN_LIBGCC2
+#undef TARGET_64BIT
#ifdef __x86_64__
#define TARGET_64BIT 1
#else
#define TARGET_64BIT 0
#endif
#else
-#ifdef TARGET_BI_ARCH
-#define TARGET_64BIT (target_flags & MASK_64BIT)
-#else
+#ifndef TARGET_BI_ARCH
+#undef TARGET_64BIT
#if TARGET_64BIT_DEFAULT
#define TARGET_64BIT 1
#else
#define HAS_LONG_COND_BRANCH 1
#define HAS_LONG_UNCOND_BRANCH 1
-/* Avoid adding %gs:0 in TLS references; use %gs:address directly. */
-#define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
-
#define TARGET_386 (ix86_tune == PROCESSOR_I386)
#define TARGET_486 (ix86_tune == PROCESSOR_I486)
#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
+#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
#define TARGET_K6 (ix86_tune == PROCESSOR_K6)
#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
+#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
+#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
+#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
+#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
+#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
+
+/* Feature tests against the various tunings. */
+enum ix86_tune_indices {
+ X86_TUNE_USE_LEAVE,
+ X86_TUNE_PUSH_MEMORY,
+ X86_TUNE_ZERO_EXTEND_WITH_AND,
+ X86_TUNE_USE_BIT_TEST,
+ X86_TUNE_UNROLL_STRLEN,
+ X86_TUNE_DEEP_BRANCH_PREDICTION,
+ X86_TUNE_BRANCH_PREDICTION_HINTS,
+ X86_TUNE_DOUBLE_WITH_ADD,
+ X86_TUNE_USE_SAHF,
+ X86_TUNE_MOVX,
+ X86_TUNE_PARTIAL_REG_STALL,
+ X86_TUNE_PARTIAL_FLAG_REG_STALL,
+ X86_TUNE_USE_HIMODE_FIOP,
+ X86_TUNE_USE_SIMODE_FIOP,
+ X86_TUNE_USE_MOV0,
+ X86_TUNE_USE_CLTD,
+ X86_TUNE_USE_XCHGB,
+ X86_TUNE_SPLIT_LONG_MOVES,
+ X86_TUNE_READ_MODIFY_WRITE,
+ X86_TUNE_READ_MODIFY,
+ X86_TUNE_PROMOTE_QIMODE,
+ X86_TUNE_FAST_PREFIX,
+ X86_TUNE_SINGLE_STRINGOP,
+ X86_TUNE_QIMODE_MATH,
+ X86_TUNE_HIMODE_MATH,
+ X86_TUNE_PROMOTE_QI_REGS,
+ X86_TUNE_PROMOTE_HI_REGS,
+ X86_TUNE_ADD_ESP_4,
+ X86_TUNE_ADD_ESP_8,
+ X86_TUNE_SUB_ESP_4,
+ X86_TUNE_SUB_ESP_8,
+ X86_TUNE_INTEGER_DFMODE_MOVES,
+ X86_TUNE_PARTIAL_REG_DEPENDENCY,
+ X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
+ X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
+ X86_TUNE_SSE_SPLIT_REGS,
+ X86_TUNE_SSE_TYPELESS_STORES,
+ X86_TUNE_SSE_LOAD0_BY_PXOR,
+ X86_TUNE_MEMORY_MISMATCH_STALL,
+ X86_TUNE_PROLOGUE_USING_MOVE,
+ X86_TUNE_EPILOGUE_USING_MOVE,
+ X86_TUNE_SHIFT1,
+ X86_TUNE_USE_FFREEP,
+ X86_TUNE_INTER_UNIT_MOVES,
+ X86_TUNE_FOUR_JUMP_LIMIT,
+ X86_TUNE_SCHEDULE,
+ X86_TUNE_USE_BT,
+ X86_TUNE_USE_INCDEC,
+ X86_TUNE_PAD_RETURNS,
+ X86_TUNE_EXT_80387_CONSTANTS,
+ X86_TUNE_SHORTEN_X87_SSE,
+ X86_TUNE_AVOID_VECTOR_DECODE,
+ X86_TUNE_PROMOTE_HIMODE_IMUL,
+ X86_TUNE_SLOW_IMUL_IMM32_MEM,
+ X86_TUNE_SLOW_IMUL_IMM8,
+ X86_TUNE_MOVE_M1_VIA_OR,
+ X86_TUNE_NOT_UNPAIRABLE,
+ X86_TUNE_NOT_VECTORMODE,
+
+ X86_TUNE_LAST
+};
+
+extern unsigned int ix86_tune_features[X86_TUNE_LAST];
+
+#define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
+#define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
+#define TARGET_ZERO_EXTEND_WITH_AND \
+ ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
+#define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
+#define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
+#define TARGET_DEEP_BRANCH_PREDICTION \
+ ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
+#define TARGET_BRANCH_PREDICTION_HINTS \
+ ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
+#define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
+#define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
+#define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
+#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
+#define TARGET_PARTIAL_FLAG_REG_STALL \
+ ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
+#define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
+#define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
+#define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
+#define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
+#define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
+#define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
+#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
+#define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
+#define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
+#define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
+#define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
+#define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
+#define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
+#define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
+#define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
+#define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
+#define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
+#define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
+#define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
+#define TARGET_INTEGER_DFMODE_MOVES \
+ ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
+#define TARGET_PARTIAL_REG_DEPENDENCY \
+ ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
+#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
+ ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
+#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
+ ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
+#define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
+#define TARGET_SSE_TYPELESS_STORES \
+ ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
+#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
+#define TARGET_MEMORY_MISMATCH_STALL \
+ ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
+#define TARGET_PROLOGUE_USING_MOVE \
+ ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
+#define TARGET_EPILOGUE_USING_MOVE \
+ ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
+#define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
+#define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
+#define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
+#define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
+#define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
+#define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
+#define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
+#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
+#define TARGET_EXT_80387_CONSTANTS \
+ ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
+#define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
+#define TARGET_AVOID_VECTOR_DECODE \
+ ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
+#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
+ ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
+#define TARGET_SLOW_IMUL_IMM32_MEM \
+ ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
+#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
+#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
+#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
+#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
+
+/* Feature tests against the various architecture variations. */
+enum ix86_arch_indices {
+ X86_ARCH_CMOVE, /* || TARGET_SSE */
+ X86_ARCH_CMPXCHG,
+ X86_ARCH_CMPXCHG8B,
+ X86_ARCH_XADD,
+ X86_ARCH_BSWAP,
+
+ X86_ARCH_LAST
+};
+
+extern unsigned int ix86_arch_features[X86_ARCH_LAST];
+
+#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
+#define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
+#define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
+#define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
+#define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
+
+#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
-#define TUNEMASK (1 << ix86_tune)
-extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
-extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
-extern const int x86_branch_hints, x86_unroll_strlen;
-extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
-extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
-extern const int x86_use_cltd, x86_read_modify_write;
-extern const int x86_read_modify, x86_split_long_moves;
-extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
-extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
-extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
-extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
-extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
-extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
-extern const int x86_epilogue_using_move, x86_decompose_lea;
-extern const int x86_arch_always_fancy_math_387, x86_shift1;
-extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
-extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
-extern const int x86_use_ffreep;
-extern const int x86_inter_unit_moves, x86_schedule;
-extern const int x86_use_bt;
extern int x86_prefetch_sse;
-#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
-#define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
-#define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
-#define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
-#define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
-/* For sane SSE instruction set generation we need fcomi instruction. It is
- safe to enable all CMOVE instructions. */
-#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
-#define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
-#define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
-#define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
-#define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
-#define TARGET_MOVX (x86_movx & TUNEMASK)
-#define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
-#define TARGET_USE_LOOP (x86_use_loop & TUNEMASK)
-#define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK)
-#define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
-#define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
-#define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
-#define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
-#define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
-#define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
-#define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
-#define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
-#define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
-#define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
-#define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
-#define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
-#define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
-#define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
-#define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
-#define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
-#define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
-#define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
-#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
- (x86_sse_partial_reg_dependency & TUNEMASK)
-#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
-#define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
-#define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
-#define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
-#define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
-#define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
-#define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
-#define TARGET_PREFETCH_SSE (x86_prefetch_sse)
-#define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
-#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
-#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
-#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
-#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
-#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
-#define TARGET_USE_BT (x86_use_bt & TUNEMASK)
-
-#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
-
-#define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
-#define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
-
-#define ASSEMBLER_DIALECT (ix86_asm_dialect)
-
-#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
-#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
-#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
-#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
-#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
- && (ix86_fpmath & FPMATH_387))
-#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
-#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
-#define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
-
-#define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
-
-#define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
-
-#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
-#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
-
-/* WARNING: Do not mark empty strings for translation, as calling
- gettext on an empty string does NOT return an empty
- string. */
-
-
-#define TARGET_SWITCHES \
-{ { "80387", MASK_80387, N_("Use hardware fp") }, \
- { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
- { "hard-float", MASK_80387, N_("Use hardware fp") }, \
- { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
- { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
- { "386", 0, "" /*Deprecated.*/}, \
- { "486", 0, "" /*Deprecated.*/}, \
- { "pentium", 0, "" /*Deprecated.*/}, \
- { "pentiumpro", 0, "" /*Deprecated.*/}, \
- { "intel-syntax", 0, "" /*Deprecated.*/}, \
- { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
- { "rtd", MASK_RTD, \
- N_("Alternate calling convention") }, \
- { "no-rtd", -MASK_RTD, \
- N_("Use normal calling convention") }, \
- { "align-double", MASK_ALIGN_DOUBLE, \
- N_("Align some doubles on dword boundary") }, \
- { "no-align-double", -MASK_ALIGN_DOUBLE, \
- N_("Align doubles on word boundary") }, \
- { "svr3-shlib", MASK_SVR3_SHLIB, \
- N_("Uninitialized locals in .bss") }, \
- { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
- N_("Uninitialized locals in .data") }, \
- { "ieee-fp", MASK_IEEE_FP, \
- N_("Use IEEE math for fp comparisons") }, \
- { "no-ieee-fp", -MASK_IEEE_FP, \
- N_("Do not use IEEE math for fp comparisons") }, \
- { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
- N_("Return values of functions in FPU registers") }, \
- { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
- N_("Do not return values of functions in FPU registers")}, \
- { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
- N_("Do not generate sin, cos, sqrt for FPU") }, \
- { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
- N_("Generate sin, cos, sqrt for FPU")}, \
- { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
- N_("Omit the frame pointer in leaf functions") }, \
- { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
- { "stack-arg-probe", MASK_STACK_PROBE, \
- N_("Enable stack probing") }, \
- { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
- { "windows", 0, 0 /* undocumented */ }, \
- { "dll", 0, 0 /* undocumented */ }, \
- { "align-stringops", -MASK_NO_ALIGN_STROPS, \
- N_("Align destination of the string operations") }, \
- { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
- N_("Do not align destination of the string operations") }, \
- { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
- N_("Inline all known string operations") }, \
- { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
- N_("Do not inline all known string operations") }, \
- { "push-args", -MASK_NO_PUSH_ARGS, \
- N_("Use push instructions to save outgoing arguments") }, \
- { "no-push-args", MASK_NO_PUSH_ARGS, \
- N_("Do not use push instructions to save outgoing arguments") }, \
- { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
- N_("Use push instructions to save outgoing arguments") }, \
- { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
- N_("Do not use push instructions to save outgoing arguments") }, \
- { "mmx", MASK_MMX, \
- N_("Support MMX built-in functions") }, \
- { "no-mmx", -(MASK_MMX|MASK_3DNOW|MASK_3DNOW_A), \
- N_("Do not support MMX built-in functions") }, \
- { "3dnow", MASK_3DNOW, \
- N_("Support 3DNow! built-in functions") }, \
- { "no-3dnow", -(MASK_3DNOW|MASK_3DNOW_A), \
- N_("Do not support 3DNow! built-in functions") }, \
- { "sse", MASK_SSE, \
- N_("Support MMX and SSE built-in functions and code generation") }, \
- { "no-sse", -(MASK_SSE|MASK_SSE2|MASK_SSE3), \
- N_("Do not support MMX and SSE built-in functions and code generation") },\
- { "sse2", MASK_SSE2, \
- N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
- { "no-sse2", -(MASK_SSE2|MASK_SSE3), \
- N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
- { "sse3", MASK_SSE3, \
- N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
- { "no-sse3", -MASK_SSE3, \
- N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
- { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
- N_("sizeof(long double) is 16") }, \
- { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
- N_("sizeof(long double) is 12") }, \
- { "64", MASK_64BIT, \
- N_("Generate 64bit x86-64 code") }, \
- { "32", -MASK_64BIT, \
- N_("Generate 32bit i386 code") }, \
- { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
- N_("Use native (MS) bitfield layout") }, \
- { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
- N_("Use gcc default bitfield layout") }, \
- { "red-zone", -MASK_NO_RED_ZONE, \
- N_("Use red-zone in the x86-64 code") }, \
- { "no-red-zone", MASK_NO_RED_ZONE, \
- N_("Do not use red-zone in the x86-64 code") }, \
- { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \
- N_("Use direct references against %gs when accessing tls data") }, \
- { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \
- N_("Do not use direct references against %gs when accessing tls data") }, \
- SUBTARGET_SWITCHES \
- { "", \
- TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \
- | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }}
+#define TARGET_ABM x86_abm
+#define TARGET_CMPXCHG16B x86_cmpxchg16b
+#define TARGET_POPCNT x86_popcnt
+#define TARGET_PREFETCH_SSE x86_prefetch_sse
+#define TARGET_SAHF x86_sahf
+#define TARGET_RECIP x86_recip
+
+#define ASSEMBLER_DIALECT (ix86_asm_dialect)
+
+#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
+#define TARGET_MIX_SSE_I387 \
+ ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
+
+#define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
+#define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
+#define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
+#define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
+
+extern int ix86_isa_flags;
#ifndef TARGET_64BIT_DEFAULT
#define TARGET_64BIT_DEFAULT 0
#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
#endif
+/* Fence to use after loop using storent. */
+
+extern tree x86_mfence;
+#define FENCE_FOLLOWING_MOVNT x86_mfence
+
/* Once GDB has been enhanced to deal with functions without frame
pointers, we can change this to allow for elimination of
the frame pointer in leaf functions. */
#define TARGET_DEFAULT 0
+/* Extra bits to force. */
+#define TARGET_SUBTARGET_DEFAULT 0
+#define TARGET_SUBTARGET_ISA_DEFAULT 0
+
+/* Extra bits to force on w/ 32-bit mode. */
+#define TARGET_SUBTARGET32_DEFAULT 0
+#define TARGET_SUBTARGET32_ISA_DEFAULT 0
+
+/* Extra bits to force on w/ 64-bit mode. */
+#define TARGET_SUBTARGET64_DEFAULT 0
+#define TARGET_SUBTARGET64_ISA_DEFAULT 0
+
/* This is not really a target flag, but is done this way so that
it's analogous to similar code for Mach-O on PowerPC. darwin.h
redefines this to 1. */
#define TARGET_MACHO 0
+/* Likewise, for the Windows 64-bit ABI. */
+#define TARGET_64BIT_MS_ABI 0
+
/* Subtargets may reset this to 1 in order to enable 96-bit long double
with the rounding mode forced to 53 bits. */
#define TARGET_96_ROUND_53_LONG_DOUBLE 0
-/* This macro is similar to `TARGET_SWITCHES' but defines names of
- command options that have values. Its definition is an
- initializer with a subgrouping for each command option.
-
- Each subgrouping contains a string constant, that defines the
- fixed part of the option name, and the address of a variable. The
- variable, type `char *', is set to the variable part of the given
- option if the fixed part matches. The actual option name is made
- by appending `-m' to the specified name. */
-#define TARGET_OPTIONS \
-{ { "tune=", &ix86_tune_string, \
- N_("Schedule code for given CPU"), 0}, \
- { "fpmath=", &ix86_fpmath_string, \
- N_("Generate floating point mathematics using given instruction set"), 0},\
- { "arch=", &ix86_arch_string, \
- N_("Generate code for given CPU"), 0}, \
- { "regparm=", &ix86_regparm_string, \
- N_("Number of registers used to pass integer arguments"), 0},\
- { "align-loops=", &ix86_align_loops_string, \
- N_("Loop code aligned to this power of 2"), 0}, \
- { "align-jumps=", &ix86_align_jumps_string, \
- N_("Jump targets are aligned to this power of 2"), 0}, \
- { "align-functions=", &ix86_align_funcs_string, \
- N_("Function starts are aligned to this power of 2"), 0}, \
- { "preferred-stack-boundary=", \
- &ix86_preferred_stack_boundary_string, \
- N_("Attempt to keep stack aligned to this power of 2"), 0}, \
- { "branch-cost=", &ix86_branch_cost_string, \
- N_("Branches are this expensive (1-5, arbitrary units)"), 0},\
- { "cmodel=", &ix86_cmodel_string, \
- N_("Use given x86-64 code model"), 0}, \
- { "debug-arg", &ix86_debug_arg_string, \
- "" /* Undocumented. */, 0}, \
- { "debug-addr", &ix86_debug_addr_string, \
- "" /* Undocumented. */, 0}, \
- { "asm=", &ix86_asm_string, \
- N_("Use given assembler dialect"), 0}, \
- { "tls-dialect=", &ix86_tls_dialect_string, \
- N_("Use given thread-local storage dialect"), 0}, \
- SUBTARGET_OPTIONS \
-}
-
/* Sometimes certain combinations of command options do not make
sense on a particular target machine. You can define a macro
`OVERRIDE_OPTIONS' to take account of this. This macro, if
#define OVERRIDE_OPTIONS override_options ()
-/* These are meant to be redefined in the host dependent files */
-#define SUBTARGET_SWITCHES
-#define SUBTARGET_OPTIONS
-
/* Define this to change the optimizations performed by default. */
#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
optimization_options ((LEVEL), (SIZE))
-/* Support for configure-time defaults of some command line options. */
+/* -march=native handling only makes sense with compiler running on
+ an x86 or x86_64 chip. If changing this condition, also change
+ the condition in driver-i386.c. */
+#if defined(__i386__) || defined(__x86_64__)
+/* In driver-i386.c. */
+extern const char *host_detect_local_cpu (int argc, const char **argv);
+#define EXTRA_SPEC_FUNCTIONS \
+ { "local_cpu_detect", host_detect_local_cpu },
+#define HAVE_LOCAL_CPU_DETECT
+#endif
+
+/* Support for configure-time defaults of some command line options.
+ The order here is important so that -march doesn't squash the
+ tune or cpu values. */
#define OPTION_DEFAULT_SPECS \
- {"arch", "%{!march=*:-march=%(VALUE)}"}, \
{"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
- {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
+ {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
+ {"arch", "%{!march=*:-march=%(VALUE)}"}
/* Specs for the compiler proper */
#ifndef CC1_CPU_SPEC
-#define CC1_CPU_SPEC "\
-%{!mtune*: \
-%{m386:mtune=i386 \
-%n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
-%{m486:-mtune=i486 \
-%n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
-%{mpentium:-mtune=pentium \
-%n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
-%{mpentiumpro:-mtune=pentiumpro \
-%n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
+#define CC1_CPU_SPEC_1 "\
%{mcpu=*:-mtune=%* \
-%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
+%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
%<mcpu=* \
%{mintel-syntax:-masm=intel \
%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
%{mno-intel-syntax:-masm=att \
%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
+
+#ifndef HAVE_LOCAL_CPU_DETECT
+#define CC1_CPU_SPEC CC1_CPU_SPEC_1
+#else
+#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
+"%{march=native:%<march=native %:local_cpu_detect(arch) \
+ %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
+%{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
+#endif
#endif
\f
/* Target CPU builtins. */
size_t arch_len = strlen (ix86_arch_string); \
size_t tune_len = strlen (ix86_tune_string); \
int last_arch_char = ix86_arch_string[arch_len - 1]; \
- int last_tune_char = ix86_tune_string[tune_len - 1]; \
+ int last_tune_char = ix86_tune_string[tune_len - 1]; \
\
if (TARGET_64BIT) \
{ \
break; \
} \
} \
+ else if (TARGET_GEODE) \
+ { \
+ builtin_define ("__tune_geode__"); \
+ } \
else if (TARGET_K6) \
{ \
builtin_define ("__tune_k6__"); \
} \
else if (TARGET_K8) \
builtin_define ("__tune_k8__"); \
+ else if (TARGET_AMDFAM10) \
+ builtin_define ("__tune_amdfam10__"); \
else if (TARGET_PENTIUM4) \
builtin_define ("__tune_pentium4__"); \
else if (TARGET_NOCONA) \
builtin_define ("__tune_nocona__"); \
+ else if (TARGET_CORE2) \
+ builtin_define ("__tune_core2__"); \
\
if (TARGET_MMX) \
builtin_define ("__MMX__"); \
builtin_define ("__SSE2__"); \
if (TARGET_SSE3) \
builtin_define ("__SSE3__"); \
+ if (TARGET_SSSE3) \
+ builtin_define ("__SSSE3__"); \
+ if (TARGET_SSE4_1) \
+ builtin_define ("__SSE4_1__"); \
+ if (TARGET_SSE4_2) \
+ builtin_define ("__SSE4_2__"); \
+ if (TARGET_SSE4A) \
+ builtin_define ("__SSE4A__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \
builtin_define ("__pentiumpro"); \
builtin_define ("__pentiumpro__"); \
} \
+ else if (ix86_arch == PROCESSOR_GEODE) \
+ { \
+ builtin_define ("__geode"); \
+ builtin_define ("__geode__"); \
+ } \
else if (ix86_arch == PROCESSOR_K6) \
{ \
\
builtin_define ("__k8"); \
builtin_define ("__k8__"); \
} \
+ else if (ix86_arch == PROCESSOR_AMDFAM10) \
+ { \
+ builtin_define ("__amdfam10"); \
+ builtin_define ("__amdfam10__"); \
+ } \
else if (ix86_arch == PROCESSOR_PENTIUM4) \
{ \
builtin_define ("__pentium4"); \
builtin_define ("__nocona"); \
builtin_define ("__nocona__"); \
} \
+ else if (ix86_arch == PROCESSOR_CORE2) \
+ { \
+ builtin_define ("__core2"); \
+ builtin_define ("__core2__"); \
+ } \
} \
while (0)
#define TARGET_CPU_DEFAULT_pentium2 5
#define TARGET_CPU_DEFAULT_pentium3 6
#define TARGET_CPU_DEFAULT_pentium4 7
-#define TARGET_CPU_DEFAULT_k6 8
-#define TARGET_CPU_DEFAULT_k6_2 9
-#define TARGET_CPU_DEFAULT_k6_3 10
-#define TARGET_CPU_DEFAULT_athlon 11
-#define TARGET_CPU_DEFAULT_athlon_sse 12
-#define TARGET_CPU_DEFAULT_k8 13
-#define TARGET_CPU_DEFAULT_pentium_m 14
-#define TARGET_CPU_DEFAULT_prescott 15
-#define TARGET_CPU_DEFAULT_nocona 16
+#define TARGET_CPU_DEFAULT_geode 8
+#define TARGET_CPU_DEFAULT_k6 9
+#define TARGET_CPU_DEFAULT_k6_2 10
+#define TARGET_CPU_DEFAULT_k6_3 11
+#define TARGET_CPU_DEFAULT_athlon 12
+#define TARGET_CPU_DEFAULT_athlon_sse 13
+#define TARGET_CPU_DEFAULT_k8 14
+#define TARGET_CPU_DEFAULT_pentium_m 15
+#define TARGET_CPU_DEFAULT_prescott 16
+#define TARGET_CPU_DEFAULT_nocona 17
+#define TARGET_CPU_DEFAULT_core2 18
+#define TARGET_CPU_DEFAULT_generic 19
+#define TARGET_CPU_DEFAULT_amdfam10 20
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \
- "pentium4", "k6", "k6-2", "k6-3",\
+ "pentium4", "geode", "k6", "k6-2", "k6-3", \
"athlon", "athlon-4", "k8", \
- "pentium-m", "prescott", "nocona"}
+ "pentium-m", "prescott", "nocona", \
+ "core2", "generic", "amdfam10"}
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
aligned; the compiler cannot rely on having this alignment. */
#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
-/* As of July 2001, many runtimes to not align the stack properly when
+/* As of July 2001, many runtimes do not align the stack properly when
entering main. This causes expand_main_function to forcibly align
the stack, which results in aligned frames for functions called from
main, though it does nothing for the alignment of main itself. */
#define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
(ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
+/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
+ mandatory for the 64-bit ABI, and may or may not be true for other
+ operating systems. */
+#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
+
/* Minimum allocation boundary for the code of a function. */
#define FUNCTION_BOUNDARY 8
/* Decide whether a variable of mode MODE should be 128 bit aligned. */
#define ALIGN_MODE_128(MODE) \
- ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
+ ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
/* The published ABIs say that doubles should be aligned on word
boundaries, so lower the alignment for structure fields unless
#define STACK_REGS
#define IS_STACK_MODE(MODE) \
- ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
+ (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
+ || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
+ || (MODE) == XFmode)
/* Number of actual hardware registers.
The hardware registers are assigned numbers for the compiler
#define FIXED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-/*arg,flags,fpsr,dir,frame*/ \
- 1, 1, 1, 1, 1, \
+/*arg,flags,fpsr,fpcr,frame*/ \
+ 1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
- The value is zero if the register is not fixed on either 32 or
- 64 bit targets, one if the register if fixed on both 32 and 64
- bit targets, two if it is only fixed on 32bit targets and three
- if its only fixed on 64bit targets.
+ The value is zero if the register is not call used on either 32 or
+ 64 bit targets, one if the register if call used on both 32 and 64
+ bit targets, two if it is only call used on 32bit targets and three
+ if its only call used on 64bit targets.
Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
*/
#define CALL_USED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-/*arg,flags,fpsr,dir,frame*/ \
- 1, 1, 1, 1, 1, \
+/*arg,flags,fpsr,fpcr,frame*/ \
+ 1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
- 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math,
- we want to allocate SSE before x87 registers and vice vera. */
+ we want to allocate SSE before x87 registers and vice versa. */
#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
#define CONDITIONAL_REGISTER_USAGE \
do { \
int i; \
+ unsigned int j; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
{ \
if (fixed_regs[i] > 1) \
call_used_regs[i] = (call_used_regs[i] \
== (TARGET_64BIT ? 3 : 2)); \
} \
- if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
+ j = PIC_OFFSET_TABLE_REGNUM; \
+ if (j != INVALID_REGNUM) \
{ \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
- call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ fixed_regs[j] = 1; \
+ call_used_regs[j] = 1; \
} \
if (! TARGET_MMX) \
{ \
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
- fixed_regs[i] = call_used_regs[i] = 1; \
+ fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
} \
if (! TARGET_SSE) \
{ \
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
- fixed_regs[i] = call_used_regs[i] = 1; \
+ fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
} \
if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
{ \
COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
if (TEST_HARD_REG_BIT (x, i)) \
- fixed_regs[i] = call_used_regs[i] = 1; \
+ fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
+ } \
+ if (! TARGET_64BIT) \
+ { \
+ int i; \
+ for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
+ reg_names[i] = ""; \
+ for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
+ reg_names[i] = ""; \
+ } \
+ if (TARGET_64BIT_MS_ABI) \
+ { \
+ call_used_regs[4 /*RSI*/] = 0; \
+ call_used_regs[5 /*RDI*/] = 0; \
} \
} while (0)
? (TARGET_64BIT ? 4 : 6) \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
+#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
+ ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
+ ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
+ ? 0 \
+ : ((MODE) == XFmode || (MODE) == XCmode)) \
+ : 0)
+
+#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
+
#define VALID_SSE2_REG_MODE(MODE) \
((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
|| (MODE) == V2DImode || (MODE) == DFmode)
/* ??? No autovectorization into MMX or 3DNOW until we can reliably
place emms and femms instructions. */
-#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : 0)
+#define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
|| (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
|| (MODE) == V4SFmode || (MODE) == V4SImode)
-/* Return true for modes passed in MMX registers. */
-#define MMX_REG_MODE_P(MODE) \
- ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
- || (MODE) == V2SFmode)
-
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
- ((MODE1) == (MODE2) \
- || (((MODE1) == HImode || (MODE1) == SImode \
- || ((MODE1) == QImode \
- && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
- || ((MODE1) == DImode && TARGET_64BIT)) \
- && ((MODE2) == HImode || (MODE2) == SImode \
- || ((MODE2) == QImode \
- && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
- || ((MODE2) == DImode && TARGET_64BIT))))
+#define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
/* It is possible to write patterns to move flags; but until someone
does it, */
This is computed in `reload', in reload1.c. */
#define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
-/* Override this in other tm.h files to cope with various OS losage
+/* Override this in other tm.h files to cope with various OS lossage
requiring a frame pointer. */
#ifndef SUBTARGET_FRAME_POINTER_REQUIRED
#define SUBTARGET_FRAME_POINTER_REQUIRED 0
#define REAL_PIC_OFFSET_TABLE_REGNUM 3
#define PIC_OFFSET_TABLE_REGNUM \
- (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
+ ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
+ || !flag_pic ? INVALID_REGNUM \
: reload_completed ? REGNO (pic_offset_table_rtx) \
: REAL_PIC_OFFSET_TABLE_REGNUM)
opcode needs reg %ebx. But some systems pass args to the OS in ebx,
and the "b" register constraint is useful in asms for syscalls.
- The flags and fpsr registers are in no class. */
+ The flags, fpsr and fpcr registers are in no class. */
enum reg_class
{
GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
+ SSE_FIRST_REG,
SSE_REGS,
MMX_REGS,
FP_TOP_SSE_REGS,
#define SSE_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), SSE_REGS)
#define MMX_CLASS_P(CLASS) \
- reg_class_subset_p ((CLASS), MMX_REGS)
+ ((CLASS) == MMX_REGS)
#define MAYBE_INTEGER_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), GENERAL_REGS)
#define MAYBE_FLOAT_CLASS_P(CLASS) \
"GENERAL_REGS", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
+ "SSE_FIRST_REG", \
"SSE_REGS", \
"MMX_REGS", \
"FP_TOP_SSE_REGS", \
{ 0x0f, 0x0 }, /* Q_REGS */ \
{ 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
{ 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
- { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
+ { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
{ 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
{ 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
{ 0xff00, 0x0 }, /* FLOAT_REGS */ \
+ { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
{ 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
{ 0xe0000000, 0x1f }, /* MMX_REGS */ \
{ 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
-{ 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
+{ 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
{ 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
{ 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
{ 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
#define SMALL_REGISTER_CLASSES 1
-#define QI_REG_P(X) \
- (REG_P (X) && REGNO (X) < 4)
+#define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
#define GENERAL_REGNO_P(N) \
- ((N) < 8 || REX_INT_REGNO_P (N))
+ ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
#define GENERAL_REG_P(X) \
(REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
#define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
-#define NON_QI_REG_P(X) \
- (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
-
-#define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
+#define REX_INT_REGNO_P(N) \
+ IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
#define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
-#define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
+#define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
#define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
#define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
-#define SSE_REGNO_P(N) \
- (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
- || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
+#define X87_FLOAT_MODE_P(MODE) \
+ (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
+
+#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
+#define SSE_REGNO_P(N) \
+ (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
+ || REX_SSE_REGNO_P (N))
#define REX_SSE_REGNO_P(N) \
- ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
+ IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
#define SSE_REGNO(N) \
((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
-#define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
#define SSE_FLOAT_MODE_P(MODE) \
((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
-#define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
+#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
-#define STACK_REG_P(XOP) \
- (REG_P (XOP) && \
- REGNO (XOP) >= FIRST_STACK_REG && \
- REGNO (XOP) <= LAST_STACK_REG)
-
-#define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
+#define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
+#define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
#define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
#define INDEX_REG_CLASS INDEX_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Unused letters:
- B TU W
- h jk vw z
-*/
-
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'r' ? GENERAL_REGS : \
- (C) == 'R' ? LEGACY_REGS : \
- (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
- (C) == 'Q' ? Q_REGS : \
- (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FLOAT_REGS \
- : NO_REGS) : \
- (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FP_TOP_REG \
- : NO_REGS) : \
- (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
- ? FP_SECOND_REG \
- : NO_REGS) : \
- (C) == 'a' ? AREG : \
- (C) == 'b' ? BREG : \
- (C) == 'c' ? CREG : \
- (C) == 'd' ? DREG : \
- (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
- (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
- (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
- (C) == 'A' ? AD_REGS : \
- (C) == 'D' ? DIREG : \
- (C) == 'S' ? SIREG : \
- (C) == 'l' ? INDEX_REGS : \
- NO_REGS)
-
-/* The letters I, J, K, L and M in a register constraint string
- can be used to stand for particular ranges of immediate operands.
- This macro defines what the ranges are.
- C is the letter, and VALUE is a constant value.
- Return 1 if VALUE is in the range specified by C.
-
- I is for non-DImode shifts.
- J is for DImode shifts.
- K is for signed imm8 operands.
- L is for andsi as zero-extending move.
- M is for shifts that can be executed by the "lea" opcode.
- N is for immediate operands for out/in instructions (0-255)
- */
-
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
- : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
- : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
- : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
- : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
- : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
- : 0)
-
-/* Similar, but for floating constants, and defining letters G and H.
- Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
- TARGET_387 isn't set, because the stack register converter may need to
- load 0.0 into the function value register. */
-
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'G' ? standard_80387_constant_p (VALUE) \
- : 0)
-
-/* A C expression that defines the optional machine-dependent
- constraint letters that can be used to segregate specific types of
- operands, usually memory references, for the target machine. Any
- letter that is not elsewhere defined and not matched by
- `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
- be defined.
-
- If it is required for a particular target machine, it should
- return 1 if VALUE corresponds to the operand type represented by
- the constraint letter C. If C is not defined as an extra
- constraint, the value returned should be 0 regardless of VALUE. */
-
-#define EXTRA_CONSTRAINT(VALUE, D) \
- ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
- : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
- : (D) == 'C' ? standard_sse_constant_p (VALUE) \
- : 0)
-
/* Place additional restrictions on the register class to use when it
is necessary to be able to hold a value of mode MODE in a reload
register for which class CLASS would ordinarily be used. */
#define PREFERRED_RELOAD_CLASS(X, CLASS) \
ix86_preferred_reload_class ((X), (CLASS))
+/* Discourage putting floating-point values in SSE registers unless
+ SSE math is being used, and likewise for the 387 registers. */
+
+#define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
+ ix86_preferred_output_reload_class ((X), (CLASS))
+
/* If we are copying between general and FP registers, we need a memory
location. The same is true for SSE and MMX registers. */
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
|| ((CLASS) == FP_TOP_REG) \
|| ((CLASS) == FP_SECOND_REG))
-/* Return a class of registers that cannot change FROM mode to TO mode.
-
- x87 registers can't do subreg as all values are reformated to extended
- precision. XMM registers does not support with nonzero offsets equal
- to 4, 8 and 12 otherwise valid for integer registers. Since we can't
- determine these, prohibit all nonparadoxical subregs changing size. */
+/* Return a class of registers that cannot change FROM mode to TO mode. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \
- ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \
- || MAYBE_MMX_CLASS_P (CLASS) \
- : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
- ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ ix86_cannot_change_mode_class (FROM, TO, CLASS)
\f
/* Stack layout; function entry, exit and calling. */
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
-/* Define this if the nominal address of the stack frame
+/* Define this to nonzero if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
goes at a more negative offset in the frame. */
-#define FRAME_GROWS_DOWNWARD
+#define FRAME_GROWS_DOWNWARD 1
/* Offset within stack frame to start allocating local variables at.
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
/* If we generate an insn to push BYTES bytes,
this says how many the stack pointer really advances by.
- On 386 pushw decrements by exactly 2 no matter what the position was.
- On the 386 there is no pushb; we use pushw instead, and this
- has the effect of rounding up to 2.
+ On 386, we have pushw instruction that decrements by exactly 2 no
+ matter what the position was, there is no pushb.
+ But as CIE data alignment factor on this arch is -4, we need to make
+ sure all stack pointer adjustments are in multiple of 4.
For 64bit ABI we round up to 8 bytes.
*/
#define PUSH_ROUNDING(BYTES) \
(TARGET_64BIT \
? (((BYTES) + 7) & (-8)) \
- : (((BYTES) + 1) & (-2)))
+ : (((BYTES) + 3) & (-4)))
/* If defined, the maximum amount of space required for outgoing arguments will
be computed and placed into the variable
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
-/* Define how to find the value returned by a function.
- VALTYPE is the data type of the value (as a tree).
- If the precise function being called is known, FUNC is its FUNCTION_DECL;
- otherwise, FUNC is 0. */
-#define FUNCTION_VALUE(VALTYPE, FUNC) \
- ix86_function_value (VALTYPE)
-
#define FUNCTION_VALUE_REGNO_P(N) \
ix86_function_value_regno_p (N)
int words; /* # words passed so far */
int nregs; /* # registers available for passing */
int regno; /* next available register number */
- int fastcall; /* fastcall calling convention is used */
+ int fastcall; /* fastcall calling convention is used */
int sse_words; /* # sse words passed so far */
int sse_nregs; /* # sse registers available for passing */
int warn_sse; /* True when we want to warn about SSE ABI. */
int mmx_nregs; /* # mmx registers available for passing */
int mmx_regno; /* next available mmx register number */
int maybe_vaarg; /* true for calls to possibly vardic fncts. */
+ int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
+ be passed in SSE registers. Otherwise 0. */
} CUMULATIVE_ARGS;
/* Initialize a variable CUM of type CUMULATIVE_ARGS
#define REGNO_OK_FOR_INDEX_P(REGNO) \
((REGNO) < STACK_POINTER_REGNUM \
- || (REGNO >= FIRST_REX_INT_REG \
- && (REGNO) <= LAST_REX_INT_REG) \
- || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
- && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
- || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
+ || REX_INT_REGNO_P (REGNO) \
+ || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
+ || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
#define REGNO_OK_FOR_BASE_P(REGNO) \
- ((REGNO) <= STACK_POINTER_REGNUM \
+ (GENERAL_REGNO_P (REGNO) \
|| (REGNO) == ARG_POINTER_REGNUM \
|| (REGNO) == FRAME_POINTER_REGNUM \
- || (REGNO >= FIRST_REX_INT_REG \
- && (REGNO) <= LAST_REX_INT_REG) \
- || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
- && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
- || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
-
-#define REGNO_OK_FOR_SIREG_P(REGNO) \
- ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
-#define REGNO_OK_FOR_DIREG_P(REGNO) \
- ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
+ || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
/* Non strict versions, pseudos are ok. */
#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
(REGNO (X) < STACK_POINTER_REGNUM \
- || (REGNO (X) >= FIRST_REX_INT_REG \
- && REGNO (X) <= LAST_REX_INT_REG) \
+ || REX_INT_REGNO_P (REGNO (X)) \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
#define REG_OK_FOR_BASE_NONSTRICT_P(X) \
- (REGNO (X) <= STACK_POINTER_REGNUM \
+ (GENERAL_REGNO_P (REGNO (X)) \
|| REGNO (X) == ARG_POINTER_REGNUM \
|| REGNO (X) == FRAME_POINTER_REGNUM \
- || (REGNO (X) >= FIRST_REX_INT_REG \
- && REGNO (X) <= LAST_REX_INT_REG) \
|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
/* Strict versions, hard registers only */
goto WIN; \
} while (0)
-#define REWRITE_ADDRESS(X) rewrite_address (X)
-
/* Nonzero if the constant value X is a legitimate general operand
when generating PIC code. It is given that flag_pic is on and
that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
/* Go to LABEL if ADDR (a legitimate address expression)
has an effect that depends on the machine mode it is used for.
On the 80386, only postdecrement and postincrement address depend thus
- (the amount of decrement or increment being the length of the operand). */
-#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
-do { \
- if (GET_CODE (ADDR) == POST_INC \
- || GET_CODE (ADDR) == POST_DEC) \
- goto LABEL; \
-} while (0)
-\f
-/* Codes for all the SSE/MMX builtins. */
-enum ix86_builtins
-{
- IX86_BUILTIN_ADDPS,
- IX86_BUILTIN_ADDSS,
- IX86_BUILTIN_DIVPS,
- IX86_BUILTIN_DIVSS,
- IX86_BUILTIN_MULPS,
- IX86_BUILTIN_MULSS,
- IX86_BUILTIN_SUBPS,
- IX86_BUILTIN_SUBSS,
-
- IX86_BUILTIN_CMPEQPS,
- IX86_BUILTIN_CMPLTPS,
- IX86_BUILTIN_CMPLEPS,
- IX86_BUILTIN_CMPGTPS,
- IX86_BUILTIN_CMPGEPS,
- IX86_BUILTIN_CMPNEQPS,
- IX86_BUILTIN_CMPNLTPS,
- IX86_BUILTIN_CMPNLEPS,
- IX86_BUILTIN_CMPNGTPS,
- IX86_BUILTIN_CMPNGEPS,
- IX86_BUILTIN_CMPORDPS,
- IX86_BUILTIN_CMPUNORDPS,
- IX86_BUILTIN_CMPNEPS,
- IX86_BUILTIN_CMPEQSS,
- IX86_BUILTIN_CMPLTSS,
- IX86_BUILTIN_CMPLESS,
- IX86_BUILTIN_CMPNEQSS,
- IX86_BUILTIN_CMPNLTSS,
- IX86_BUILTIN_CMPNLESS,
- IX86_BUILTIN_CMPORDSS,
- IX86_BUILTIN_CMPUNORDSS,
- IX86_BUILTIN_CMPNESS,
-
- IX86_BUILTIN_COMIEQSS,
- IX86_BUILTIN_COMILTSS,
- IX86_BUILTIN_COMILESS,
- IX86_BUILTIN_COMIGTSS,
- IX86_BUILTIN_COMIGESS,
- IX86_BUILTIN_COMINEQSS,
- IX86_BUILTIN_UCOMIEQSS,
- IX86_BUILTIN_UCOMILTSS,
- IX86_BUILTIN_UCOMILESS,
- IX86_BUILTIN_UCOMIGTSS,
- IX86_BUILTIN_UCOMIGESS,
- IX86_BUILTIN_UCOMINEQSS,
-
- IX86_BUILTIN_CVTPI2PS,
- IX86_BUILTIN_CVTPS2PI,
- IX86_BUILTIN_CVTSI2SS,
- IX86_BUILTIN_CVTSI642SS,
- IX86_BUILTIN_CVTSS2SI,
- IX86_BUILTIN_CVTSS2SI64,
- IX86_BUILTIN_CVTTPS2PI,
- IX86_BUILTIN_CVTTSS2SI,
- IX86_BUILTIN_CVTTSS2SI64,
-
- IX86_BUILTIN_MAXPS,
- IX86_BUILTIN_MAXSS,
- IX86_BUILTIN_MINPS,
- IX86_BUILTIN_MINSS,
-
- IX86_BUILTIN_LOADAPS,
- IX86_BUILTIN_LOADUPS,
- IX86_BUILTIN_STOREAPS,
- IX86_BUILTIN_STOREUPS,
- IX86_BUILTIN_LOADSS,
- IX86_BUILTIN_STORESS,
- IX86_BUILTIN_MOVSS,
-
- IX86_BUILTIN_MOVHLPS,
- IX86_BUILTIN_MOVLHPS,
- IX86_BUILTIN_LOADHPS,
- IX86_BUILTIN_LOADLPS,
- IX86_BUILTIN_STOREHPS,
- IX86_BUILTIN_STORELPS,
-
- IX86_BUILTIN_MASKMOVQ,
- IX86_BUILTIN_MOVMSKPS,
- IX86_BUILTIN_PMOVMSKB,
-
- IX86_BUILTIN_MOVNTPS,
- IX86_BUILTIN_MOVNTQ,
-
- IX86_BUILTIN_LOADDQA,
- IX86_BUILTIN_LOADDQU,
- IX86_BUILTIN_STOREDQA,
- IX86_BUILTIN_STOREDQU,
- IX86_BUILTIN_MOVQ,
- IX86_BUILTIN_LOADD,
- IX86_BUILTIN_STORED,
-
- IX86_BUILTIN_CLRTI,
-
- IX86_BUILTIN_PACKSSWB,
- IX86_BUILTIN_PACKSSDW,
- IX86_BUILTIN_PACKUSWB,
-
- IX86_BUILTIN_PADDB,
- IX86_BUILTIN_PADDW,
- IX86_BUILTIN_PADDD,
- IX86_BUILTIN_PADDQ,
- IX86_BUILTIN_PADDSB,
- IX86_BUILTIN_PADDSW,
- IX86_BUILTIN_PADDUSB,
- IX86_BUILTIN_PADDUSW,
- IX86_BUILTIN_PSUBB,
- IX86_BUILTIN_PSUBW,
- IX86_BUILTIN_PSUBD,
- IX86_BUILTIN_PSUBQ,
- IX86_BUILTIN_PSUBSB,
- IX86_BUILTIN_PSUBSW,
- IX86_BUILTIN_PSUBUSB,
- IX86_BUILTIN_PSUBUSW,
-
- IX86_BUILTIN_PAND,
- IX86_BUILTIN_PANDN,
- IX86_BUILTIN_POR,
- IX86_BUILTIN_PXOR,
-
- IX86_BUILTIN_PAVGB,
- IX86_BUILTIN_PAVGW,
-
- IX86_BUILTIN_PCMPEQB,
- IX86_BUILTIN_PCMPEQW,
- IX86_BUILTIN_PCMPEQD,
- IX86_BUILTIN_PCMPGTB,
- IX86_BUILTIN_PCMPGTW,
- IX86_BUILTIN_PCMPGTD,
-
- IX86_BUILTIN_PEXTRW,
- IX86_BUILTIN_PINSRW,
-
- IX86_BUILTIN_PMADDWD,
-
- IX86_BUILTIN_PMAXSW,
- IX86_BUILTIN_PMAXUB,
- IX86_BUILTIN_PMINSW,
- IX86_BUILTIN_PMINUB,
-
- IX86_BUILTIN_PMULHUW,
- IX86_BUILTIN_PMULHW,
- IX86_BUILTIN_PMULLW,
-
- IX86_BUILTIN_PSADBW,
- IX86_BUILTIN_PSHUFW,
-
- IX86_BUILTIN_PSLLW,
- IX86_BUILTIN_PSLLD,
- IX86_BUILTIN_PSLLQ,
- IX86_BUILTIN_PSRAW,
- IX86_BUILTIN_PSRAD,
- IX86_BUILTIN_PSRLW,
- IX86_BUILTIN_PSRLD,
- IX86_BUILTIN_PSRLQ,
- IX86_BUILTIN_PSLLWI,
- IX86_BUILTIN_PSLLDI,
- IX86_BUILTIN_PSLLQI,
- IX86_BUILTIN_PSRAWI,
- IX86_BUILTIN_PSRADI,
- IX86_BUILTIN_PSRLWI,
- IX86_BUILTIN_PSRLDI,
- IX86_BUILTIN_PSRLQI,
-
- IX86_BUILTIN_PUNPCKHBW,
- IX86_BUILTIN_PUNPCKHWD,
- IX86_BUILTIN_PUNPCKHDQ,
- IX86_BUILTIN_PUNPCKLBW,
- IX86_BUILTIN_PUNPCKLWD,
- IX86_BUILTIN_PUNPCKLDQ,
-
- IX86_BUILTIN_SHUFPS,
-
- IX86_BUILTIN_RCPPS,
- IX86_BUILTIN_RCPSS,
- IX86_BUILTIN_RSQRTPS,
- IX86_BUILTIN_RSQRTSS,
- IX86_BUILTIN_SQRTPS,
- IX86_BUILTIN_SQRTSS,
-
- IX86_BUILTIN_UNPCKHPS,
- IX86_BUILTIN_UNPCKLPS,
-
- IX86_BUILTIN_ANDPS,
- IX86_BUILTIN_ANDNPS,
- IX86_BUILTIN_ORPS,
- IX86_BUILTIN_XORPS,
-
- IX86_BUILTIN_EMMS,
- IX86_BUILTIN_LDMXCSR,
- IX86_BUILTIN_STMXCSR,
- IX86_BUILTIN_SFENCE,
-
- /* 3DNow! Original */
- IX86_BUILTIN_FEMMS,
- IX86_BUILTIN_PAVGUSB,
- IX86_BUILTIN_PF2ID,
- IX86_BUILTIN_PFACC,
- IX86_BUILTIN_PFADD,
- IX86_BUILTIN_PFCMPEQ,
- IX86_BUILTIN_PFCMPGE,
- IX86_BUILTIN_PFCMPGT,
- IX86_BUILTIN_PFMAX,
- IX86_BUILTIN_PFMIN,
- IX86_BUILTIN_PFMUL,
- IX86_BUILTIN_PFRCP,
- IX86_BUILTIN_PFRCPIT1,
- IX86_BUILTIN_PFRCPIT2,
- IX86_BUILTIN_PFRSQIT1,
- IX86_BUILTIN_PFRSQRT,
- IX86_BUILTIN_PFSUB,
- IX86_BUILTIN_PFSUBR,
- IX86_BUILTIN_PI2FD,
- IX86_BUILTIN_PMULHRW,
-
- /* 3DNow! Athlon Extensions */
- IX86_BUILTIN_PF2IW,
- IX86_BUILTIN_PFNACC,
- IX86_BUILTIN_PFPNACC,
- IX86_BUILTIN_PI2FW,
- IX86_BUILTIN_PSWAPDSI,
- IX86_BUILTIN_PSWAPDSF,
-
- IX86_BUILTIN_SSE_ZERO,
- IX86_BUILTIN_MMX_ZERO,
-
- /* SSE2 */
- IX86_BUILTIN_ADDPD,
- IX86_BUILTIN_ADDSD,
- IX86_BUILTIN_DIVPD,
- IX86_BUILTIN_DIVSD,
- IX86_BUILTIN_MULPD,
- IX86_BUILTIN_MULSD,
- IX86_BUILTIN_SUBPD,
- IX86_BUILTIN_SUBSD,
-
- IX86_BUILTIN_CMPEQPD,
- IX86_BUILTIN_CMPLTPD,
- IX86_BUILTIN_CMPLEPD,
- IX86_BUILTIN_CMPGTPD,
- IX86_BUILTIN_CMPGEPD,
- IX86_BUILTIN_CMPNEQPD,
- IX86_BUILTIN_CMPNLTPD,
- IX86_BUILTIN_CMPNLEPD,
- IX86_BUILTIN_CMPNGTPD,
- IX86_BUILTIN_CMPNGEPD,
- IX86_BUILTIN_CMPORDPD,
- IX86_BUILTIN_CMPUNORDPD,
- IX86_BUILTIN_CMPNEPD,
- IX86_BUILTIN_CMPEQSD,
- IX86_BUILTIN_CMPLTSD,
- IX86_BUILTIN_CMPLESD,
- IX86_BUILTIN_CMPNEQSD,
- IX86_BUILTIN_CMPNLTSD,
- IX86_BUILTIN_CMPNLESD,
- IX86_BUILTIN_CMPORDSD,
- IX86_BUILTIN_CMPUNORDSD,
- IX86_BUILTIN_CMPNESD,
-
- IX86_BUILTIN_COMIEQSD,
- IX86_BUILTIN_COMILTSD,
- IX86_BUILTIN_COMILESD,
- IX86_BUILTIN_COMIGTSD,
- IX86_BUILTIN_COMIGESD,
- IX86_BUILTIN_COMINEQSD,
- IX86_BUILTIN_UCOMIEQSD,
- IX86_BUILTIN_UCOMILTSD,
- IX86_BUILTIN_UCOMILESD,
- IX86_BUILTIN_UCOMIGTSD,
- IX86_BUILTIN_UCOMIGESD,
- IX86_BUILTIN_UCOMINEQSD,
-
- IX86_BUILTIN_MAXPD,
- IX86_BUILTIN_MAXSD,
- IX86_BUILTIN_MINPD,
- IX86_BUILTIN_MINSD,
-
- IX86_BUILTIN_ANDPD,
- IX86_BUILTIN_ANDNPD,
- IX86_BUILTIN_ORPD,
- IX86_BUILTIN_XORPD,
-
- IX86_BUILTIN_SQRTPD,
- IX86_BUILTIN_SQRTSD,
-
- IX86_BUILTIN_UNPCKHPD,
- IX86_BUILTIN_UNPCKLPD,
-
- IX86_BUILTIN_SHUFPD,
-
- IX86_BUILTIN_LOADAPD,
- IX86_BUILTIN_LOADUPD,
- IX86_BUILTIN_STOREAPD,
- IX86_BUILTIN_STOREUPD,
- IX86_BUILTIN_LOADSD,
- IX86_BUILTIN_STORESD,
- IX86_BUILTIN_MOVSD,
-
- IX86_BUILTIN_LOADHPD,
- IX86_BUILTIN_LOADLPD,
- IX86_BUILTIN_STOREHPD,
- IX86_BUILTIN_STORELPD,
-
- IX86_BUILTIN_CVTDQ2PD,
- IX86_BUILTIN_CVTDQ2PS,
-
- IX86_BUILTIN_CVTPD2DQ,
- IX86_BUILTIN_CVTPD2PI,
- IX86_BUILTIN_CVTPD2PS,
- IX86_BUILTIN_CVTTPD2DQ,
- IX86_BUILTIN_CVTTPD2PI,
-
- IX86_BUILTIN_CVTPI2PD,
- IX86_BUILTIN_CVTSI2SD,
- IX86_BUILTIN_CVTSI642SD,
-
- IX86_BUILTIN_CVTSD2SI,
- IX86_BUILTIN_CVTSD2SI64,
- IX86_BUILTIN_CVTSD2SS,
- IX86_BUILTIN_CVTSS2SD,
- IX86_BUILTIN_CVTTSD2SI,
- IX86_BUILTIN_CVTTSD2SI64,
-
- IX86_BUILTIN_CVTPS2DQ,
- IX86_BUILTIN_CVTPS2PD,
- IX86_BUILTIN_CVTTPS2DQ,
-
- IX86_BUILTIN_MOVNTI,
- IX86_BUILTIN_MOVNTPD,
- IX86_BUILTIN_MOVNTDQ,
-
- IX86_BUILTIN_SETPD1,
- IX86_BUILTIN_SETPD,
- IX86_BUILTIN_CLRPD,
- IX86_BUILTIN_SETRPD,
- IX86_BUILTIN_LOADPD1,
- IX86_BUILTIN_LOADRPD,
- IX86_BUILTIN_STOREPD1,
- IX86_BUILTIN_STORERPD,
-
- /* SSE2 MMX */
- IX86_BUILTIN_MASKMOVDQU,
- IX86_BUILTIN_MOVMSKPD,
- IX86_BUILTIN_PMOVMSKB128,
- IX86_BUILTIN_MOVQ2DQ,
- IX86_BUILTIN_MOVDQ2Q,
-
- IX86_BUILTIN_PACKSSWB128,
- IX86_BUILTIN_PACKSSDW128,
- IX86_BUILTIN_PACKUSWB128,
-
- IX86_BUILTIN_PADDB128,
- IX86_BUILTIN_PADDW128,
- IX86_BUILTIN_PADDD128,
- IX86_BUILTIN_PADDQ128,
- IX86_BUILTIN_PADDSB128,
- IX86_BUILTIN_PADDSW128,
- IX86_BUILTIN_PADDUSB128,
- IX86_BUILTIN_PADDUSW128,
- IX86_BUILTIN_PSUBB128,
- IX86_BUILTIN_PSUBW128,
- IX86_BUILTIN_PSUBD128,
- IX86_BUILTIN_PSUBQ128,
- IX86_BUILTIN_PSUBSB128,
- IX86_BUILTIN_PSUBSW128,
- IX86_BUILTIN_PSUBUSB128,
- IX86_BUILTIN_PSUBUSW128,
-
- IX86_BUILTIN_PAND128,
- IX86_BUILTIN_PANDN128,
- IX86_BUILTIN_POR128,
- IX86_BUILTIN_PXOR128,
-
- IX86_BUILTIN_PAVGB128,
- IX86_BUILTIN_PAVGW128,
-
- IX86_BUILTIN_PCMPEQB128,
- IX86_BUILTIN_PCMPEQW128,
- IX86_BUILTIN_PCMPEQD128,
- IX86_BUILTIN_PCMPGTB128,
- IX86_BUILTIN_PCMPGTW128,
- IX86_BUILTIN_PCMPGTD128,
-
- IX86_BUILTIN_PEXTRW128,
- IX86_BUILTIN_PINSRW128,
-
- IX86_BUILTIN_PMADDWD128,
-
- IX86_BUILTIN_PMAXSW128,
- IX86_BUILTIN_PMAXUB128,
- IX86_BUILTIN_PMINSW128,
- IX86_BUILTIN_PMINUB128,
-
- IX86_BUILTIN_PMULUDQ,
- IX86_BUILTIN_PMULUDQ128,
- IX86_BUILTIN_PMULHUW128,
- IX86_BUILTIN_PMULHW128,
- IX86_BUILTIN_PMULLW128,
-
- IX86_BUILTIN_PSADBW128,
- IX86_BUILTIN_PSHUFHW,
- IX86_BUILTIN_PSHUFLW,
- IX86_BUILTIN_PSHUFD,
-
- IX86_BUILTIN_PSLLW128,
- IX86_BUILTIN_PSLLD128,
- IX86_BUILTIN_PSLLQ128,
- IX86_BUILTIN_PSRAW128,
- IX86_BUILTIN_PSRAD128,
- IX86_BUILTIN_PSRLW128,
- IX86_BUILTIN_PSRLD128,
- IX86_BUILTIN_PSRLQ128,
- IX86_BUILTIN_PSLLDQI128,
- IX86_BUILTIN_PSLLWI128,
- IX86_BUILTIN_PSLLDI128,
- IX86_BUILTIN_PSLLQI128,
- IX86_BUILTIN_PSRAWI128,
- IX86_BUILTIN_PSRADI128,
- IX86_BUILTIN_PSRLDQI128,
- IX86_BUILTIN_PSRLWI128,
- IX86_BUILTIN_PSRLDI128,
- IX86_BUILTIN_PSRLQI128,
-
- IX86_BUILTIN_PUNPCKHBW128,
- IX86_BUILTIN_PUNPCKHWD128,
- IX86_BUILTIN_PUNPCKHDQ128,
- IX86_BUILTIN_PUNPCKHQDQ128,
- IX86_BUILTIN_PUNPCKLBW128,
- IX86_BUILTIN_PUNPCKLWD128,
- IX86_BUILTIN_PUNPCKLDQ128,
- IX86_BUILTIN_PUNPCKLQDQ128,
-
- IX86_BUILTIN_CLFLUSH,
- IX86_BUILTIN_MFENCE,
- IX86_BUILTIN_LFENCE,
-
- /* Prescott New Instructions. */
- IX86_BUILTIN_ADDSUBPS,
- IX86_BUILTIN_HADDPS,
- IX86_BUILTIN_HSUBPS,
- IX86_BUILTIN_MOVSHDUP,
- IX86_BUILTIN_MOVSLDUP,
- IX86_BUILTIN_ADDSUBPD,
- IX86_BUILTIN_HADDPD,
- IX86_BUILTIN_HSUBPD,
- IX86_BUILTIN_LOADDDUP,
- IX86_BUILTIN_MOVDDUP,
- IX86_BUILTIN_LDDQU,
-
- IX86_BUILTIN_MONITOR,
- IX86_BUILTIN_MWAIT,
-
- IX86_BUILTIN_MAX
-};
+ (the amount of decrement or increment being the length of the operand).
+ These are now caught in recog.c. */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
\f
/* Max number of args passed in registers. If this is more than 3, we will
have problems with ebx (register #4), since it is a caller save register and
\f
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
-#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
+#define CASE_VECTOR_MODE \
+ (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
-/* Number of bytes moved into a data cache for a single prefetch operation. */
-#define PREFETCH_BLOCK ix86_cost->prefetch_block
-
-/* Number of prefetch operations that can be done in parallel. */
-#define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
-
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
#define MOVE_MAX 16
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
-/* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
+/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
For non floating point regs, the following are the HImode names.
For float regs, the stack top is sometimes referred to as "%st(0)"
#define HI_REGISTER_NAMES \
{"ax","dx","cx","bx","si","di","bp","sp", \
"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
- "argp", "flags", "fpsr", "dirflag", "frame", \
+ "argp", "flags", "fpsr", "fpcr", "frame", \
"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
- "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
+ "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
{ "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
{ "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
{ "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
- { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
- { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
- { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
+ { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
/* Note we are omitting these since currently I don't know how
to get gcc to use these, since they want the same but different
Whether or not a particular assembler allows us to enter such, I
guess we'll have to see. */
#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
- (flag_pic \
- ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
- : DW_EH_PE_absptr)
+ asm_preferred_eh_data_format ((CODE), (GLOBAL))
/* This is how to output an insn to push a register on the stack.
It need not be very fast code. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
-/* Under some conditions we need jump tables in the text section, because
- the assembler cannot handle label differences between sections. */
+/* Under some conditions we need jump tables in the text section,
+ because the assembler cannot handle label differences between
+ sections. This is the case for x86_64 on Mach-O for example. */
#define JUMP_TABLES_IN_TEXT_SECTION \
- (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
-
-/* Emit a dtp-relative reference to a TLS variable. */
-
-#ifdef HAVE_AS_TLS
-#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
- i386_output_dwarf_dtprel (FILE, SIZE, X)
-#endif
+ (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
+ || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
/* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
and switch back. For x86 we do this only to save a few bytes that
if (! output_addr_const_extra (FILE, (X))) \
goto FAIL; \
} while (0);
-
-/* a letter which is not needed by the normal asm syntax, which
- we can use for operand syntax in the extended asm */
-
-#define ASM_OPERAND_LETTER '#'
-#define RET return ""
-#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
\f
/* Which processor to schedule for. The cpu attribute defines a list that
mirrors this list, so changes to i386.md must be made at the same time. */
PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
PROCESSOR_PENTIUM,
PROCESSOR_PENTIUMPRO,
+ PROCESSOR_GEODE,
PROCESSOR_K6,
PROCESSOR_ATHLON,
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
PROCESSOR_NOCONA,
+ PROCESSOR_CORE2,
+ PROCESSOR_GENERIC32,
+ PROCESSOR_GENERIC64,
+ PROCESSOR_AMDFAM10,
PROCESSOR_max
};
extern enum processor_type ix86_tune;
-extern const char *ix86_tune_string;
-
extern enum processor_type ix86_arch;
-extern const char *ix86_arch_string;
enum fpmath_unit
{
};
extern enum fpmath_unit ix86_fpmath;
-extern const char *ix86_fpmath_string;
enum tls_dialect
{
TLS_DIALECT_GNU,
+ TLS_DIALECT_GNU2,
TLS_DIALECT_SUN
};
extern enum tls_dialect ix86_tls_dialect;
-extern const char *ix86_tls_dialect_string;
enum cmodel {
CM_32, /* The traditional 32-bit ABI. */
CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
CM_LARGE, /* No assumptions. */
- CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
+ CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
+ CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
+ CM_LARGE_PIC /* No assumptions. */
};
extern enum cmodel ix86_cmodel;
-extern const char *ix86_cmodel_string;
/* Size of the RED_ZONE area. */
#define RED_ZONE_SIZE 128
ASM_INTEL
};
-extern const char *ix86_asm_string;
extern enum asm_dialect ix86_asm_dialect;
-
-extern int ix86_regparm;
-extern const char *ix86_regparm_string;
-
extern unsigned int ix86_preferred_stack_boundary;
-extern const char *ix86_preferred_stack_boundary_string;
-
-extern int ix86_branch_cost;
-extern const char *ix86_branch_cost_string;
-
-extern const char *ix86_debug_arg_string;
-extern const char *ix86_debug_addr_string;
-
-/* Obsoleted by -f options. Remove before 3.2 ships. */
-extern const char *ix86_align_loops_string;
-extern const char *ix86_align_jumps_string;
-extern const char *ix86_align_funcs_string;
+extern int ix86_branch_cost, ix86_section_threshold;
/* Smallest class containing REGNO. */
extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
extern rtx ix86_compare_op0; /* operand 0 for comparisons */
extern rtx ix86_compare_op1; /* operand 1 for comparisons */
+extern rtx ix86_compare_emitted;
\f
/* To properly truncate FP values into integers, we need to set i387 control
word. We can't emit proper mode switching code before reload, as spills
Post-reload pass may be later used to eliminate the redundant fildcw if
needed. */
+enum ix86_entity
+{
+ I387_TRUNC = 0,
+ I387_FLOOR,
+ I387_CEIL,
+ I387_MASK_PM,
+ MAX_386_ENTITIES
+};
+
+enum ix86_stack_slot
+{
+ SLOT_TEMP = 0,
+ SLOT_CW_STORED,
+ SLOT_CW_TRUNC,
+ SLOT_CW_FLOOR,
+ SLOT_CW_CEIL,
+ SLOT_CW_MASK_PM,
+ MAX_386_STACK_LOCALS
+};
/* Define this macro if the port needs extra instructions inserted
for mode switching in an optimizing compilation. */
-#define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching
+#define OPTIMIZE_MODE_SWITCHING(ENTITY) \
+ ix86_optimize_mode_switching[(ENTITY)]
/* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
initializer for an array of integers. Each initializer element N
starting counting at zero - determines the integer that is used to
refer to the mode-switched entity in question. */
-#define NUM_MODES_FOR_MODE_SWITCHING { I387_CW_ANY }
+#define NUM_MODES_FOR_MODE_SWITCHING \
+ { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
/* ENTITY is an integer specifying a mode-switched entity. If
`OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
return an integer value not larger than the corresponding element
in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
- must be switched into prior to the execution of INSN.
-
- The mode UNINITIALIZED is used to force re-load of possibly previously
- stored control word after function call. The mode ANY specify that
- function has no requirements on the control word and make no changes
- in the bits we are interested in. */
-
-#define MODE_NEEDED(ENTITY, I) \
- (GET_CODE (I) == CALL_INSN \
- || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
- || GET_CODE (PATTERN (I)) == ASM_INPUT))\
- ? I387_CW_UNINITIALIZED \
- : recog_memoized (I) < 0 \
- ? I387_CW_ANY \
- : get_attr_i387_cw (I))
+ must be switched into prior to the execution of INSN. */
+
+#define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
/* This macro specifies the order in which modes for ENTITY are
processed. 0 is the highest priority. */
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
- ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
- assign_386_stack_local (HImode, 2), \
- MODE), 0 \
+ ? emit_i387_cw_initialization (MODE), 0 \
: 0)
+
\f
/* Avoid renaming of stack registers, as doing so in combination with
scheduling just increases amount of live registers at time and in
??? Maybe Pentium chips benefits from renaming, someone can try.... */
#define HARD_REGNO_RENAME_OK(SRC, TARGET) \
- ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
+ (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
\f
-#define DLL_IMPORT_EXPORT_PREFIX '#'
-
#define FASTCALL_PREFIX '@'
\f
struct machine_function GTY(())
{
struct stack_local_entry *stack_locals;
const char *some_ld_name;
+ rtx force_align_arg_pointer;
int save_varrargs_registers;
int accesses_prev_frame;
- int optimize_mode_switching;
+ int optimize_mode_switching[MAX_386_ENTITIES];
/* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
determine the style used. */
int use_fast_prologue_epilogue;
/* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
for. */
int use_fast_prologue_epilogue_nregs;
+ /* If true, the current function needs the default PIC register, not
+ an alternate register (on x86) and must not use the red zone (on
+ x86_64), even if it's a leaf function. We don't want the
+ function to be regarded as non-leaf because TLS calls need not
+ affect register allocation. This flag is set when a TLS call
+ instruction is expanded within a function, and never reset, even
+ if all such instructions are optimized away. Use the
+ ix86_current_function_calls_tls_descriptor macro for a better
+ approximation. */
+ int tls_descriptor_call_expanded_p;
};
#define ix86_stack_locals (cfun->machine->stack_locals)
#define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
#define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
+#define ix86_tls_descriptor_calls_expanded_in_cfun \
+ (cfun->machine->tls_descriptor_call_expanded_p)
+/* Since tls_descriptor_call_expanded is not cleared, even if all TLS
+ calls are optimized away, we try to detect cases in which it was
+ optimized away. Since such instructions (use (reg REG_SP)), we can
+ verify whether there's any such instruction live by testing that
+ REG_SP is live. */
+#define ix86_current_function_calls_tls_descriptor \
+ (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
/* Control behavior of x86_file_start. */
#define X86_FILE_START_VERSION_DIRECTIVE false
#define X86_FILE_START_FLTUSED false
+/* Flag to mark data that is in the large address area. */
+#define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
+#define SYMBOL_REF_FAR_ADDR_P(X) \
+ ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
+
+/* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
+ have defined always, to avoid ifdefing. */
+#define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
+#define SYMBOL_REF_DLLIMPORT_P(X) \
+ ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
+
+#define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
+#define SYMBOL_REF_DLLEXPORT_P(X) \
+ ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
+
/*
Local variables:
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