PR middle-end/31723

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.h

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 21ed8ad..ee1fbbc 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -35,6 +35,20 @@ Boston, MA 02110-1301, USA.  */
    ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
    that start with ASM_ or end in ASM_OP.  */
 
+/* Redefines for option macros.  */
+
+#define TARGET_64BIT   OPTION_ISA_64BIT
+#define TARGET_MMX     OPTION_ISA_MMX
+#define TARGET_3DNOW   OPTION_ISA_3DNOW
+#define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
+#define TARGET_SSE     OPTION_ISA_SSE
+#define TARGET_SSE2    OPTION_ISA_SSE2
+#define TARGET_SSE3    OPTION_ISA_SSE3
+#define TARGET_SSSE3   OPTION_ISA_SSSE3
+#define TARGET_SSE4_1  OPTION_ISA_SSE4_1
+#define TARGET_SSE4_2  OPTION_ISA_SSE4_2
+#define TARGET_SSE4A   OPTION_ISA_SSE4A
+
 #include "config/vxworks-dummy.h"
 
 /* Algorithm to expand string function with.  */
@@ -342,13 +356,16 @@ extern unsigned int ix86_arch_features[X86_ARCH_LAST];
 #define TARGET_XADD            ix86_arch_features[X86_ARCH_XADD]
 #define TARGET_BSWAP           ix86_arch_features[X86_ARCH_BSWAP]
 
-#define TARGET_CMPXCHG16B      x86_cmpxchg16b
-#define TARGET_SAHF            x86_sahf
-
 #define TARGET_FISTTP          (TARGET_SSE3 && TARGET_80387)
 
 extern int x86_prefetch_sse;
+
+#define TARGET_ABM             x86_abm
+#define TARGET_CMPXCHG16B      x86_cmpxchg16b
+#define TARGET_POPCNT          x86_popcnt
 #define TARGET_PREFETCH_SSE    x86_prefetch_sse
+#define TARGET_SAHF            x86_sahf
+#define TARGET_RECIP           x86_recip
 
 #define ASSEMBLER_DIALECT      (ix86_asm_dialect)
 
@@ -361,6 +378,8 @@ extern int x86_prefetch_sse;
 #define TARGET_ANY_GNU_TLS     (TARGET_GNU_TLS || TARGET_GNU2_TLS)
 #define TARGET_SUN_TLS         (ix86_tls_dialect == TLS_DIALECT_SUN)
 
+extern int ix86_isa_flags;
+
 #ifndef TARGET_64BIT_DEFAULT
 #define TARGET_64BIT_DEFAULT 0
 #endif
@@ -368,13 +387,27 @@ extern int x86_prefetch_sse;
 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
 #endif
 
+/* Fence to use after loop using storent.  */
+
+extern tree x86_mfence;
+#define FENCE_FOLLOWING_MOVNT x86_mfence
+
 /* Once GDB has been enhanced to deal with functions without frame
    pointers, we can change this to allow for elimination of
    the frame pointer in leaf functions.  */
 #define TARGET_DEFAULT 0
 
+/* Extra bits to force.  */
+#define TARGET_SUBTARGET_DEFAULT 0
+#define TARGET_SUBTARGET_ISA_DEFAULT 0
+
+/* Extra bits to force on w/ 32-bit mode.  */
+#define TARGET_SUBTARGET32_DEFAULT 0
+#define TARGET_SUBTARGET32_ISA_DEFAULT 0
+
 /* Extra bits to force on w/ 64-bit mode.  */
 #define TARGET_SUBTARGET64_DEFAULT 0
+#define TARGET_SUBTARGET64_ISA_DEFAULT 0
 
 /* This is not really a target flag, but is done this way so that
    it's analogous to similar code for Mach-O on PowerPC.  darwin.h
@@ -540,6 +573,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
        builtin_define ("__SSE3__");                            \
       if (TARGET_SSSE3)                                                \
        builtin_define ("__SSSE3__");                           \
+      if (TARGET_SSE4_1)                                       \
+       builtin_define ("__SSE4_1__");                          \
+      if (TARGET_SSE4_2)                                       \
+       builtin_define ("__SSE4_2__");                          \
       if (TARGET_SSE4A)                                                \
        builtin_define ("__SSE4A__");                           \
       if (TARGET_SSE_MATH && TARGET_SSE)                       \
@@ -1237,6 +1274,7 @@ enum reg_class
   GENERAL_REGS,                        /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
   FP_TOP_REG, FP_SECOND_REG,   /* %st(0) %st(1) */
   FLOAT_REGS,
+  SSE_FIRST_REG,
   SSE_REGS,
   MMX_REGS,
   FP_TOP_SSE_REGS,
@@ -1255,7 +1293,7 @@ enum reg_class
 #define FLOAT_CLASS_P(CLASS) \
   reg_class_subset_p ((CLASS), FLOAT_REGS)
 #define SSE_CLASS_P(CLASS) \
-  ((CLASS) == SSE_REGS)
+  reg_class_subset_p ((CLASS), SSE_REGS)
 #define MMX_CLASS_P(CLASS) \
   ((CLASS) == MMX_REGS)
 #define MAYBE_INTEGER_CLASS_P(CLASS) \
@@ -1283,6 +1321,7 @@ enum reg_class
    "GENERAL_REGS",                     \
    "FP_TOP_REG", "FP_SECOND_REG",      \
    "FLOAT_REGS",                       \
+   "SSE_FIRST_REG",                    \
    "SSE_REGS",                         \
    "MMX_REGS",                         \
    "FP_TOP_SSE_REGS",                  \
@@ -1310,6 +1349,7 @@ enum reg_class
   { 0x1100ff,  0x1fe0 },               /* GENERAL_REGS */              \
      { 0x100,     0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
     { 0xff00,     0x0 },               /* FLOAT_REGS */                \
+  { 0x200000,     0x0 },               /* SSE_FIRST_REG */             \
 { 0x1fe00000,0x1fe000 },               /* SSE_REGS */                  \
 { 0xe0000000,    0x1f },               /* MMX_REGS */                  \
 { 0x1fe00100,0x1fe000 },               /* FP_TOP_SSE_REG */            \
@@ -2392,7 +2432,7 @@ struct machine_function GTY(())
    verify whether there's any such instruction live by testing that
    REG_SP is live.  */
 #define ix86_current_function_calls_tls_descriptor \
-  (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
+  (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
 
 /* Control behavior of x86_file_start.  */
 #define X86_FILE_START_VERSION_DIRECTIVE false