;; "worst case" and then be adjusted to their correct values by
;; h8300_adjust_insn_length.
-;; On the H8/300H and H8/S, adds/subs operate on the 32bit "er"
+;; On the H8/300H and H8S, adds/subs operate on the 32bit "er"
;; registers. Right now GCC doesn't expose the "e" half to the
;; compiler, so using add/subs for addhi and subhi is safe. Long
;; term, we want to expose the "e" half to the compiler (gives us 8
;; more 16bit registers). At that point addhi and subhi can't use
;; adds/subs.
-;; There's currently no way to have a insv/extzv expander for the H8/300H
+;; There's currently no way to have an insv/extzv expander for the H8/300H
;; because word_mode is different for the H8/300 and H8/300H.
;; Shifts/rotates by small constants should be handled by special
;; none - insn does not affect cc
;; none_0hit - insn does not affect cc but it does modify operand 0
;; This attribute is used to keep track of when operand 0 changes.
-;; See the description of NOTICE_UPDATE_CC for more info.
+;; See the description of NOTICE_UPDATE_CC for more info.
;; set_znv - insn sets z,n,v to usable values (like a tst insn); c is unknown.
;; set_zn - insn sets z,n to usable values; v,c are unknown.
;; compare - compare instruction
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
- (mult:HI (sign_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+ (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
"TARGET_H8300H || TARGET_H8300S"
"mulxs.b %X2,%T0"
(define_insn "mulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
- (mult:SI (sign_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+ (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
(sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
"TARGET_H8300H || TARGET_H8300S"
"mulxs.w %T2,%S0"
(define_insn "umulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
- (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%0"))
+ (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
""
"mulxu %X2,%T0"
(define_insn "umulhisi3"
[(set (match_operand:SI 0 "register_operand" "=r")
- (mult:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "%0"))
+ (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
(zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
"TARGET_H8300H || TARGET_H8300S"
"mulxu.w %T2,%S0"
(umod:HI
(match_dup 1)
(zero_extend:HI (match_dup 2)))))]
- "TARGET_H8300H || TARGET_H8300S"
+ ""
"*
{
if (find_reg_note (insn, REG_UNUSED, operands[3]))
[(set (match_operand:QI 0 "bit_operand" "=r,U")
(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
- "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
+ "register_operand (operands[0], QImode)
+ || single_zero_operand (operands[2], QImode)"
"@
and %X2,%X0
bclr %W2,%R0"
""
"
{
- if (fix_bit_operand (operands, 'O', AND))
+ if (fix_bit_operand (operands, 0, AND))
DONE;
}")
""
"")
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r")
- (and:HI (match_operand:HI 1 "register_operand" "%0")
- (match_operand:HI 2 "nonmemory_operand" "rn")))]
- "TARGET_H8300"
- "* return output_logical_op (HImode, AND, operands);"
+(define_insn "*andorqi3"
+ [(set (match_operand:QI 0 "register_operand" "=r")
+ (ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
+ (match_operand:QI 3 "single_one_operand" "n"))
+ (match_operand:QI 1 "register_operand" "0")))]
+ ""
+ "bld\\t%V3,%X2\;bst\\t%V3,%X0"
[(set_attr "length" "4")
(set_attr "cc" "clobber")])
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (and:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (HImode, AND, operands);"
- [(set_attr "length" "2,4")
- (set_attr "cc" "set_znv,clobber")])
-
(define_insn "*andorhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
- (match_operand:HI 3 "const_int_operand" "n"))
+ (match_operand:HI 3 "single_one_operand" "n"))
(match_operand:HI 1 "register_operand" "0")))]
- "exact_log2 (INTVAL (operands[3]) & 0xffff) != -1"
+ ""
"*
{
operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
""
"")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r")
- (and:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "nonmemory_operand" "rn")))]
- "TARGET_H8300"
- "* return output_logical_op (SImode, AND, operands);"
- [(set_attr "length" "8")
- (set_attr "cc" "clobber")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (and:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (SImode, AND, operands);"
- [(set_attr "length" "4,6")
- (set_attr "cc" "set_znv,clobber")])
-
;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------
(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
"register_operand (operands[0], QImode)
- || (GET_CODE (operands[2]) == CONST_INT
- && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
- "*
-{
- switch (which_alternative)
- {
- case 0:
- return \"or\t%X2,%X0\";
- case 1:
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
- return \"bset\t%V2,%R0\";
- default:
- abort ();
- }
-}"
+ || single_one_operand (operands[2], QImode)"
+ "@
+ or\\t%X2,%X0
+ bset\\t%V2,%R0"
[(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
""
"
{
- if (fix_bit_operand (operands, 'P', IOR))
+ if (fix_bit_operand (operands, 1, IOR))
DONE;
}")
""
"")
-(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=r,r")
- (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "J,rn")))]
- "TARGET_H8300"
- "* return output_logical_op (HImode, IOR, operands);"
- [(set_attr "length" "2,4")
- (set_attr "cc" "clobber,clobber")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=r,r,r")
- (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
- (match_operand:HI 2 "general_operand" "J,r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (HImode, IOR, operands);"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "clobber,set_znv,clobber")])
-
(define_expand "iorsi3"
[(set (match_operand:SI 0 "register_operand" "")
(ior:SI (match_operand:SI 1 "register_operand" "")
""
"")
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
- "TARGET_H8300"
- "* return output_logical_op (SImode, IOR, operands);"
- [(set_attr "length" "2,8")
- (set_attr "cc" "clobber,clobber")])
-
-(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
- (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (SImode, IOR, operands);"
- [(set_attr "length" "2,4,6")
- (set_attr "cc" "clobber,set_znv,clobber")])
-
;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------
(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
"register_operand (operands[0], QImode)
- || (GET_CODE (operands[2]) == CONST_INT
- && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
- "*
-{
- switch (which_alternative)
- {
- case 0:
- return \"xor\t%X2,%X0\";
- case 1:
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
- return \"bnot\t%V2,%R0\";
- default:
- abort ();
- }
-}"
+ || single_one_operand (operands[2], QImode)"
+ "@
+ xor\\t%X2,%X0
+ bnot\\t%V2,%R0"
[(set_attr "length" "2,8")
(set_attr "adjust_length" "no")
(set_attr "cc" "set_znv,none_0hit")])
""
"
{
- if (fix_bit_operand (operands, 'O', XOR))
+ if (fix_bit_operand (operands, 1, XOR))
DONE;
}")
""
"")
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r,r")
- (xor:HI (match_operand:HI 1 "register_operand" "%0,0")
- (match_operand:HI 2 "nonmemory_operand" "J,rn")))]
- "TARGET_H8300"
- "* return output_logical_op (HImode, XOR, operands);"
- [(set_attr "length" "2,4")
- (set_attr "cc" "clobber,clobber")])
-
-(define_insn ""
- [(set (match_operand:HI 0 "register_operand" "=r,r,r")
- (xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
- (match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (HImode, XOR, operands);"
- [(set_attr "length" "2,2,4")
- (set_attr "cc" "clobber,set_znv,clobber")])
-
(define_expand "xorsi3"
[(set (match_operand:SI 0 "register_operand" "")
(xor:SI (match_operand:SI 1 "register_operand" "")
""
"")
+;; ----------------------------------------------------------------------
+;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
+;; ----------------------------------------------------------------------
+
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "J,rn")))]
- "TARGET_H8300"
- "* return output_logical_op (SImode, XOR, operands);"
- [(set_attr "length" "2,8")
- (set_attr "cc" "clobber,clobber")])
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (match_operator:HI 3 "bit_operator"
+ [(match_operand:HI 1 "register_operand" "%0")
+ (match_operand:HI 2 "nonmemory_operand" "rn")]))]
+ ""
+ "* return output_logical_op (HImode, operands);"
+ [(set (attr "length")
+ (symbol_ref "compute_logical_op_length (HImode, operands)"))
+ (set (attr "cc")
+ (symbol_ref "compute_logical_op_cc (HImode, operands)"))])
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
- (match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
- "TARGET_H8300H || TARGET_H8300S"
- "* return output_logical_op (SImode, XOR, operands);"
- [(set_attr "length" "2,4,6")
- (set_attr "cc" "clobber,set_znv,clobber")])
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (match_operator:SI 3 "bit_operator"
+ [(match_operand:SI 1 "register_operand" "%0")
+ (match_operand:SI 2 "nonmemory_operand" "rn")]))]
+ ""
+ "* return output_logical_op (SImode, operands);"
+ [(set (attr "length")
+ (symbol_ref "compute_logical_op_length (SImode, operands)"))
+ (set (attr "cc")
+ (symbol_ref "compute_logical_op_cc (SImode, operands)"))])
\f
;; ----------------------------------------------------------------------
;; NEGATION INSTRUCTIONS
;; Call subroutine with no return value.
-;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
+;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
(define_insn "call"
[(call (match_operand:QI 0 "call_insn_operand" "or")
;; Call subroutine, returning value in operand 0
;; (which must be a hard register).
-;; ??? Even though we use HImode here, this works on the H8/300H and H8/S.
+;; ??? Even though we use HImode here, this works on the H8/300H and H8S.
(define_insn "call_value"
[(set (match_operand 0 "" "=r")
[(set (match_operand:QI 0 "register_operand" "=r,r")
(match_operator:QI 3 "nshift_operator"
[ (match_operand:QI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
+ (match_operand:QI 2 "nonmemory_operand" "R,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
""
"* return output_a_shift (operands);"
- [(set_attr "length" "20")
+ [(set (attr "length")
+ (symbol_ref "compute_a_shift_length (insn, operands)"))
(set_attr "cc" "clobber")])
;; HI BIT SHIFTS
[(set (match_operand:HI 0 "register_operand" "=r,r")
(match_operator:HI 3 "nshift_operator"
[ (match_operand:HI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "KM,rn")]))
+ (match_operand:QI 2 "nonmemory_operand" "S,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
""
"* return output_a_shift (operands);"
- [(set_attr "length" "20")
+ [(set (attr "length")
+ (symbol_ref "compute_a_shift_length (insn, operands)"))
(set_attr "cc" "clobber")])
;; SI BIT SHIFTS
[(set (match_operand:SI 0 "register_operand" "=r,r")
(match_operator:SI 3 "nshift_operator"
[ (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "K,rn")]))
+ (match_operand:QI 2 "nonmemory_operand" "T,rn")]))
(clobber (match_scratch:QI 4 "=X,&r"))]
""
"* return output_a_shift (operands);"
- [(set_attr "length" "20")
+ [(set (attr "length")
+ (symbol_ref "compute_a_shift_length (insn, operands)"))
(set_attr "cc" "clobber")])
\f
;; ----------------------------------------------------------------------
(set_attr "length" "6")])
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(const_int 1)
(match_operand 2 "const_int_operand" "n")))]
(set_attr "length" "6")])
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=&r")
+ [(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (xor:SI (match_operand:SI 1 "register_operand" "r")
(match_operand 3 "const_int_operand" "n"))
(const_int 1)
"TARGET_H8300"
"
{
- /* We only have single bit bitfield instructions. */
+ /* We only have single bit bit-field instructions. */
if (INTVAL (operands[1]) != 1)
FAIL;
"TARGET_H8300"
"
{
- /* We only have single bit bitfield instructions. */
+ /* We only have single bit bit-field instructions. */
if (INTVAL (operands[2]) != 1)
FAIL;
"mov.w\\t%f2,%e0"
[(set_attr "cc" "clobber")
(set_attr "length" "2")])
+
+(define_insn_and_split ""
+ [(set (pc)
+ (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ "#"
+ ""
+ [(set (cc0)
+ (match_dup 0))
+ (set (pc)
+ (if_then_else (ge (cc0)
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_insn_and_split ""
+ [(set (pc)
+ (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ "#"
+ ""
+ [(set (cc0)
+ (match_dup 0))
+ (set (pc)
+ (if_then_else (lt (cc0)
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
OSDN Git Service
