/* Definitions of target machine for GNU compiler.
Hitachi H8/300 version generating coff
- Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000
+ Free SoftwareFoundation, Inc.
Contributed by Steve Chamberlain (sac@cygnus.com),
Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
-/* Which cpu to compile for.
+#ifndef GCC_H8300_H
+#define GCC_H8300_H
+
+/* Which CPU to compile for.
We use int for CPU_TYPE to avoid lots of casts. */
#if 0 /* defined in insn-attr.h, here for documentation */
enum attr_cpu { CPU_H8300, CPU_H8300H };
/* Various globals defined in h8300.c. */
-extern char *h8_push_op,*h8_pop_op,*h8_mov_op;
-extern char **h8_reg_names;
+extern const char *h8_push_op, *h8_pop_op, *h8_mov_op;
+extern const char * const *h8_reg_names;
/* Names to predefine in the preprocessor for this target machine. */
"-D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L"
#define CPP_SPEC \
- "%{!mh:-D__H8300__} %{mh:-D__H8300H__} \
- %{!mh:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
+ "%{!mh:%{!ms:-D__H8300__}} %{mh:-D__H8300H__} %{ms:-D__H8300S__} \
+ %{!mh:%{!ms:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
%{mh:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
- %{!mh:-Acpu(h8300) -Amachine(h8300)} %{mh:-Acpu(h8300h) -Amachine(h8300h)} \
+ %{ms:-D__SIZE_TYPE__=unsigned\\ long -D__PTRDIFF_TYPE__=long} \
+ %{!mh:%{!ms:-Acpu(h8300) -Amachine(h8300)}} \
+ %{mh:-Acpu(h8300h) -Amachine(h8300h)} \
+ %{ms:-Acpu(h8300s) -Amachine(h8300s)} \
%{!mint32:-D__INT_MAX__=32767} %{mint32:-D__INT_MAX__=2147483647}"
-#define LINK_SPEC "%{mh:-m h8300h}"
+#define LINK_SPEC "%{mh:-m h8300h} %{ms:-m h8300s}"
#define LIB_SPEC "%{mrelax:-relax} %{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
This is for debugging the compiler only. */
#define TARGET_RTL_DUMP (target_flags & 2048)
-/* Select between the h8/300 and h8/300h cpus. */
-#define TARGET_H8300 (! TARGET_H8300H)
+/* Select between the H8/300 and H8/300H CPUs. */
+#define TARGET_H8300 (! TARGET_H8300H && ! TARGET_H8300S)
#define TARGET_H8300H (target_flags & 4096)
+#define TARGET_H8300S (target_flags & 1)
+
+/* mac register and relevant instructions are available. */
+#define TARGET_MAC (target_flags & 2)
-/* Align structures on the h8/300h the same way as the h8/300. Specifically,
- 32 bit and larger values in structures are aligned on 16 bit boundaries.
- This is all the hardware requires, but the default is 32 bits for the 300h.
+/* Align all values on the H8/300H the same way as the H8/300. Specifically,
+ 32 bit and larger values are aligned on 16 bit boundaries.
+ This is all the hardware requires, but the default is 32 bits for the 300H.
??? Now watch someone add hardware floating point requiring 32 bit
alignment. */
-#define TARGET_ALIGN_STRUCT_300 (target_flags & 8192)
+#define TARGET_ALIGN_300 (target_flags & 8192)
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"int32",8}, \
- {"addresses",64 }, \
- {"quickcall",128}, \
- {"no-quickcall",-128}, \
- {"slowbyte",256}, \
- {"relax",1024}, \
- {"rtl-dump",2048}, \
- {"h",4096}, \
- {"no-h",-4096}, \
- {"align-struct-300",8192}, \
- { "", TARGET_DEFAULT}}
+ { {"s", 1, N_("Generate H8/S code")}, \
+ {"no-s", -1, N_("Do not generate H8/S code")}, \
+ {"s2600", 2, N_("Generate H8/S2600 code")}, \
+ {"no-s2600", -2, N_("Do not generate H8/S2600 code")}, \
+ {"int32", 8, N_("Make integers 32 bits wide")}, \
+ {"addresses", 64, NULL}, \
+ {"quickcall", 128, \
+ N_("Use registers for argument passing")}, \
+ {"no-quickcall", -128, \
+ N_("Do not use registers for argument passing")}, \
+ {"slowbyte", 256, \
+ N_("Consider access to byte sized memory slow")}, \
+ {"relax", 1024, N_("Enable linker relaxing")}, \
+ {"rtl-dump", 2048, NULL}, \
+ {"h", 4096, N_("Generate H8/300H code")}, \
+ {"no-h", -4096, N_("Do not generate H8/300H code")}, \
+ {"align-300", 8192, N_("Use H8/300 alignment rules")}, \
+ { "", TARGET_DEFAULT, NULL}}
+
+#ifdef IN_LIBGCC2
+#undef TARGET_H8300H
+#undef TARGET_H8300S
+/* If compiling libgcc2, make these compile time constants based on what
+ flags are we actually compiling with. */
+#ifdef __H8300H__
+#define TARGET_H8300H 1
+#else
+#define TARGET_H8300H 0
+#endif
+#ifdef __H8300S__
+#define TARGET_H8300S 1
+#else
+#define TARGET_H8300S 0
+#endif
+#endif /* !IN_LIBGCC2 */
/* Do things that must be done once at start up. */
-#define OVERRIDE_OPTIONS \
-do { \
- h8300_init_once (); \
-} while (0)
+#define OVERRIDE_OPTIONS \
+ do \
+ { \
+ h8300_init_once (); \
+ } \
+ while (0)
/* Default target_flags if no switches specified. */
/* Define this if addresses of constant functions
shouldn't be put through pseudo regs where they can be cse'd.
Desirable on machines where ordinary constants are expensive
- but a CALL with constant address is cheap. */
+ but a CALL with constant address is cheap.
+
+ Calls through a register are cheaper than calls to named
+ functions; however, the register pressure this causes makes
+ CSEing of function addresses generally a lose. */
#define NO_FUNCTION_CSE
\f
/* Target machine storage layout */
/* Define this if most significant word of a multiword number is lowest
numbered.
This is true on an H8/300 (actually we can make it up, but we choose to
- be consistent. */
+ be consistent). */
#define WORDS_BIG_ENDIAN 1
/* Number of bits in an addressable storage unit */
Note that this is not necessarily the width of data type `int';
if using 16-bit ints on a 68000, this would still be 32.
But on a machine with 16-bit registers, this would be 16. */
-#define BITS_PER_WORD (TARGET_H8300H ? 32 : 16)
+#define BITS_PER_WORD (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
#define MAX_BITS_PER_WORD 32
/* Width of a word, in units (bytes). */
-#define UNITS_PER_WORD (TARGET_H8300H ? 4 : 2)
+#define UNITS_PER_WORD (TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MIN_UNITS_PER_WORD 2
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
-#define POINTER_SIZE (TARGET_H8300H ? 32 : 16)
+#define POINTER_SIZE (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
#define SHORT_TYPE_SIZE 16
#define INT_TYPE_SIZE (TARGET_INT32 ? 32 : 16)
#define LONG_TYPE_SIZE 32
-#define LONG_LONG_TYPE_SIZE 32
+#define LONG_LONG_TYPE_SIZE 32
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 32
#define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
#define MAX_FIXED_MODE_SIZE 32
/* Allocation boundary (in *bits*) for storing arguments in argument list. */
-#define PARM_BOUNDARY (TARGET_H8300H ? 32 : 16)
+#define PARM_BOUNDARY (TARGET_H8300H || TARGET_H8300S ? 32 : 16)
/* Allocation boundary (in *bits*) for the code of a function. */
#define FUNCTION_BOUNDARY 16
/* No data type wants to be aligned rounder than this.
32 bit values are aligned as such on the 300h for speed. */
-#define BIGGEST_ALIGNMENT (TARGET_H8300H ? 32 : 16)
-
-/* No structure field wants to be aligned rounder than this. */
-#define BIGGEST_FIELD_ALIGNMENT \
-((TARGET_H8300H && ! TARGET_ALIGN_STRUCT_300) ? 32 : 16)
+#define BIGGEST_ALIGNMENT \
+(((TARGET_H8300H || TARGET_H8300S) && ! TARGET_ALIGN_300) ? 32 : 16)
/* The stack goes in 16/32 bit lumps. */
#define STACK_BOUNDARY (TARGET_H8300 ? 16 : 32)
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
- Reg 8 does not correspond to any hardware register, but instead
+ Reg 9 does not correspond to any hardware register, but instead
appears in the RTL as an argument pointer prior to reload, and is
eliminated during reloading in favor of either the stack or frame
pointer. */
-#define FIRST_PSEUDO_REGISTER 9
+#define FIRST_PSEUDO_REGISTER 10
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator. */
#define FIXED_REGISTERS \
- { 0, 0, 0, 0, 0, 0, 0, 1, 1}
+ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
Aside from that, you can include as many other registers as you
like.
- h8 destroys r0,r1,r2,r3. */
+ H8 destroys r0,r1,r2,r3. */
#define CALL_USED_REGISTERS \
- { 1, 1, 1, 1, 0, 0, 0, 1, 1 }
+ { 1, 1, 1, 1, 0, 0, 0, 1, 1, 1 }
#define REG_ALLOC_ORDER \
- { 2, 3, 0, 1, 4, 5, 6, 7, 8}
+ { 2, 3, 0, 1, 4, 5, 6, 8, 7, 9}
+
+#define CONDITIONAL_REGISTER_USAGE \
+{ \
+ if (!TARGET_MAC) \
+ fixed_regs[8] = call_used_regs[8] = 1; \
+}
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
- but can be less for certain modes in special long registers. */
+ but can be less for certain modes in special long registers.
+
+ We pretend the MAC register is 32bits -- we don't have any data
+ types on the H8 series to handle more than 32bits. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* Value is 1 if hard register REGNO can hold a value of machine-mode
MODE.
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(TARGET_H8300 ? (((REGNO)&1)==0) || (MODE==HImode) || (MODE==QImode) \
- : 1)
+ : REGNO == 8 ? MODE == SImode : 1)
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
for any hard reg, then this must be 0 for correct output. */
-#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2))
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+ ((MODE1) == (MODE2) \
+ || ((MODE1) == HImode && (MODE2) == QImode) \
+ || ((MODE1) == QImode && (MODE2) == HImode) \
+ || ((TARGET_H8300H || TARGET_H8300S) \
+ && (((MODE1) == SImode && (MODE2) == HImode) \
+ || ((MODE1) == HImode && (MODE2) == SImode))))
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
#define FRAME_POINTER_REQUIRED 0
/* Base register for access to arguments of the function. */
-#define ARG_POINTER_REGNUM 8
+#define ARG_POINTER_REGNUM 9
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 3
For any two classes, it is very desirable that there be another
class that represents their union. */
-
-/* The h8 has only one kind of register, but we mustn't do byte by
- byte operations on the sp, so we keep it as a different class */
-enum reg_class { NO_REGS, LONG_REGS, GENERAL_REGS, SP_REG, SP_AND_G_REG, ALL_REGS, LIM_REG_CLASSES };
+enum reg_class {
+ NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS, LIM_REG_CLASSES
+};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
- {"NO_REGS", "LONG_REGS", "GENERAL_REGS", "SP_REG", "SP_AND_G_REG", "ALL_REGS", "LIM_REGS" }
+{ "NO_REGS", "GENERAL_REGS", "MAC_REGS", "ALL_REGS", "LIM_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \
-{ 0, /* No regs */ \
- 0x07f, /* LONG_REGS */ \
- 0x07f, /* GENERAL_REGS */ \
- 0x080, /* SP_REG */ \
- 0x0ff, /* SP_AND_G_REG */ \
- 0x1ff, /* ALL_REGS */ \
+{ {0}, /* No regs */ \
+ {0x2ff}, /* GENERAL_REGS */ \
+ {0x100}, /* MAC_REGS */ \
+ {0x3ff}, /* ALL_REGS */ \
}
/* The same information, inverted:
reg number REGNO. This could be a conditional expression
or could index an array. */
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) < 7 ? LONG_REGS : \
- (REGNO) == 7 ? SP_REG : \
- GENERAL_REGS)
+#define REGNO_REG_CLASS(REGNO) (REGNO != 8 ? GENERAL_REGS : MAC_REGS)
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS NO_REGS
#define BASE_REG_CLASS GENERAL_REGS
-/* Get reg_class from a letter such as appears in the machine description. */
+/* Get reg_class from a letter such as appears in the machine description.
+
+ 'a' is the MAC register. */
-#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'a' ? (SP_REG) : (C) == 'l' ? (LONG_REGS) : (NO_REGS))
+#define REG_CLASS_FROM_LETTER(C) ((C) == 'a' ? MAC_REGS : NO_REGS)
/* The letters I, J, K, L, M, N, O, P in a register constraint string
can be used to stand for particular ranges of immediate operands.
Return 1 if VALUE is in the range specified by C. */
#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
-#define CONST_OK_FOR_J(VALUE) ((unsigned) (VALUE) < 256)
-#define CONST_OK_FOR_K(VALUE) (((VALUE) == 1) || (VALUE) == 2)
-#define CONST_OK_FOR_L(VALUE) (((VALUE) == -1) || (VALUE) == -2)
-#define CONST_OK_FOR_M(VALUE) (((VALUE) == 3) || (VALUE) == 4)
-#define CONST_OK_FOR_N(VALUE) (((VALUE) == -3) || (VALUE) == -4)
+#define CONST_OK_FOR_J(VALUE) ((unsigned HOST_WIDE_INT) (VALUE) < 256)
+#define CONST_OK_FOR_K(VALUE) ((VALUE) == 1 || (VALUE) == 2)
+#define CONST_OK_FOR_L(VALUE) \
+ (TARGET_H8300H || TARGET_H8300S \
+ ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 4 \
+ : (VALUE) == 1 || (VALUE) == 2)
+#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3 || (VALUE) == 4)
+#define CONST_OK_FOR_N(VALUE) \
+ (TARGET_H8300H || TARGET_H8300S \
+ ? (VALUE) == -1 || (VALUE) == -2 || (VALUE) == -4 \
+ : (VALUE) == -1 || (VALUE) == -2)
#define CONST_OK_FOR_O(VALUE) (ok_for_bclr (VALUE))
#define CONST_OK_FOR_P(VALUE) (small_power_of_two (VALUE))
-#define CONST_OK_FOR_LETTER_P(VALUE, C) \
- ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
- (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
- (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
- (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
- (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
- (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \
- (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \
- (C) == 'P' ? CONST_OK_FOR_P(VALUE) : \
+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
+ ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
+ (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
+ (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
+ (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
+ (C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
+ (C) == 'N' ? CONST_OK_FOR_N (VALUE) : \
+ (C) == 'O' ? CONST_OK_FOR_O (VALUE) : \
+ (C) == 'P' ? CONST_OK_FOR_P (VALUE) : \
0)
/* Similar, but for floating constants, and defining letters G and H.
`G' is a floating-point zero. */
-#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? (VALUE) == CONST0_RTX (DFmode) \
: 0)
so define REGISTER_MOVE_COST to be > 2 so that reload never
shortcuts. */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) 3
+#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
+ (CLASS1 == MAC_REGS || CLASS2 == MAC_REGS ? 6 : 3)
\f
/* Stack layout; function entry, exit and calling. */
On the H8 the return value is in R0/R1. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
- gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
+ gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
/* On the h8 the return value is in R0/R1 */
#define LIBCALL_VALUE(MODE) \
- gen_rtx (REG, MODE, 0)
+ gen_rtx_REG (MODE, 0)
/* 1 if N is a possible register number for a function value.
On the H8, R0 is the only register thus used. */
/* 1 if N is a possible register number for function argument passing.
On the H8, no registers are used in this way. */
-/* ??? What about TARGET_QUICKCALL? */
-#define FUNCTION_ARG_REGNO_P(N) 0
+#define FUNCTION_ARG_REGNO_P(N) (TARGET_QUICKCALL ? N < 3 : 0)
/* Register in which address to store a structure value
is passed to a function. */
#define STRUCT_VALUE 0
/* Return true if X should be returned in memory. */
-/* ??? This will return small structs in regs. */
-#define RETURN_IN_MEMORY(X) (GET_MODE_SIZE (TYPE_MODE (X)) > 4)
+#define RETURN_IN_MEMORY(X) \
+ (TYPE_MODE (X) == BLKmode || GET_MODE_SIZE (TYPE_MODE (X)) > 4)
/* When defined, the compiler allows registers explicitly used in the
rtl to be used as spill registers but prevents the compiler from
extending the lifetime of these registers. */
-#define SMALL_REGISTER_CLASSES
+#define SMALL_REGISTER_CLASSES 1
\f
/* Define a data type for recording info about an argument list
during the scan of that argument list. This data type should
function if any. */
#define CUMULATIVE_ARGS struct cum_arg
-struct cum_arg { int nbytes; struct rtx_def * libcall; };
+struct cum_arg
+{
+ int nbytes;
+ struct rtx_def *libcall;
+};
/* Initialize a variable CUM of type CUMULATIVE_ARGS
for a call to a function whose data type is FNTYPE.
On the H8/300, the offset starts at 0. */
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
((CUM).nbytes = 0, (CUM).libcall = LIBNAME)
/* Update the data in CUM to advance over an argument
of mode MODE and data type TYPE.
(TYPE is null for libcalls where that information may not be available.) */
-#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
- ((CUM).nbytes += ((MODE) != BLKmode \
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
+ ((CUM).nbytes += ((MODE) != BLKmode \
? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \
: (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
case the first 3 arguments are passed in registers.
See function `function_arg'. */
-struct rtx_def *function_arg();
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg (&CUM, MODE, TYPE, NAMED)
-/* Perform any needed actions needed for a function that is receiving a
- variable number of arguments. */
-
-extern int current_function_anonymous_args;
-#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
- current_function_anonymous_args = 1;
-
/* Generate assembly output for the start of a function. */
#define FUNCTION_PROLOGUE(FILE, SIZE) \
else \
{ \
fprintf (FILE, "\tmov.l #0x12345678,er3\n"); \
- fprintf (FILE, "\tjmp @0x123456\n"); \
+ fprintf (FILE, "\tjmp @0x123456\n"); \
} \
} while (0)
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
{ \
- enum machine_mode mode = TARGET_H8300H ? SImode : HImode; \
- emit_move_insn (gen_rtx (MEM, mode, plus_constant ((TRAMP), 2)), CXT); \
- emit_move_insn (gen_rtx (MEM, mode, plus_constant ((TRAMP), 6)), FNADDR); \
- if (TARGET_H8300H) \
- emit_move_insn (gen_rtx (MEM, QImode, plus_constant ((TRAMP), 6)), GEN_INT (0x5A)); \
+ enum machine_mode mode = TARGET_H8300H || TARGET_H8300S? SImode : HImode; \
+ emit_move_insn (gen_rtx_MEM (mode, plus_constant ((TRAMP), 2)), CXT); \
+ emit_move_insn (gen_rtx_MEM (mode, plus_constant ((TRAMP), 6)), FNADDR); \
+ if (TARGET_H8300H || TARGET_H8300S) \
+ emit_move_insn (gen_rtx_MEM (QImode, plus_constant ((TRAMP), 6)), \
+ GEN_INT (0x5A)); \
}
\f
/* Addressing modes, and classification of registers for them. */
-#define HAVE_POST_INCREMENT
-/*#define HAVE_POST_DECREMENT */
+#define HAVE_POST_INCREMENT 1
+/*#define HAVE_POST_DECREMENT 0 */
-#define HAVE_PRE_DECREMENT
-/*#define HAVE_PRE_INCREMENT */
+#define HAVE_PRE_DECREMENT 1
+/*#define HAVE_PRE_INCREMENT 0 */
/* Macros to check register numbers against specific register classes. */
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in local-alloc.c. */
-
+
#define REGNO_OK_FOR_INDEX_P(regno) 0
#define REGNO_OK_FOR_BASE_P(regno) \
- ((regno) < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0)
+ (((regno) < FIRST_PSEUDO_REGISTER && regno != 8) || reg_renumber[regno] >= 0)
\f
/* Maximum number of registers that can appear in a valid memory address. */
/* 1 if X is an rtx for a constant that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) \
+#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| (GET_CODE (X) == CONST_INT \
/* We handle signed and unsigned offsets here. */ \
&& INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \
&& INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000)) \
- || GET_CODE (X) == CONST \
- || GET_CODE (X) == HIGH)
+ || ((GET_CODE (X) == HIGH || GET_CODE (X) == CONST) \
+ && TARGET_H8300))
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
#define REG_OK_FOR_INDEX_P(X) 0
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
-#define REG_OK_FOR_BASE_P(X) 1
+/* Don't use REGNO_OK_FOR_BASE_P here because it uses reg_renumber. */
+#define REG_OK_FOR_BASE_P(X) \
+ (REGNO (X) >= FIRST_PSEUDO_REGISTER || REGNO (X) != 8)
#define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#define STRICT 0
#endif
-/* Extra constraints - 'U' if for an operand valid for a bset
- destination; i.e. a register or register indirect target. */
-#define OK_FOR_U(OP) \
- ((GET_CODE (OP) == REG && REG_OK_FOR_BASE_P (OP)) \
- || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (OP, 0))))
-
-#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'U' ? OK_FOR_U (OP) : 0)
+/* Extra constraints. */
+
+/* 'T' if valid for dec.[wl] on H8/300H and H8/S. Note that, for
+ inc.[wl], we can use 'K', which has already been defined. */
+#define OK_FOR_T(OP) \
+ (GET_CODE (OP) == CONST_INT \
+ && (INTVAL (OP) == -1 || INTVAL (OP) == -2))
+
+/* Nonzero if X is a constant address suitable as an 8-bit absolute on
+ the H8/300H, which is a special case of the 'R' operand. */
+
+#define EIGHTBIT_CONSTANT_ADDRESS_P(X) \
+ (GET_CODE (X) == CONST_INT && TARGET_H8300H \
+ && 0xffff00 <= INTVAL (X) && INTVAL (X) <= 0xffffff)
+
+/* 'U' if valid for a bset destination;
+ i.e. a register, register indirect, or the eightbit memory region
+ (a SYMBOL_REF with an SYMBOL_REF_FLAG set).
+
+ On the H8/S 'U' can also be a 16bit or 32bit absolute. */
+#define OK_FOR_U(OP) \
+ ((GET_CODE (OP) == REG && REG_OK_FOR_BASE_P (OP)) \
+ || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
+ && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
+ || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
+ && (TARGET_H8300S || SYMBOL_REF_FLAG (XEXP (OP, 0)))) \
+ || ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST \
+ && GET_CODE (XEXP (XEXP (OP, 0), 0)) == PLUS \
+ && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 0)) == SYMBOL_REF \
+ && GET_CODE (XEXP (XEXP (XEXP (OP, 0), 0), 1)) == CONST_INT) \
+ && (TARGET_H8300S || SYMBOL_REF_FLAG (XEXP (XEXP (OP, 0), 0)))) \
+ || (GET_CODE (OP) == MEM \
+ && EIGHTBIT_CONSTANT_ADDRESS_P (XEXP (OP, 0))) \
+ || (GET_CODE (OP) == MEM && TARGET_H8300S \
+ && GET_CODE (XEXP (OP, 0)) == CONST_INT))
+
+#define EXTRA_CONSTRAINT(OP, C) \
+ ((C) == 'T' ? OK_FOR_T (OP) : \
+ (C) == 'U' ? OK_FOR_U (OP) : \
+ 0)
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
that is a valid memory address for an instruction.
REG, REG+CONSTANT_ADDRESS or CONSTANT_ADDRESS. */
/* Accept either REG or SUBREG where a register is valid. */
-
+
#define RTX_OK_FOR_BASE_P(X) \
((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
|| (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
has an effect that depends on the machine mode it is used for.
On the H8/300, the predecrement and postincrement address depend thus
- (the amount of decrement or increment being the length of the operand)
- and all indexed address depend thus (because the index scale factor
- is the length of the operand). */
+ (the amount of decrement or increment being the length of the operand). */
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL;
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE Pmode
-/* Define this if the case instruction expects the table
- to contain offsets from the address of the table.
- Do not define this if the table should contain absolute addresses. */
-/*#define CASE_VECTOR_PC_RELATIVE*/
-
-/* Define this if the case instruction drops through after the table
- when the index is out of range. Don't define it if the case insn
- jumps to the default label instead. */
-#define CASE_DROPS_THROUGH
+/* Define as C expression which evaluates to nonzero if the tablejump
+ instruction expects the table to contain offsets from the address of the
+ table.
+ Do not define this if the table should contain absolute addresses. */
+/*#define CASE_VECTOR_PC_RELATIVE 1 */
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
-#define MOVE_MAX (TARGET_H8300H ? 4 : 2)
+#define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MAX_MOVE_MAX 4
/* Define this if zero-extension is slow (more than one real instruction). */
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
-#define Pmode (TARGET_H8300H ? SImode : HImode)
+#define Pmode (TARGET_H8300H || TARGET_H8300S ? SImode : HImode)
/* ANSI C types.
We use longs for the 300h because ints can be 16 or 32.
so give the MEM rtx a byte's mode. */
#define FUNCTION_MODE QImode
+/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
+ is a valid machine specific attribute for DECL.
+ The attributes in ATTRIBUTES have previously been assigned to DECL. */
+#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
+h8300_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
+
+#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
+ LENGTH += h8300_adjust_insn_length (INSN, LENGTH);
+
/* Compute the cost of computing a constant rtl expression RTX
whose rtx-code is CODE. The body of this macro is a portion
of a switch statement. If the code is computed here,
return it with a return statement. Otherwise, break from the switch. */
-#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
- default: { int _zxy= const_costs(RTX, CODE); \
- if(_zxy) return _zxy; break;}
+#define DEFAULT_RTX_COSTS(RTX,CODE,OUTER_CODE) \
+ return (const_costs (RTX, CODE));
#define BRANCH_COST 0
switch on CODE. */
/* ??? Shifts need to have a *much* higher cost than this. */
-#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
- case MOD: \
- case DIV: \
- return 60; \
- case MULT: \
- return 20; \
- case ASHIFT: \
- case ASHIFTRT: \
- case LSHIFTRT: \
- case ROTATE: \
- case ROTATERT: \
- if (GET_MODE (RTX) == HImode) return 2; \
- return 8;
+#define RTX_COSTS(RTX,CODE,OUTER_CODE) \
+ case MOD: \
+ case DIV: \
+ return 60; \
+ case MULT: \
+ return 20; \
+ case ASHIFT: \
+ case ASHIFTRT: \
+ case LSHIFTRT: \
+ case ROTATE: \
+ case ROTATERT: \
+ if (GET_MODE (RTX) == HImode) return 2; \
+ return 8;
/* Tell final.c how to eliminate redundant test instructions. */
/* Here we define machine-dependent flags and fields in cc_status
- (see `conditions.h'). No extra ones are needed for the vax. */
+ (see `conditions.h'). No extra ones are needed for the h8300. */
/* Store in cc_status the expressions
that the condition codes will describe
Do not alter them if the instruction would not alter the cc's. */
#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
-#define CC_DONE_CBIT 0400
-#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
-{ \
- if (cc_status.flags & CC_NO_OVERFLOW) \
- return NO_OV; \
- return NORMAL; \
-}
+/* The add insns don't set overflow in a usable way. */
+#define CC_OVERFLOW_UNUSABLE 01000
+/* The mov,and,or,xor insns don't set carry. That's ok though as the
+ Z bit is all we need when doing unsigned comparisons on the result of
+ these insns (since they're always with 0). However, conditions.h has
+ CC_NO_OVERFLOW defined for this purpose. Rename it to something more
+ understandable. */
+#define CC_NO_CARRY CC_NO_OVERFLOW
\f
/* Control the assembler format that we output. */
-#define ASM_IDENTIFY_GCC /* nothing */
+#define ASM_IDENTIFY_GCC(FILE) /* nothing */
/* Output at beginning/end of assembler file. */
#define IDENT_ASM_OP "\t.ident\n"
/* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H. */
-#define ASM_WORD_OP (TARGET_H8300 ? ".word" : ".long")
+#define ASM_WORD_OP (TARGET_H8300 ? "\t.word\t" : "\t.long\t")
-/* Output before read-only data. */
+/* We define a readonly data section solely to remove readonly data
+ from the instruction stream. This can improve relaxing in two significant
+ ways. First it's more likely that references to readonly data
+ can be done with a 16bit absolute address since they'll be in low
+ memory. Second, it's more likely that jsr instructions can be
+ turned into bsr instructions since read-only data is not in the
+ instruction stream. */
+#define READONLY_DATA_SECTION readonly_data
#define TEXT_SECTION_ASM_OP "\t.section .text"
#define DATA_SECTION_ASM_OP "\t.section .data"
#define INIT_SECTION_ASM_OP "\t.section .init"
#define CTORS_SECTION_ASM_OP "\t.section .ctors"
#define DTORS_SECTION_ASM_OP "\t.section .dtors"
+#define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata"
-#define EXTRA_SECTIONS in_ctors, in_dtors
+#define EXTRA_SECTIONS in_ctors, in_dtors, in_readonly_data
#define EXTRA_SECTION_FUNCTIONS \
\
void \
-ctors_section() \
+ctors_section () \
{ \
if (in_section != in_ctors) \
{ \
} \
\
void \
-dtors_section() \
+dtors_section () \
{ \
if (in_section != in_dtors) \
{ \
in_section = in_dtors; \
} \
} \
+ \
+void \
+readonly_data () \
+{ \
+ if (in_section != in_readonly_data) \
+ { \
+ fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP);\
+ in_section = in_readonly_data; \
+ } \
+}
#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
do { ctors_section(); \
- fprintf(FILE, "\t%s\t_%s\n", ASM_WORD_OP, NAME); } while (0)
+ fprintf(FILE, "%s_%s\n", ASM_WORD_OP, NAME); } while (0)
#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { dtors_section(); \
- fprintf(FILE, "\t%s\t_%s\n", ASM_WORD_OP, NAME); } while (0)
+ fprintf(FILE, "%s_%s\n", ASM_WORD_OP, NAME); } while (0)
-#undef DO_GLOBAL_CTORS_BODY
+#undef DO_GLOBAL_CTORS_BODY
#define DO_GLOBAL_CTORS_BODY \
{ \
typedef (*pfunc)(); \
{ \
(*--p)(); \
} \
-}
+}
-#undef DO_GLOBAL_DTORS_BODY
+#undef DO_GLOBAL_DTORS_BODY
#define DO_GLOBAL_DTORS_BODY \
{ \
typedef (*pfunc)(); \
{ \
(*p)(); \
} \
-}
+}
+
+#define TINY_DATA_NAME_P(NAME) (*(NAME) == '&')
+
+/* If we are referencing a function that is supposed to be called
+ through the function vector, the SYMBOL_REF_FLAG in the rtl
+ so the call patterns can generate the correct code. */
+#define ENCODE_SECTION_INFO(DECL) \
+ if (TREE_CODE (DECL) == FUNCTION_DECL \
+ && h8300_funcvec_function_p (DECL)) \
+ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
+ else if ((TREE_STATIC (DECL) || DECL_EXTERNAL (DECL)) \
+ && TREE_CODE (DECL) == VAR_DECL \
+ && h8300_eightbit_data_p (DECL)) \
+ SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
+ else if ((TREE_STATIC (DECL) || DECL_EXTERNAL (DECL)) \
+ && TREE_CODE (DECL) == VAR_DECL \
+ && h8300_tiny_data_p (DECL)) \
+ h8300_encode_label (DECL);
+
+/* Store the user-specified part of SYMBOL_NAME in VAR.
+ This is sort of inverse to ENCODE_SECTION_INFO. */
+#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
+ (VAR) = (SYMBOL_NAME) + ((SYMBOL_NAME)[0] == '*' || (SYMBOL_NAME)[0] == '@' || (SYMBOL_NAME)[0] == '&')
/* How to refer to registers in assembler output.
This sequence is indexed by compiler's hard-register-number (see above). */
#define REGISTER_NAMES \
-{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "ap"}
+{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "mac", "ap"}
-#define ADDITIONAL_REGISTER_NAMES { { "r7", 7 } }
+#define ADDITIONAL_REGISTER_NAMES \
+{ {"er0", 0}, {"er1", 1}, {"er2", 2}, {"er3", 3}, {"er4", 4}, \
+ {"er5", 5}, {"er6", 6}, {"er7", 7}, {"r7", 7} }
/* How to renumber registers for dbx and gdb.
H8/300 needs no change in the numeration. */
#include "dbxcoff.h"
+/* Override definition in dbxcoff.h. */
+/* Generate a blank trailing N_SO to mark the end of the .o file, since
+ we can't depend upon the linker to mark .o file boundaries with
+ embedded stabs. */
+
+#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
+#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \
+ fprintf (FILE, \
+ "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
+
/* A C statement to output something to the assembler file to switch to section
NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
NULL_TREE. Some target formats do not support arbitrary sections. Do not
define this macro in such cases. */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
+#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
fprintf (FILE, "\t.section %s\n", NAME)
/* This is how to output the definition of a user-level label named NAME,
#define ASM_OUTPUT_LABEL(FILE, NAME) \
do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
-#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)
+#define ASM_OUTPUT_LABELREF(FILE,NAME) \
+ asm_fprintf ((FILE), "%U%s", (NAME) + (TINY_DATA_NAME_P (NAME) ? 1 : 0))
+
+#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)
/* This is how to output a command to make the user-level label named NAME
defined for reference from other files. */
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
ASM_OUTPUT_LABEL(FILE, NAME)
-/* This is how to output a reference to a user-level label named NAME.
- `assemble_name' uses this. */
+/* The prefix to add to user-visible assembler symbols. */
-#define ASM_OUTPUT_LABELREF(FILE, NAME) \
- fprintf (FILE, "_%s", NAME)
+#define USER_LABEL_PREFIX "_"
/* This is how to output an internal numbered label where
- PREFIX is the class of label and NUM is the number within the class. */
+ PREFIX is the class of label and NUM is the number within the class.
+
+ N.B.: The h8300.md branch_true and branch_false patterns also know
+ how to generate internal labels. */
#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM) \
fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
fprintf (FILE, "\t.double %s\n", dstr); \
} while (0)
-
/* This is how to output an assembler line defining a `float' constant. */
#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
do { char dstr[30]; \
/* This is how to output an element of a case-vector that is absolute. */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
- asm_fprintf (FILE, "\t%s .L%d\n", ASM_WORD_OP, VALUE)
+ asm_fprintf (FILE, "%s.L%d\n", ASM_WORD_OP, VALUE)
/* This is how to output an element of a case-vector that is relative. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
- fprintf (FILE, "\t%s .L%d-.L%d\n", ASM_WORD_OP, VALUE, REL)
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
+ fprintf (FILE, "%s.L%d-.L%d\n", ASM_WORD_OP, VALUE, REL)
/* This is how to output an assembler line
that says to advance the location counter
to a multiple of 2**LOG bytes. */
-#define ASM_OUTPUT_ALIGN(FILE,LOG) \
- if ((LOG) != 0) \
+#define ASM_OUTPUT_ALIGN(FILE,LOG) \
+ if ((LOG) != 0) \
fprintf (FILE, "\t.align %d\n", (LOG))
/* This is how to output an assembler line
that says to advance the location counter by SIZE bytes. */
-#define ASM_OUTPUT_IDENT(FILE, NAME) \
- fprintf(FILE, "%s\t \"%s\"\n", IDENT_ASM_OP, NAME)
+#define ASM_OUTPUT_IDENT(FILE, NAME) \
+ fprintf(FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME)
#define ASM_OUTPUT_SKIP(FILE, SIZE) \
fprintf (FILE, "\t.space %d\n", (SIZE))
/* This says how to output an assembler line
to define a global common symbol. */
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
+#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
+( fputs ("\t.comm ", (FILE)), \
+ assemble_name ((FILE), (NAME)), \
fprintf ((FILE), ",%d\n", (SIZE)))
+/* This says how to output the assembler to define a global
+ uninitialized but not common symbol.
+ Try to use asm_output_bss to implement this macro. */
+
+#define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ROUNDED) \
+ asm_output_bss ((FILE), (DECL), (NAME), (SIZE), (ROUNDED))
+
/* This says how to output an assembler line
to define a local common symbol. */
#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE,X,CODE)
/* Print a memory operand whose address is X, on file FILE.
- This uses a function in output-vax.c. */
+ This uses a function in h8300.c. */
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
-/* Define this macro if you want to implement any pragmas. If defined, it
- should be a C statement to be executed when #pragma is seen. The
- argument STREAM is the stdio input stream from which the source
- text can be read. CH is the first character after the #pragma. The
- statement should execute a `return' with the terminating character found
- (newline or EOF). */
-#define HANDLE_PRAGMA(FILE, CH) return handle_pragma (FILE, CH)
+/* H8300 specific pragmas. */
+#define REGISTER_TARGET_PRAGMAS(PFILE) do { \
+ cpp_register_pragma (PFILE, 0, "saveall", h8300_pr_saveall); \
+ cpp_register_pragma (PFILE, 0, "interrupt", h8300_pr_interrupt); \
+} while (0)
#define FINAL_PRESCAN_INSN(insn, operand, nop) final_prescan_insn (insn, operand,nop)
/* Perform target dependent optabs initialization. */
-#define INIT_TARGET_OPTABS \
- do { \
- smul_optab->handlers[(int) HImode].libfunc \
- = gen_rtx (SYMBOL_REF, Pmode, MULHI3_LIBCALL); \
- sdiv_optab->handlers[(int) HImode].libfunc \
- = gen_rtx (SYMBOL_REF, Pmode, DIVHI3_LIBCALL); \
- udiv_optab->handlers[(int) HImode].libfunc \
- = gen_rtx (SYMBOL_REF, Pmode, UDIVHI3_LIBCALL); \
- smod_optab->handlers[(int) HImode].libfunc \
- = gen_rtx (SYMBOL_REF, Pmode, MODHI3_LIBCALL); \
- umod_optab->handlers[(int) HImode].libfunc \
- = gen_rtx (SYMBOL_REF, Pmode, UMODHI3_LIBCALL); \
+#define INIT_TARGET_OPTABS \
+ do { \
+ smul_optab->handlers[(int) HImode].libfunc \
+ = init_one_libfunc (MULHI3_LIBCALL); \
+ sdiv_optab->handlers[(int) HImode].libfunc \
+ = init_one_libfunc (DIVHI3_LIBCALL); \
+ udiv_optab->handlers[(int) HImode].libfunc \
+ = init_one_libfunc (UDIVHI3_LIBCALL); \
+ smod_optab->handlers[(int) HImode].libfunc \
+ = init_one_libfunc (MODHI3_LIBCALL); \
+ umod_optab->handlers[(int) HImode].libfunc \
+ = init_one_libfunc (UMODHI3_LIBCALL); \
} while (0)
#define MOVE_RATIO 3
-/* Declarations for functions used in insn-output.c. */
-char *emit_a_shift ();
-
-
+#endif /* GCC_H8300_H */
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