;; -*- Mode: Scheme -*-
;; Machine description for GNU compiler,
;; for ATMEL AVR micro controllers.
-;; Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007
+;; Free Software Foundation, Inc.
;; Contributed by Denis Chertykov (denisc@overta.ru)
-;; This file is part of GNU CC.
+;; This file is part of GCC.
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING. If not, write to
-;; the Free Software Foundation, 59 Temple Place - Suite 330,
-;; Boston, MA 02111-1307, USA.
+;; along with GCC; see the file COPYING. If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
;; Special characters after '%':
;; A No effect (add 0).
;; j Branch condition.
;; k Reverse branch condition.
;; o Displacement for (mem (plus (reg) (const_int))) operands.
+;; p POST_INC or PRE_DEC address as a pointer (X, Y, Z)
+;; r POST_INC or PRE_DEC address as a register (r26, r28, r30)
;; ~ Output 'r' if not AVR_MEGA.
;; UNSPEC usage:
;; 0 Length of a string, see "strlenhi".
-;; 1 Read from a word address in program memory, see "casesi".
-
+;; 1 Jump by register pair Z or by table addressed by Z, see "casesi".
+
+(define_constants
+ [(REG_X 26)
+ (REG_Y 28)
+ (REG_Z 30)
+ (REG_W 24)
+ (REG_SP 32)
+ (TMP_REGNO 0) ; temporary register r0
+ (ZERO_REGNO 1) ; zero register r1
+ (UNSPEC_STRLEN 0)
+ (UNSPEC_INDEX_JMP 1)])
+
+(include "predicates.md")
+(include "constraints.md")
+
;; Condition code settings.
(define_attr "cc" "none,set_czn,set_zn,set_n,compare,clobber"
(const_string "none"))
-(define_attr "type" "branch,branch1,arith"
+(define_attr "type" "branch,branch1,arith,xcall"
(const_string "arith"))
-(define_attr "mcu_enhanced" "yes,no"
- (const (if_then_else (symbol_ref "AVR_ENHANCED")
+(define_attr "mcu_have_movw" "yes,no"
+ (const (if_then_else (symbol_ref "AVR_HAVE_MOVW")
(const_string "yes")
(const_string "no"))))
(le (minus (pc) (match_dup 0))
(const_int 2043)))
(const_int 3)
- (const_int 4)))]
+ (const_int 4)))
+ (eq_attr "type" "xcall")
+ (if_then_else (eq_attr "mcu_mega" "no")
+ (const_int 1)
+ (const_int 2))]
(const_int 2)))
(define_insn "*pop1"
[(set_attr "length" "5")])
(define_insn "*pushqi"
- [(set (mem:QI (post_dec (reg:HI 32)))
- (match_operand:QI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], QImode))"
+ [(set (mem:QI (post_dec (reg:HI REG_SP)))
+ (match_operand:QI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %0
push __zero_reg__"
(define_insn "*pushhi"
- [(set (mem:HI (post_dec (reg:HI 32)))
- (match_operand:HI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], HImode))"
+ [(set (mem:HI (post_dec (reg:HI REG_SP)))
+ (match_operand:HI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %B0\;push %A0
push __zero_reg__\;push __zero_reg__"
[(set_attr "length" "2,2")])
(define_insn "*pushsi"
- [(set (mem:SI (post_dec (reg:HI 32)))
- (match_operand:SI 0 "nonmemory_operand" "r,L"))]
- "(operands[0] == const0_rtx || register_operand (operands[0], SImode))"
+ [(set (mem:SI (post_dec (reg:HI REG_SP)))
+ (match_operand:SI 0 "reg_or_0_operand" "r,L"))]
+ ""
"@
push %D0\;push %C0\;push %B0\;push %A0
push __zero_reg__\;push __zero_reg__\;push __zero_reg__\;push __zero_reg__"
[(set_attr "length" "4,4")])
(define_insn "*pushsf"
- [(set (mem:SF (post_dec (reg:HI 32)))
+ [(set (mem:SF (post_dec (reg:HI REG_SP)))
(match_operand:SF 0 "register_operand" "r"))]
""
"push %D0
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "general_operand" ""))]
""
- "/* One of the ops has to be in a register */
+ "/* One of the ops has to be in a register. */
if (!register_operand(operand0, QImode)
&& ! (register_operand(operand1, QImode) || const0_rtx == operand1))
operands[1] = copy_to_mode_reg(QImode, operand1);
(define_peephole2
[(match_scratch:QI 2 "d")
- (set (match_operand:QI 0 "register_operand" "")
+ (set (match_operand:QI 0 "l_register_operand" "")
(match_operand:QI 1 "immediate_operand" ""))]
"(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ && operands[1] != const1_rtx
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
"if (!avr_peep2_scratch_safe (operands[2]))
""
"
{
- /* One of the ops has to be in a register */
+ /* One of the ops has to be in a register. */
if (!register_operand(operand0, HImode)
&& !(register_operand(operand1, HImode) || const0_rtx == operands[1]))
{
(define_peephole2
[(match_scratch:QI 2 "d")
- (set (match_operand:HI 0 "register_operand" "")
- (match_operand:HI 1 "immediate_operand" ""))]
- "(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ (set (match_operand:HI 0 "l_register_operand" "")
+ (match_operand:HI 1 "immediate_operand" ""))]
+ "(operands[1] != const0_rtx
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
"if (!avr_peep2_scratch_safe (operands[2]))
(define_peephole2
[(match_scratch:QI 2 "d")
- (set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "immediate_operand" ""))]
+ (set (match_operand:SI 0 "l_register_operand" "")
+ (match_operand:SI 1 "immediate_operand" ""))]
"(operands[1] != const0_rtx
- && test_hard_reg_class (NO_LD_REGS, operands[0]))"
+ && operands[1] != constm1_rtx)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))])]
"if (!avr_peep2_scratch_safe (operands[2]))
;;=========================================================================
;; move string (like memcpy)
+;; implement as RTL loop
-(define_expand "movstrhi"
+(define_expand "movmemhi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:HI 2 "const_int_operand" ""))
- (use (match_operand:HI 3 "const_int_operand" ""))
- (clobber (match_dup 4))
- (clobber (match_dup 5))
- (clobber (match_dup 6))])]
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand:HI 2 "const_int_operand" ""))
+ (use (match_operand:HI 3 "const_int_operand" ""))])]
""
"{
- rtx addr0, addr1;
- int cnt8;
+ int prob;
+ HOST_WIDE_INT count;
+ enum machine_mode mode;
+ rtx label = gen_label_rtx ();
+ rtx loop_reg;
+ rtx jump;
+
+ /* Copy pointers into new psuedos - they will be changed. */
+ rtx addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
+ rtx addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
+
+ /* Create rtx for tmp register - we use this as scratch. */
+ rtx tmp_reg_rtx = gen_rtx_REG (QImode, TMP_REGNO);
if (GET_CODE (operands[2]) != CONST_INT)
FAIL;
- cnt8 = byte_immediate_operand (operands[2], GET_MODE (operands[2]));
- operands[2] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[2]);
- operands[4] = operands[2];
- addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
- addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
-
- operands[5] = addr0;
- operands[6] = addr1;
+ count = INTVAL (operands[2]);
+ if (count <= 0)
+ FAIL;
- operands[0] = gen_rtx (MEM, BLKmode, addr0);
- operands[1] = gen_rtx (MEM, BLKmode, addr1);
+ /* Work out branch probability for latter use. */
+ prob = REG_BR_PROB_BASE - REG_BR_PROB_BASE / count;
+
+ /* See if constant fit 8 bits. */
+ mode = (count < 0x100) ? QImode : HImode;
+ /* Create loop counter register. */
+ loop_reg = copy_to_mode_reg (mode, gen_int_mode (count, mode));
+
+ /* Now create RTL code for move loop. */
+ /* Label at top of loop. */
+ emit_label (label);
+
+ /* Move one byte into scratch and inc pointer. */
+ emit_move_insn (tmp_reg_rtx, gen_rtx_MEM (QImode, addr1));
+ emit_move_insn (addr1, gen_rtx_PLUS (Pmode, addr1, const1_rtx));
+
+ /* Move to mem and inc pointer. */
+ emit_move_insn (gen_rtx_MEM (QImode, addr0), tmp_reg_rtx);
+ emit_move_insn (addr0, gen_rtx_PLUS (Pmode, addr0, const1_rtx));
+
+ /* Decrement count. */
+ emit_move_insn (loop_reg, gen_rtx_PLUS (mode, loop_reg, constm1_rtx));
+
+ /* Compare with zero and jump if not equal. */
+ emit_cmp_and_jump_insns (loop_reg, const0_rtx, NE, NULL_RTX, mode, 1,
+ label);
+ /* Set jump probability based on loop count. */
+ jump = get_last_insn ();
+ REG_NOTES (jump) = gen_rtx_EXPR_LIST (REG_BR_PROB,
+ GEN_INT (prob),
+ REG_NOTES (jump));
+ DONE;
}")
-(define_insn "*movstrqi_insn"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
- (mem:BLK (match_operand:HI 1 "register_operand" "e")))
- (use (match_operand:QI 2 "register_operand" "r"))
- (use (match_operand:QI 3 "const_int_operand" "i"))
- (clobber (match_dup 2))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "ld __tmp_reg__,%a1+
- st %a0+,__tmp_reg__
- dec %2
- brne _PC_-8"
- [(set_attr "length" "4")
- (set_attr "cc" "clobber")])
-
-(define_insn "*movstrhi"
- [(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
- (mem:BLK (match_operand:HI 1 "register_operand" "e,e")))
- (use (match_operand:HI 2 "register_operand" "!w,d"))
- (use (match_operand:HI 3 "const_int_operand" ""))
- (clobber (match_dup 2))
- (clobber (match_dup 0))
- (clobber (match_dup 1))]
- ""
- "*{
- if (which_alternative==0)
- return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
- AS2 (st,%a0+,__tmp_reg__) CR_TAB
- AS2 (sbiw,%A2,1) CR_TAB
- AS1 (brne,_PC_-8));
- else
- return (AS2 (ld,__tmp_reg__,%a1+) CR_TAB
- AS2 (st,%a0+,__tmp_reg__) CR_TAB
- AS2 (subi,%A2,1) CR_TAB
- AS2 (sbci,%B2,0) CR_TAB
- AS1 (brne,_PC_-10));
-}"
- [(set_attr "length" "4,5")
- (set_attr "cc" "clobber,clobber")])
-
-;; =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0 =0
-;; memset (%0, 0, %1)
+;; =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2 =%2
+;; memset (%0, %2, %1)
-(define_expand "clrstrhi"
+(define_expand "setmemhi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (const_int 0))
+ (match_operand 2 "const_int_operand" ""))
(use (match_operand:HI 1 "const_int_operand" ""))
- (use (match_operand:HI 2 "const_int_operand" "n"))
- (clobber (match_dup 3))
- (clobber (match_dup 4))])]
+ (use (match_operand:HI 3 "const_int_operand" "n"))
+ (clobber (match_scratch:HI 4 ""))
+ (clobber (match_dup 5))])]
""
"{
rtx addr0;
int cnt8;
+ enum machine_mode mode;
+
+ /* If value to set is not zero, use the library routine. */
+ if (operands[2] != const0_rtx)
+ FAIL;
if (GET_CODE (operands[1]) != CONST_INT)
FAIL;
cnt8 = byte_immediate_operand (operands[1], GET_MODE (operands[1]));
- operands[1] = copy_to_mode_reg (cnt8 ? QImode : HImode, operands[1]);
- operands[3] = operands[1];
-
+ mode = cnt8 ? QImode : HImode;
+ operands[5] = gen_rtx_SCRATCH (mode);
+ operands[1] = copy_to_mode_reg (mode,
+ gen_int_mode (INTVAL (operands[1]), mode));
addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
- operands[4] = addr0;
-
- operands[0] = gen_rtx (MEM, BLKmode, addr0);
+ operands[0] = gen_rtx_MEM (BLKmode, addr0);
}")
-(define_insn "*clrstrqi"
+(define_insn "*clrmemqi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e"))
(const_int 0))
(use (match_operand:QI 1 "register_operand" "r"))
(use (match_operand:QI 2 "const_int_operand" "n"))
- (clobber (match_dup 1))
- (clobber (match_dup 0))]
+ (clobber (match_scratch:HI 3 "=0"))
+ (clobber (match_scratch:QI 4 "=1"))]
""
"st %a0+,__zero_reg__
dec %1
- brne _PC_-6"
+ brne .-6"
[(set_attr "length" "3")
(set_attr "cc" "clobber")])
-(define_insn "*clrstrhi"
+(define_insn "*clrmemhi"
[(set (mem:BLK (match_operand:HI 0 "register_operand" "e,e"))
(const_int 0))
(use (match_operand:HI 1 "register_operand" "!w,d"))
(use (match_operand:HI 2 "const_int_operand" "n,n"))
- (clobber (match_dup 1))
- (clobber (match_dup 0))]
+ (clobber (match_scratch:HI 3 "=0,0"))
+ (clobber (match_scratch:HI 4 "=1,1"))]
""
"*{
if (which_alternative==0)
return (AS2 (st,%a0+,__zero_reg__) CR_TAB
AS2 (sbiw,%A1,1) CR_TAB
- AS1 (brne,_PC_-6));
+ AS1 (brne,.-6));
else
return (AS2 (st,%a0+,__zero_reg__) CR_TAB
AS2 (subi,%A1,1) CR_TAB
AS2 (sbci,%B1,0) CR_TAB
- AS1 (brne,_PC_-8));
+ AS1 (brne,.-8));
}"
[(set_attr "length" "3,4")
(set_attr "cc" "clobber,clobber")])
[(set (match_dup 4)
(unspec:HI [(match_operand:BLK 1 "memory_operand" "")
(match_operand:QI 2 "const_int_operand" "")
- (match_operand:HI 3 "immediate_operand" "")] 0))
+ (match_operand:HI 3 "immediate_operand" "")]
+ UNSPEC_STRLEN))
(set (match_dup 4) (plus:HI (match_dup 4)
(const_int -1)))
(set (match_operand:HI 0 "register_operand" "")
if (! (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0))
FAIL;
addr = copy_to_mode_reg (Pmode, XEXP (operands[1],0));
- operands[1] = gen_rtx (MEM, BLKmode, addr);
+ operands[1] = gen_rtx_MEM (BLKmode, addr);
operands[5] = addr;
operands[4] = gen_reg_rtx (HImode);
}")
[(set (match_operand:HI 0 "register_operand" "=e")
(unspec:HI [(mem:BLK (match_operand:HI 1 "register_operand" "%0"))
(const_int 0)
- (match_operand:HI 2 "immediate_operand" "i")] 0))]
+ (match_operand:HI 2 "immediate_operand" "i")]
+ UNSPEC_STRLEN))]
""
"ld __tmp_reg__,%a0+
tst __tmp_reg__
- brne _PC_-6"
+ brne .-6"
[(set_attr "length" "3")
(set_attr "cc" "clobber")])
(match_operand:QI 2 "register_operand" "")))]
""
"{
- if (!AVR_ENHANCED)
+ if (!AVR_HAVE_MUL)
{
emit_insn (gen_mulqi3_call (operands[0], operands[1], operands[2]));
DONE;
[(set (match_operand:QI 0 "register_operand" "=r")
(mult:QI (match_operand:QI 1 "register_operand" "r")
(match_operand:QI 2 "register_operand" "r")))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %1,%2
mov %0,r0
clr r1"
(define_insn "*mulqi3_call"
[(set (reg:QI 24) (mult:QI (reg:QI 24) (reg:QI 22)))
(clobber (reg:QI 22))]
- "!AVR_ENHANCED"
+ "!AVR_HAVE_MUL"
"%~call __mulqi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "d"))
(sign_extend:HI (match_operand:QI 2 "register_operand" "d"))))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"muls %1,%2
movw %0,r0
clr r1"
[(set (match_operand:HI 0 "register_operand" "=r")
(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
(zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %1,%2
movw %0,r0
clr r1"
""
"
{
- if (!AVR_ENHANCED)
+ if (!AVR_HAVE_MUL)
{
emit_insn (gen_mulhi3_call (operands[0], operands[1], operands[2]));
DONE;
[(set (match_operand:HI 0 "register_operand" "=&r")
(mult:HI (match_operand:HI 1 "register_operand" "r")
(match_operand:HI 2 "register_operand" "r")))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"mul %A1,%A2
movw %0,r0
mul %A1,%B2
[(set (reg:HI 24) (mult:HI (reg:HI 24) (reg:HI 22)))
(clobber (reg:HI 22))
(clobber (reg:QI 21))]
- "!AVR_ENHANCED"
+ "!AVR_HAVE_MUL"
"%~call __mulhi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
;; Operand 2 (reg:SI 18) not clobbered on the enhanced core.
(clobber (reg:HI 26))
(clobber (reg:HI 30))])
(set (match_operand:SI 0 "register_operand" "") (reg:SI 22))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"")
(define_insn "*mulsi3_call"
[(set (reg:SI 22) (mult:SI (reg:SI 22) (reg:SI 18)))
(clobber (reg:HI 26))
(clobber (reg:HI 30))]
- "AVR_ENHANCED"
+ "AVR_HAVE_MUL"
"%~call __mulsi3"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
; / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / % / %
(clobber (reg:QI 23))]
""
"%~call __divmodqi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodqi4"
(clobber (reg:QI 23))]
""
"%~call __udivmodqi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "divmodhi4"
(clobber (reg:QI 21))]
""
"%~call __divmodhi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodhi4"
(clobber (reg:QI 21))]
""
"%~call __udivmodhi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "divmodsi4"
(clobber (reg:HI 30))]
""
"%~call __divmodsi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
(define_expand "udivmodsi4"
(clobber (reg:HI 30))]
""
"%~call __udivmodsi4"
- [(set (attr "length") (if_then_else (eq_attr "mcu_mega" "no")
- (const_int 1)
- (const_int 2)))
+ [(set_attr "type" "xcall")
(set_attr "cc" "clobber")])
;&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
;; arithmetic shift left
(define_insn "ashlqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
- (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
""
"* return ashlqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,4,6,9")
- (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
+ [(set_attr "length" "5,0,1,2,4,6,9")
+ (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
(define_insn "ashlhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashlhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,2,4,10,10")
- (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "6,0,2,2,4,10,10")
+ (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashlsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,4,8,10,12")
- (set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "8,0,4,4,8,10,12")
+ (set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
FAIL;")
(define_insn "*ashlhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (ashift:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return ashlhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,2,4,10")
- (set_attr "cc" "set_n,clobber,set_n,clobber")])
+ [(set_attr "length" "0,2,2,4,10")
+ (set_attr "cc" "none,set_n,clobber,set_n,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
FAIL;")
(define_insn "*ashlsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashift:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return ashlsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "set_n,clobber,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,set_n,clobber,clobber")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; arithmetic shift right
(define_insn "ashrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
- (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
+ (ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
""
"* return ashrqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,5,9")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "5,0,1,2,5,9")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
(define_insn "ashrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,4,4,10,10")
- (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
+ [(set_attr "length" "6,0,2,4,4,10,10")
+ (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return ashrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,6,8,10,12")
- (set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
+ [(set_attr "length" "8,0,4,6,8,10,12")
+ (set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
FAIL;")
(define_insn "*ashrhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return ashrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,4,4,10")
- (set_attr "cc" "clobber,set_n,clobber,clobber")])
+ [(set_attr "length" "0,2,4,4,10")
+ (set_attr "cc" "none,clobber,set_n,clobber,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
FAIL;")
(define_insn "*ashrsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return ashrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "clobber,set_n,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,clobber,set_n,clobber")])
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
;; logical shift right
(define_insn "lshrqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
- (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
+ [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
+ (lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
""
"* return lshrqi3_out (insn, operands, NULL);"
- [(set_attr "length" "5,1,2,4,6,9")
- (set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
+ [(set_attr "length" "5,0,1,2,4,6,9")
+ (set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
(define_insn "lshrhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return lshrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "6,2,2,4,10,10")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "6,0,2,2,4,10,10")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
- (match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
+ (match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
""
"* return lshrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "8,4,4,8,10,12")
- (set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "8,0,4,4,8,10,12")
+ (set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
;; Optimize if a scratch register from LD_REGS happens to be available.
FAIL;")
(define_insn "*lshrhi3_const"
- [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
- (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
- (match_operand:QI 2 "const_int_operand" "P,O,K,n")))
- (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
+ [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
+ (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
"reload_completed"
"* return lshrhi3_out (insn, operands, NULL);"
- [(set_attr "length" "2,2,4,10")
- (set_attr "cc" "clobber,clobber,clobber,clobber")])
+ [(set_attr "length" "0,2,2,4,10")
+ (set_attr "cc" "none,clobber,clobber,clobber,clobber")])
(define_peephole2
[(match_scratch:QI 3 "d")
FAIL;")
(define_insn "*lshrsi3_const"
- [(set (match_operand:SI 0 "register_operand" "=r,r,r")
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
- (match_operand:QI 2 "const_int_operand" "P,O,n")))
- (clobber (match_scratch:QI 3 "=X,X,&d"))]
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
+ (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
+ (match_operand:QI 2 "const_int_operand" "L,P,O,n")))
+ (clobber (match_scratch:QI 3 "=X,X,X,&d"))]
"reload_completed"
"* return lshrsi3_out (insn, operands, NULL);"
- [(set_attr "length" "4,4,10")
- (set_attr "cc" "clobber,clobber,clobber")])
+ [(set_attr "length" "0,4,4,10")
+ (set_attr "cc" "none,clobber,clobber,clobber")])
;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
;; abs
[(set_attr_alternative "length"
[(const_int 7)
(const_int 8)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 7)
(const_int 8))])
(set_attr "cc" "set_czn,set_n,set_czn")])
{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;sbrc %B0,7\;com %C0\;mov %D0,%C0"
[(set_attr_alternative "length"
[(const_int 4)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 5)
(const_int 6))])
(set_attr "cc" "set_n,set_n")])
{mov %A0,%A1\;mov %B0,%B1|movw %A0,%A1}\;clr %C0\;clr %D0"
[(set_attr_alternative "length"
[(const_int 2)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 3)
(const_int 4))])
(set_attr "cc" "set_n,set_n")])
[(set (cc0)
(compare (sign_extend:HI
(match_operand:QI 0 "register_operand" "d"))
- (match_operand:HI 1 "immediate_operand" "M")))]
- ""
+ (match_operand:HI 1 "const_int_operand" "n")))]
+ "INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) <= 127"
"cpi %0,lo8(%1)"
[(set_attr "cc" "compare")
(set_attr "length" "1")])
(define_insn "*sbrx_branch"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "eqne_operator"
[(zero_extract
(match_operand:QI 1 "register_operand" "r")
(const_int 1)
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE"
+ ""
"* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(define_insn "*sbrx_and_branchhi"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "eqne_operator"
[(and:HI
(match_operand:HI 1 "register_operand" "r")
- (match_operand:HI 2 "const_int_operand" "n"))
+ (match_operand:HI 2 "single_one_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && exact_log2 (INTVAL (operands[2]) & 0xffff) >= 0"
+ ""
"* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(define_insn "*sbrx_and_branchsi"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "eqne_operator"
[(and:SI
(match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "n"))
+ (match_operand:SI 2 "single_one_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && exact_log2 (INTVAL (operands[2]) & 0xffffffff) >= 0"
+ ""
"* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(const_int 0))
(label_ref (match_dup 1))
(pc)))]
- "operands[2] = GEN_INT (0x80000000);")
+ "operands[2] = GEN_INT (-2147483647 - 1);")
(define_peephole2
[(set (cc0) (match_operand:SI 0 "register_operand" ""))
(const_int 0))
(label_ref (match_dup 1))
(pc)))]
- "operands[2] = GEN_INT (0x80000000);")
+ "operands[2] = GEN_INT (-2147483647 - 1);")
;; ************************************************************************
;; Implementation of conditional jumps here.
(define_insn "branch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
+ (if_then_else (match_operator 1 "simple_comparison_operator"
[(cc0)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
[(set_attr "type" "branch")
(define_insn "difficult_branch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator"
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
[(cc0)
(const_int 0)])
(label_ref (match_operand 0 "" ""))
(pc)))]
- "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);"
[(set_attr "type" "branch1")
(define_insn "rvbranch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator" [(cc0)
- (const_int 0)])
+ (if_then_else (match_operator 1 "simple_comparison_operator"
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
[(set_attr "type" "branch1")
(define_insn "difficult_rvbranch"
[(set (pc)
- (if_then_else (match_operator 1 "comparison_operator" [(cc0)
- (const_int 0)])
+ (if_then_else (match_operator 1 "difficult_comparison_operator"
+ [(cc0)
+ (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU
- || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)"
+ ""
"*
return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);"
[(set_attr "type" "branch")
"")
(define_insn "call_insn"
- [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,i"))
- (match_operand:HI 1 "general_operand" "X,X,X"))]
+ [(call (mem:HI (match_operand:HI 0 "nonmemory_operand" "!z,*r,s,n"))
+ (match_operand:HI 1 "general_operand" "X,X,X,X"))]
;; We don't need in saving Z register because r30,r31 is a call used registers
;; Operand 1 not used on the AVR.
"(register_operand (operands[0], HImode) || CONSTANT_P (operands[0]))"
return \"icall\";
else if (which_alternative==1)
{
- if (AVR_ENHANCED)
+ if (AVR_HAVE_MOVW)
return (AS2 (movw, r30, %0) CR_TAB
\"icall\");
else
AS2 (mov, r31, %B0) CR_TAB
\"icall\");
}
- return AS1(%~call,%c0);
+ else if (which_alternative==2)
+ return AS1(%~call,%c0);
+ return (AS2 (ldi,r30,lo8(%0)) CR_TAB
+ AS2 (ldi,r31,hi8(%0)) CR_TAB
+ \"icall\");
}"
- [(set_attr "cc" "clobber,clobber,clobber")
+ [(set_attr "cc" "clobber,clobber,clobber,clobber")
(set_attr_alternative "length"
[(const_int 1)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 2)
(const_int 3))
(if_then_else (eq_attr "mcu_mega" "yes")
(const_int 2)
- (const_int 1))])])
+ (const_int 1))
+ (const_int 3)])])
(define_insn "call_value_insn"
- [(set (match_operand 0 "register_operand" "=r,r,r")
- (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,i"))
+ [(set (match_operand 0 "register_operand" "=r,r,r,r")
+ (call (mem:HI (match_operand:HI 1 "nonmemory_operand" "!z,*r,s,n"))
;; We don't need in saving Z register because r30,r31 is a call used registers
- (match_operand:HI 2 "general_operand" "X,X,X")))]
+ (match_operand:HI 2 "general_operand" "X,X,X,X")))]
;; Operand 2 not used on the AVR.
"(register_operand (operands[0], VOIDmode) || CONSTANT_P (operands[0]))"
- "*
-{
+ "*{
if (which_alternative==0)
return \"icall\";
else if (which_alternative==1)
{
- if (AVR_ENHANCED)
+ if (AVR_HAVE_MOVW)
return (AS2 (movw, r30, %1) CR_TAB
\"icall\");
else
AS2 (mov, r31, %B1) CR_TAB
\"icall\");
}
- return AS1(%~call,%c1);
+ else if (which_alternative==2)
+ return AS1(%~call,%c1);
+ return (AS2 (ldi, r30, lo8(%1)) CR_TAB
+ AS2 (ldi, r31, hi8(%1)) CR_TAB
+ \"icall\");
}"
- [(set_attr "cc" "clobber,clobber,clobber")
+ [(set_attr "cc" "clobber,clobber,clobber,clobber")
(set_attr_alternative "length"
[(const_int 1)
- (if_then_else (eq_attr "mcu_enhanced" "yes")
+ (if_then_else (eq_attr "mcu_have_movw" "yes")
(const_int 2)
(const_int 3))
(if_then_else (eq_attr "mcu_mega" "yes")
(const_int 2)
- (const_int 1))])])
+ (const_int 1))
+ (const_int 3)])])
+
+(define_insn "return"
+ [(return)]
+ "reload_completed && avr_simple_epilogue ()"
+ "ret"
+ [(set_attr "cc" "none")
+ (set_attr "length" "1")])
(define_insn "nop"
[(const_int 0)]
;; Table made from "rjmp" instructions for <=8K devices.
(define_insn "*tablejump_rjmp"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "!z,*r")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
"!AVR_MEGA"
;; Not a prologue, but similar idea - move the common piece of code to libgcc.
(define_insn "*tablejump_lib"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
"AVR_MEGA && TARGET_CALL_PROLOGUES"
(set_attr "cc" "clobber")])
(define_insn "*tablejump_enh"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
- "AVR_MEGA && AVR_ENHANCED"
+ "AVR_MEGA && AVR_HAVE_LPMX"
"lsl r30
rol r31
lpm __tmp_reg__,Z+
(set_attr "cc" "clobber")])
(define_insn "*tablejump"
- [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")] 1))
+ [(set (pc) (unspec:HI [(match_operand:HI 0 "register_operand" "z")]
+ UNSPEC_INDEX_JMP))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_dup 0))]
"AVR_MEGA"
(set (match_dup 6)
(plus:HI (match_dup 6) (label_ref (match_operand:HI 3 "" ""))))
- (parallel [(set (pc) (unspec:HI [(match_dup 6)] 1))
+ (parallel [(set (pc) (unspec:HI [(match_dup 6)] UNSPEC_INDEX_JMP))
(use (label_ref (match_dup 3)))
(clobber (match_dup 6))])]
""
;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-;; This instructin sets Z flag
+;; This instruction sets Z flag
(define_insn "sez"
[(set (cc0) (const_int 0))]
;; Clear/set/test a single bit in I/O address space.
(define_insn "*cbi"
- [(set (mem:QI (match_operand 0 "const_int_operand" "n"))
+ [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
(and:QI (mem:QI (match_dup 0))
- (match_operand 1 "const_int_operand" "n")))]
- "avr_io_address_p (operands[0], 1 + 0x20)
- && exact_log2 (~INTVAL (operands[1]) & 0xff) >= 0"
+ (match_operand:QI 1 "single_zero_operand" "n")))]
+ "(optimize > 0)"
{
operands[2] = GEN_INT (exact_log2 (~INTVAL (operands[1]) & 0xff));
return AS2 (cbi,%0-0x20,%2);
(set_attr "cc" "none")])
(define_insn "*sbi"
- [(set (mem:QI (match_operand 0 "const_int_operand" "n"))
+ [(set (mem:QI (match_operand 0 "low_io_address_operand" "n"))
(ior:QI (mem:QI (match_dup 0))
- (match_operand 1 "const_int_operand" "n")))]
- "avr_io_address_p (operands[0], 1 + 0x20)
- && exact_log2 (INTVAL (operands[1]) & 0xff) >= 0"
+ (match_operand:QI 1 "single_one_operand" "n")))]
+ "(optimize > 0)"
{
operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1]) & 0xff));
return AS2 (sbi,%0-0x20,%2);
(define_insn "*sbix_branch"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "eqne_operator"
[(zero_extract
- (mem:QI (match_operand 1 "const_int_operand" "n"))
+ (mem:QI (match_operand 1 "low_io_address_operand" "n"))
(const_int 1)
(match_operand 2 "const_int_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && avr_io_address_p (operands[1], 1 + 0x20)"
+ "(optimize > 0)"
"* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(define_insn "*sbix_branch_bit7"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
- [(mem:QI (match_operand 1 "const_int_operand" "n"))
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "low_io_address_operand" "n"))
(const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == GE || GET_CODE (operands[0]) == LT)
- && avr_io_address_p (operands[1], 1 + 0x20)"
+ "(optimize > 0)"
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
(define_insn "*sbix_branch_tmp"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
+ (match_operator 0 "eqne_operator"
[(zero_extract
- (mem:QI (match_operand 1 "const_int_operand" "n"))
+ (mem:QI (match_operand 1 "higth_io_address_operand" "n"))
(const_int 1)
(match_operand 2 "const_int_operand" "n"))
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)
- && avr_io_address_p (operands[1], 1) && INTVAL (operands[1]) >= 0x40"
+ "(optimize > 0)"
"* return avr_out_sbxx_branch (insn, operands);"
[(set (attr "length")
(if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046))
(define_insn "*sbix_branch_tmp_bit7"
[(set (pc)
(if_then_else
- (match_operator 0 "comparison_operator"
- [(mem:QI (match_operand 1 "const_int_operand" "n"))
+ (match_operator 0 "gelt_operator"
+ [(mem:QI (match_operand 1 "higth_io_address_operand" "n"))
(const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(GET_CODE (operands[0]) == GE || GET_CODE (operands[0]) == LT)
- && avr_io_address_p (operands[1], 1) && INTVAL (operands[1]) >= 0x40"
+ "(optimize > 0)"
{
operands[3] = operands[2];
operands[2] = GEN_INT (7);
;; ************************* Peepholes ********************************
(define_peephole
- [(set (match_operand:SI 0 "register_operand" "")
+ [(set (match_operand:SI 0 "d_register_operand" "")
(plus:SI (match_dup 0)
(const_int -1)))
(parallel
[(set (cc0)
(compare (match_dup 0)
(const_int -1)))
- (clobber (match_operand:QI 1 "register_operand" ""))])
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(test_hard_reg_class (LD_REGS, operands[0])
- && test_hard_reg_class (LD_REGS, operands[1]))"
+ ""
"*
{
+ CC_STATUS_INIT;
if (test_hard_reg_class (ADDW_REGS, operands[0]))
output_asm_insn (AS2 (sbiw,%0,1) CR_TAB
AS2 (sbc,%C0,__zero_reg__) CR_TAB
case 1:
return AS1 (brcc,%2);
case 2:
- return (AS1 (brcs,_PC_+2) CR_TAB
+ return (AS1 (brcs,.+2) CR_TAB
AS1 (rjmp,%2));
}
- return (AS1 (brcs,_PC_+4) CR_TAB
+ return (AS1 (brcs,.+4) CR_TAB
AS1 (jmp,%2));
}")
(define_peephole
- [(set (match_operand:HI 0 "register_operand" "")
+ [(set (match_operand:HI 0 "d_register_operand" "")
(plus:HI (match_dup 0)
(const_int -1)))
(parallel
[(set (cc0)
(compare (match_dup 0)
(const_int 65535)))
- (clobber (match_operand:QI 1 "register_operand" ""))])
+ (clobber (match_operand:QI 1 "d_register_operand" ""))])
(set (pc)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))]
- "(test_hard_reg_class (LD_REGS, operands[0])
- && test_hard_reg_class (LD_REGS, operands[1]))"
+ ""
"*
{
+ CC_STATUS_INIT;
if (test_hard_reg_class (ADDW_REGS, operands[0]))
output_asm_insn (AS2 (sbiw,%0,1), operands);
else
case 1:
return AS1 (brcc,%2);
case 2:
- return (AS1 (brcs,_PC_+2) CR_TAB
+ return (AS1 (brcs,.+2) CR_TAB
AS1 (rjmp,%2));
}
- return (AS1 (brcs,_PC_+4) CR_TAB
+ return (AS1 (brcs,.+4) CR_TAB
AS1 (jmp,%2));
}")
(define_peephole
- [(set (match_operand:QI 0 "register_operand" "")
+ [(set (match_operand:QI 0 "d_register_operand" "")
(plus:QI (match_dup 0)
(const_int -1)))
(set (cc0)
(if_then_else (ne (cc0) (const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
- "test_hard_reg_class (LD_REGS, operands[0])"
+ ""
"*
{
+ CC_STATUS_INIT;
+ cc_status.value1 = operands[0];
+ cc_status.flags |= CC_OVERFLOW_UNUSABLE;
output_asm_insn (AS2 (subi,%A0,1), operands);
switch (avr_jump_mode (operands[1],insn))
{
case 1:
return AS1 (brcc,%1);
case 2:
- return (AS1 (brcs,_PC_+2) CR_TAB
+ return (AS1 (brcs,.+2) CR_TAB
AS1 (rjmp,%1));
}
- return (AS1 (brcs,_PC_+4) CR_TAB
+ return (AS1 (brcs,.+4) CR_TAB
AS1 (jmp,%1));
}")
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