const avr_addrspace_t avr_addrspace[] =
{
{ ADDR_SPACE_RAM, 0, 2, "" , 0 },
- { ADDR_SPACE_PGM, 1, 2, "__pgm", 0 },
- { ADDR_SPACE_PGM1, 1, 2, "__pgm1", 1 },
- { ADDR_SPACE_PGM2, 1, 2, "__pgm2", 2 },
- { ADDR_SPACE_PGM3, 1, 2, "__pgm3", 3 },
- { ADDR_SPACE_PGM4, 1, 2, "__pgm4", 4 },
- { ADDR_SPACE_PGM5, 1, 2, "__pgm5", 5 },
- { ADDR_SPACE_PGMX, 1, 3, "__pgmx", 0 },
+ { ADDR_SPACE_FLASH, 1, 2, "__flash", 0 },
+ { ADDR_SPACE_FLASH1, 1, 2, "__flash1", 1 },
+ { ADDR_SPACE_FLASH2, 1, 2, "__flash2", 2 },
+ { ADDR_SPACE_FLASH3, 1, 2, "__flash3", 3 },
+ { ADDR_SPACE_FLASH4, 1, 2, "__flash4", 4 },
+ { ADDR_SPACE_FLASH5, 1, 2, "__flash5", 5 },
+ { ADDR_SPACE_MEMX, 1, 3, "__memx", 0 },
{ 0 , 0, 0, NULL, 0 }
};
#define FIRST_CUM_REG 26
/* Implicit target register of LPM instruction (R0) */
-static GTY(()) rtx lpm_reg_rtx;
+extern GTY(()) rtx lpm_reg_rtx;
+rtx lpm_reg_rtx;
/* (Implicit) address register of LPM instruction (R31:R30 = Z) */
-static GTY(()) rtx lpm_addr_reg_rtx;
+extern GTY(()) rtx lpm_addr_reg_rtx;
+rtx lpm_addr_reg_rtx;
-/* Temporary register RTX (gen_rtx_REG (QImode, TMP_REGNO)) */
-static GTY(()) rtx tmp_reg_rtx;
+/* Temporary register RTX (reg:QI TMP_REGNO) */
+extern GTY(()) rtx tmp_reg_rtx;
+rtx tmp_reg_rtx;
-/* Zeroed register RTX (gen_rtx_REG (QImode, ZERO_REGNO)) */
-static GTY(()) rtx zero_reg_rtx;
+/* Zeroed register RTX (reg:QI ZERO_REGNO) */
+extern GTY(()) rtx zero_reg_rtx;
+rtx zero_reg_rtx;
+
+/* RTXs for all general purpose registers as QImode */
+extern GTY(()) rtx all_regs_rtx[32];
+rtx all_regs_rtx[32];
/* RAMPZ special function register */
-static GTY(()) rtx rampz_rtx;
+extern GTY(()) rtx rampz_rtx;
+rtx rampz_rtx;
/* RTX containing the strings "" and "e", respectively */
static GTY(()) rtx xstring_empty;
static GTY(()) rtx xstring_e;
-/* RTXs for all general purpose registers as QImode */
-static GTY(()) rtx all_regs_rtx[32];
-
-/* AVR register names {"r0", "r1", ..., "r31"} */
-static const char *const avr_regnames[] = REGISTER_NAMES;
-
/* Preprocessor macros to define depending on MCU type. */
const char *avr_extra_arch_macro;
static GTY(()) section *progmem_swtable_section;
/* Unnamed sections associated to __attribute__((progmem)) aka. PROGMEM
- or to address space __pgm*. */
+ or to address space __flash*. */
static GTY(()) section *progmem_section[6];
/* Condition for insns/expanders from avr-dimode.md. */
/* Return TRUE if DECL is a VAR_DECL located in Flash and FALSE, otherwise. */
static bool
-avr_decl_pgm_p (tree decl)
+avr_decl_flash_p (tree decl)
{
if (TREE_CODE (decl) != VAR_DECL
|| TREE_TYPE (decl) == error_mark_node)
address space and FALSE, otherwise. */
static bool
-avr_decl_pgmx_p (tree decl)
+avr_decl_memx_p (tree decl)
{
if (TREE_CODE (decl) != VAR_DECL
|| TREE_TYPE (decl) == error_mark_node)
return false;
}
- return (ADDR_SPACE_PGMX == TYPE_ADDR_SPACE (TREE_TYPE (decl)));
+ return (ADDR_SPACE_MEMX == TYPE_ADDR_SPACE (TREE_TYPE (decl)));
}
/* Return TRUE if X is a MEM rtx located in Flash and FALSE, otherwise. */
bool
-avr_mem_pgm_p (rtx x)
+avr_mem_flash_p (rtx x)
{
return (MEM_P (x)
&& !ADDR_SPACE_GENERIC_P (MEM_ADDR_SPACE (x)));
address space and FALSE, otherwise. */
bool
-avr_mem_pgmx_p (rtx x)
+avr_mem_memx_p (rtx x)
{
return (MEM_P (x)
- && ADDR_SPACE_PGMX == MEM_ADDR_SPACE (x));
+ && ADDR_SPACE_MEMX == MEM_ADDR_SPACE (x));
}
return (n_bytes > 2
&& !AVR_HAVE_LPMX
- && avr_mem_pgm_p (op));
+ && avr_mem_flash_p (op));
}
/* Return true if a value of mode MODE is read by __xload_* function. */
rtx src = operands[1];
int *real_l = l;
- if (avr_mem_pgm_p (src)
- || avr_mem_pgm_p (dest))
+ if (avr_mem_flash_p (src)
+ || avr_mem_flash_p (dest))
{
return avr_out_lpm (insn, operands, real_l);
}
gcc_assert (GET_MODE_SIZE (GET_MODE (dest)) == 2);
- if (avr_mem_pgm_p (src)
- || avr_mem_pgm_p (dest))
+ if (avr_mem_flash_p (src)
+ || avr_mem_flash_p (dest))
{
return avr_out_lpm (insn, xop, plen);
}
rtx src = operands[1];
int *real_l = l;
- if (avr_mem_pgm_p (src)
- || avr_mem_pgm_p (dest))
+ if (avr_mem_flash_p (src)
+ || avr_mem_flash_p (dest))
{
return avr_out_lpm (insn, operands, real_l);
}
rtx dest = op[0];
rtx src = op[1];
- if (avr_mem_pgm_p (src)
- || avr_mem_pgm_p (dest))
+ if (avr_mem_flash_p (src)
+ || avr_mem_flash_p (dest))
{
return avr_out_lpm (insn, op, plen);
}
if (TREE_CODE (decl) != VAR_DECL)
return 0;
- if (avr_decl_pgmx_p (decl))
+ if (avr_decl_memx_p (decl))
return 2;
- if (avr_decl_pgm_p (decl))
+ if (avr_decl_flash_p (decl))
return 1;
if (NULL_TREE
}
-/* Sanity check NODE so that all pointers targeting address space AS1
- go along with CONST qualifier. Writing to this address space should
+/* Sanity check NODE so that all pointers targeting non-generic addres spaces
+ go along with CONST qualifier. Writing to these address spaces should
be detected and complained about as early as possible. */
static bool
addr_space_t as = TYPE_ADDR_SPACE (TREE_TYPE (decl));
/* Attribute progmem puts data in generic address space.
- Set section flags as if it was in __pgm to get the right
+ Set section flags as if it was in __flash to get the right
section prefix in the remainder. */
if (ADDR_SPACE_GENERIC_P (as))
- as = ADDR_SPACE_PGM;
+ as = ADDR_SPACE_FLASH;
flags |= as * SECTION_MACH_DEP;
flags &= ~SECTION_WRITE;
patch address space. */
if (-1 == avr_progmem_p (decl, DECL_ATTRIBUTES (decl)))
- as = ADDR_SPACE_PGM;
+ as = ADDR_SPACE_FLASH;
AVR_SYMBOL_SET_ADDR_SPACE (sym, as);
}
case ADDR_SPACE_GENERIC:
return avr_legitimate_address_p (mode, x, strict);
- case ADDR_SPACE_PGM:
- case ADDR_SPACE_PGM1:
- case ADDR_SPACE_PGM2:
- case ADDR_SPACE_PGM3:
- case ADDR_SPACE_PGM4:
- case ADDR_SPACE_PGM5:
+ case ADDR_SPACE_FLASH:
+ case ADDR_SPACE_FLASH1:
+ case ADDR_SPACE_FLASH2:
+ case ADDR_SPACE_FLASH3:
+ case ADDR_SPACE_FLASH4:
+ case ADDR_SPACE_FLASH5:
switch (GET_CODE (x))
{
break;
}
- break; /* PGM */
+ break; /* FLASH */
- case ADDR_SPACE_PGMX:
+ case ADDR_SPACE_MEMX:
if (REG_P (x))
ok = (!strict
&& can_create_pseudo_p());
&& REGNO (lo) == REG_Z);
}
- break; /* PGMX */
+ break; /* MEMX */
}
if (avr_log.legitimate_address_p)
/* Up-casting from 16-bit to 24-bit pointer. */
- if (as_from != ADDR_SPACE_PGMX
- && as_to == ADDR_SPACE_PGMX)
+ if (as_from != ADDR_SPACE_MEMX
+ && as_to == ADDR_SPACE_MEMX)
{
int msb;
rtx sym = src;
address space. */
if (SYMBOL_REF == GET_CODE (sym)
- && ADDR_SPACE_PGM == AVR_SYMBOL_GET_ADDR_SPACE (sym))
+ && ADDR_SPACE_FLASH == AVR_SYMBOL_GET_ADDR_SPACE (sym))
{
- as_from = ADDR_SPACE_PGM;
+ as_from = ADDR_SPACE_FLASH;
}
/* Linearize memory: RAM has bit 23 set. */
/* Down-casting from 24-bit to 16-bit throws away the high byte. */
- if (as_from == ADDR_SPACE_PGMX
- && as_to != ADDR_SPACE_PGMX)
+ if (as_from == ADDR_SPACE_MEMX
+ && as_to != ADDR_SPACE_MEMX)
{
rtx new_src = gen_reg_rtx (Pmode);
rtx loop_reg, addr0, addr1, a_src, a_dest, insn, xas, reg_x;
rtx a_hi8 = NULL_RTX;
- if (avr_mem_pgm_p (xop[0]))
+ if (avr_mem_flash_p (xop[0]))
return false;
if (!CONST_INT_P (xop[2]))
if (PSImode == GET_MODE (a_src))
{
- gcc_assert (as == ADDR_SPACE_PGMX);
+ gcc_assert (as == ADDR_SPACE_MEMX);
loop_mode = (count < 0x100) ? QImode : HImode;
loop_reg = gen_rtx_REG (loop_mode, 24);
}
else if (!ADDR_SPACE_GENERIC_P (as))
{
- as = ADDR_SPACE_PGM;
+ as = ADDR_SPACE_FLASH;
}
addr1 = a_src;
gcc_assert (TMP_REGNO == LPM_REGNO);
- if (as != ADDR_SPACE_PGMX)
+ if (as != ADDR_SPACE_MEMX)
{
/* Load instruction ([E]LPM or LD) is known at compile time:
Do the copy-loop inline. */
avr_asm_len ("ld %6,%a1+", xop, plen, 1);
break;
- case ADDR_SPACE_PGM:
+ case ADDR_SPACE_FLASH:
if (AVR_HAVE_LPMX)
avr_asm_len ("lpm %6,%a1+", xop, plen, 1);
"adiw %1,1", xop, plen, 2);
break;
- case ADDR_SPACE_PGM1:
- case ADDR_SPACE_PGM2:
- case ADDR_SPACE_PGM3:
- case ADDR_SPACE_PGM4:
- case ADDR_SPACE_PGM5:
+ case ADDR_SPACE_FLASH1:
+ case ADDR_SPACE_FLASH2:
+ case ADDR_SPACE_FLASH3:
+ case ADDR_SPACE_FLASH4:
+ case ADDR_SPACE_FLASH5:
if (AVR_HAVE_ELPMX)
avr_asm_len ("elpm %6,%a1+", xop, plen, 1);
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