[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
(match_operand:DI 2 "const_int_operand" "n")))]
- "REG_OK_FP_BASE_P (operands[1])"
+ "REG_OK_FP_BASE_P (operands[1])
+ && INTVAL (operands[2]) >= 0
+ /* This is the largest constant an lda+ldah pair can add, minus
+ an upper bound on the displacement between SP and AP during
+ register elimination. See INITIAL_ELIMINATION_OFFSET. */
+ && INTVAL (operands[2])
+ < (0x7fff8000
+ - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
+ - ALPHA_ROUND(current_function_outgoing_args_size)
+ - (ALPHA_ROUND (get_frame_size ()
+ + max_reg_num () * UNITS_PER_WORD
+ + current_function_pretend_args_size)
+ - current_function_pretend_args_size))"
"#")
;; Don't do this if we are adjusting SP since we don't want to do it
HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
HOST_WIDE_INT rest = val - low;
- operands[3] = GEN_INT (rest);
operands[4] = GEN_INT (low);
+ if (CONST_OK_FOR_LETTER_P (rest, 'L'))
+ operands[3] = GEN_INT (rest);
+ else if (! no_new_pseudos)
+ {
+ operands[3] = gen_reg_rtx (DImode);
+ emit_move_insn (operands[3], operands[2]);
+ emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
+ DONE;
+ }
+ else
+ FAIL;
}")
(define_insn ""
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_expand "addtf3"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand 1 "general_operand" ""))
+ (use (match_operand 2 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
+
;; Define conversion operators between DFmode and SImode, using the cvtql
;; instruction. To allow combine et al to do useful things, we keep the
;; operation as a unit until after reload, at which point we split the
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_expand "fix_trunctfdi2"
+ [(use (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:TF 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_expand "floatditf2"
+ [(use (match_operand:TF 0 "register_operand" ""))
+ (use (match_operand:DI 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
+
+(define_expand "floatunsditf2"
+ [(use (match_operand:TF 0 "register_operand" ""))
+ (use (match_operand:DI 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
+
(define_expand "extendsfdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:SF 1 "nonimmediate_operand" ""))]
[(set_attr "type" "fcpys,fld,fst")
(set_attr "trap" "yes")])
+(define_expand "extenddftf2"
+ [(use (match_operand:TF 0 "register_operand" ""))
+ (use (match_operand:DF 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_expand "trunctfdf2"
+ [(use (match_operand:DF 0 "register_operand" ""))
+ (use (match_operand:TF 1 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
[(set_attr "type" "fdiv")
(set_attr "trap" "yes")])
+(define_expand "divtf3"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand 1 "general_operand" ""))
+ (use (match_operand 2 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_arith (DIV, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
[(set_attr "type" "fmul")
(set_attr "trap" "yes")])
+(define_expand "multf3"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand 1 "general_operand" ""))
+ (use (match_operand 2 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_arith (MULT, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
+(define_expand "subtf3"
+ [(use (match_operand 0 "register_operand" ""))
+ (use (match_operand 1 "general_operand" ""))
+ (use (match_operand 2 "general_operand" ""))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
+
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=&f")
(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
DONE;
}")
+(define_expand "cmptf"
+ [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
+ (match_operand:TF 1 "general_operand" "")))]
+ "TARGET_HAS_XFLOATING_LIBS"
+ "
+{
+ alpha_compare.op0 = operands[0];
+ alpha_compare.op1 = operands[1];
+ alpha_compare.fp_p = 1;
+ DONE;
+}")
+
(define_expand "cmpdi"
[(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
(match_operand:DI 1 "reg_or_8bit_operand" "")))]
emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
emit_insn (gen_cmpdi (tmp, want));
emit_jump_insn (gen_bgtu (loop_label));
- if (obey_regdecls)
- gen_rtx_USE (VOIDmode, tmp);
memref = gen_rtx_MEM (DImode, want);
MEM_VOLATILE_P (memref) = 1;
"! TARGET_OPEN_VMS"
"
{
- current_function->machine->eh_epilogue_sp_ofs = operands[1];
+ cfun->machine->eh_epilogue_sp_ofs = operands[1];
if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
{
rtx ra = gen_rtx_REG (Pmode, 26);
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