(sign_extend:DI (match_dup 1)))]
"")
-;; Don't say we have addsi3 if optimizing. This generates better code. We
-;; have the anonymous addsi3 pattern below in case combine wants to make it.
-(define_expand "addsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
- (match_operand:SI 2 "add_operand" "")))]
- "! optimize"
- "")
-
-(define_insn "*addsi_internal"
+(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
(match_operand:SI 2 "add_operand" "rI,O,K,L")))]
""
"subqv $31,%1,%0")
-(define_expand "subsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
- (match_operand:SI 2 "reg_or_8bit_operand" "")))]
- "! optimize"
- "")
-
-(define_insn "*subsi_internal"
+(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(match_operand:DF 2 "reg_or_0_operand" "fG")
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
-(define_insn "*cmpdf_ieee_ext1"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
+ "TARGET_FP"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext2"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_0_operand" "fG")
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext3"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:DF 1 "reg_or_0_operand" "fG,0")
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:SF 1 "reg_or_0_operand" "fG,0")
(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{
operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode);
(set (match_operand:SF 0 "register_operand" "")
(if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
{
operands[3] = gen_reg_rtx (DFmode);
operands[4] = CONST0_RTX (DFmode);
(match_dup 4)))]
{
if (can_create_pseudo_p ())
- operands[5] = gen_reg_rtx (DImode);
+ operands[5] = gen_reg_rtx (SImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
})
(match_dup 4))))]
{
if (can_create_pseudo_p ())
- operands[5] = gen_reg_rtx (DImode);
+ operands[5] = gen_reg_rtx (SImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
- operands[5] = operands[0];
+ operands[5] = gen_rtx_REG (SImode, REGNO (operands[0]));
})
(define_insn_and_split "*cmp_ssub_di"
(match_dup 4)))]
{
if (can_create_pseudo_p ())
- operands[5] = gen_reg_rtx (DImode);
+ operands[5] = gen_reg_rtx (SImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
operands[5] = operands[0];
})
(match_dup 4))))]
{
if (can_create_pseudo_p ())
- operands[5] = gen_reg_rtx (DImode);
+ operands[5] = gen_reg_rtx (SImode);
else if (reg_overlap_mentioned_p (operands[5], operands[4]))
- operands[5] = operands[0];
+ operands[5] = gen_rtx_REG (SImode, REGNO (operands[0]));
})
\f
;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
"jmp $31,(%0),0"
[(set_attr "type" "ibr")])
-;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
+;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't
;; want to have to include pal.h in our .s file.
(define_insn "imb"
[(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
return "call_pal 0x9f";
}
[(set_attr "type" "callpal")])
+
+;; Special builtins for establishing and reverting VMS condition handlers.
+
+(define_expand "builtin_establish_vms_condition_handler"
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))
+ (use (match_operand:DI 1 "address_operand" ""))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ alpha_expand_builtin_establish_vms_condition_handler (operands[0],
+ operands[1]);
+})
+
+(define_expand "builtin_revert_vms_condition_handler"
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ alpha_expand_builtin_revert_vms_condition_handler (operands[0]);
+})
\f
;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since
(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
(const_int -8))))
(set (match_operand:DI 2 "register_operand" "")
- (plus:DI (match_dup 0) (const_int 1)))
+ (plus:DI (match_dup 5) (const_int 1)))
(set (match_dup 3)
(and:DI (not:DI (ashift:DI
(const_int 65535)
(set (mem:DI (and:DI (match_dup 0) (const_int -8)))
(match_dup 4))]
"WORDS_BIG_ENDIAN"
- "")
+ "operands[5] = force_reg (DImode, operands[0]);")
\f
;; Here are the define_expand's for QI and HI moves that use the above
;; patterns. We have the normal sets, plus the ones that need scratch
"br $27,$LSJ%=\n$LSJ%=:"
[(set_attr "type" "ibr")])
+;; When flag_reorder_blocks_and_partition is in effect, compiler puts
+;; exception landing pads in a cold section. To prevent inter-section offset
+;; calculation, a jump to original landing pad is emitted in the place of the
+;; original landing pad. Since landing pad is moved, RA-relative GP
+;; calculation in the prologue of landing pad breaks. To solve this problem,
+;; we use alternative GP load approach, as in the case of TARGET_LD_BUGGY_LDGP.
+
(define_expand "exception_receiver"
[(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
"TARGET_ABI_OSF"
{
- if (TARGET_LD_BUGGY_LDGP)
+ if (TARGET_LD_BUGGY_LDGP || flag_reorder_blocks_and_partition)
operands[0] = alpha_gp_save_rtx ();
else
operands[0] = const0_rtx;
(define_insn "*exception_receiver_2"
[(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
- "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
+ "TARGET_ABI_OSF
+ && (TARGET_LD_BUGGY_LDGP || flag_reorder_blocks_and_partition)"
"ldq $29,%0"
[(set_attr "type" "ild")])
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