/* Definitions of target machine for GNU compiler, for DEC Alpha.
- Copyright (C) 1992, 93-99, 2000 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GNU CC.
#define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
#define WORD_SWITCH_TAKES_ARG(STR) \
- (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
- || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
- || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
- || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
- || !strcmp (STR, "isystem"))
+ (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
/* Print subsidiary information on the compiler version in use. */
#define TARGET_VERSION
#define MASK_CIX (1 << 11)
#define TARGET_CIX (target_flags & MASK_CIX)
-/* This means that the processor is an EV5, EV56, or PCA56. This is defined
- only in TARGET_CPU_DEFAULT. */
+/* This means that the processor is an EV5, EV56, or PCA56.
+ Unlike alpha_cpu this is not affected by -mtune= setting. */
#define MASK_CPU_EV5 (1 << 28)
+#define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
/* Likewise for EV6. */
#define MASK_CPU_EV6 (1 << 29)
+#define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
/* This means we support the .arch directive in the assembler. Only
defined in TARGET_CPU_DEFAULT. */
#ifndef TARGET_HAS_XFLOATING_LIBS
#define TARGET_HAS_XFLOATING_LIBS 0
#endif
+#ifndef TARGET_PROFILING_NEEDS_GP
+#define TARGET_PROFILING_NEEDS_GP 0
+#endif
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
- {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
- {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
- {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
- {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
- {"gas", MASK_GAS, "Assume GAS"}, \
+ { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
+ {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
+ {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
+ {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
+ N_("Do not use fp registers")}, \
+ {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
+ {"gas", MASK_GAS, N_("Assume GAS")}, \
{"ieee-conformant", MASK_IEEE_CONFORMANT, \
- "Request IEEE-conformant math library routines (OSF/1)"}, \
+ N_("Request IEEE-conformant math library routines (OSF/1)")}, \
{"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
- "Emit IEEE-conformant code, without inexact exceptions"}, \
+ N_("Emit IEEE-conformant code, without inexact exceptions")}, \
{"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
- "Emit IEEE-conformant code, with inexact exceptions"}, \
+ N_("Emit IEEE-conformant code, with inexact exceptions")}, \
{"build-constants", MASK_BUILD_CONSTANTS, \
- "Do not emit complex integer constants to read-only memory"}, \
- {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
- {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
- {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
+ N_("Do not emit complex integer constants to read-only memory")}, \
+ {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
+ {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
+ {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
{"no-bwx", -MASK_BWX, ""}, \
- {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
+ {"max", MASK_MAX, \
+ N_("Emit code for the motion video ISA extension")}, \
{"no-max", -MASK_MAX, ""}, \
- {"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
+ {"fix", MASK_FIX, \
+ N_("Emit code for the fp move and sqrt ISA extension")}, \
{"no-fix", -MASK_FIX, ""}, \
- {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
+ {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
{"no-cix", -MASK_CIX, ""}, \
{"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
extern const char *alpha_cpu_string; /* For -mcpu= */
+extern const char *alpha_tune_string; /* For -mtune= */
extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
#define TARGET_OPTIONS \
{ \
{"cpu=", &alpha_cpu_string, \
- "Generate code for a given CPU"}, \
+ N_("Use features of and schedule given CPU")}, \
+ {"tune=", &alpha_tune_string, \
+ N_("Schedule given CPU")}, \
{"fp-rounding-mode=", &alpha_fprm_string, \
- "Control the generated fp rounding mode"}, \
+ N_("Control the generated fp rounding mode")}, \
{"fp-trap-mode=", &alpha_fptm_string, \
- "Control the IEEE trap mode"}, \
+ N_("Control the IEEE trap mode")}, \
{"trap-precision=", &alpha_tp_string, \
- "Control the precision given to fp exceptions"}, \
+ N_("Control the precision given to fp exceptions")}, \
{"memory-latency=", &alpha_mlat_string, \
- "Tune expected memory latency"}, \
+ N_("Tune expected memory latency")}, \
}
/* Attempt to describe CPU characteristics to the preprocessor. */
/* Corresponding to amask... */
-#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
-#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
-#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
-#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
+#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx"
+#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max"
+#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix"
+#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix"
/* Corresponding to implver... */
-#define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
-#define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
-#define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
+#define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4"
+#define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5"
+#define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6"
/* Common combinations. */
#define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
#ifndef CPP_CPU_DEFAULT_SPEC
# if TARGET_CPU_DEFAULT & MASK_CPU_EV6
-# if TARGET_CPU_DEFAULT & MAX_CIX
+# if TARGET_CPU_DEFAULT & MASK_CIX
# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
# else
# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
#ifndef CPP_CPU_SPEC
#define CPP_CPU_SPEC "\
-%{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
+%{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \
%{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
%{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
%{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
#define STACK_BOUNDARY 64
/* Allocation boundary (in *bits*) for the code of a function. */
-#define FUNCTION_BOUNDARY 256
+#define FUNCTION_BOUNDARY 128
/* Alignment of field after `int : 0' in a structure. */
#define EMPTY_FIELD_BOUNDARY 64
/* For atomic access to objects, must have at least 32-bit alignment
unless the machine has byte operations. */
-#define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
+#define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
/* Align all constants and variables to at least a word boundary so
we can pick up pieces of them faster. */
For any two classes, it is very desirable that there be another
class that represents their union. */
-enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
+enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
LIM_REG_CLASSES };
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \
- {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
+ {"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \
- { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
+ { {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
-#define REGNO_REG_CLASS(REGNO) \
- ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
+#define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) == 27 ? PV_REG \
+ : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
+ : GENERAL_REGS)
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS NO_REGS
/* Get reg_class from a letter such as appears in the machine description. */
#define REG_CLASS_FROM_LETTER(C) \
- ((C) == 'f' ? FLOAT_REGS : NO_REGS)
+ ((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS)
/* Define this macro to change register usage conditional on target flags. */
/* #define CONDITIONAL_REGISTER_USAGE */
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* If defined, gives a class of registers that cannot be used as the
- operand of a SUBREG that changes the size of the object. */
+ operand of a SUBREG that changes the mode of the object illegally. */
+
+#define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
-#define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
+/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
+
+#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
/* Define the cost of moving between registers of various classes. Moving
between FLOAT_REGS and anything else except float regs is expensive.
reduce the impact of not being able to allocate a pseudo to a
hard register. */
-#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
+#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
(((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
? 2 \
: TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
/* Define this if the maximum size of all the outgoing args is to be
accumulated and pushed during the prologue. The amount can be
found in the variable current_function_outgoing_args_size. */
-#define ACCUMULATE_OUTGOING_ARGS
+#define ACCUMULATE_OUTGOING_ARGS 1
/* Offset of first parameter from the argument pointer register value. */
+ (ALPHA_ROUND (get_frame_size () \
+ current_function_pretend_args_size) \
- current_function_pretend_args_size)); \
+ else \
+ abort (); \
}
/* Define this if stack space is still allocated for a parameter passed
} \
}
+/* We do not allow indirect calls to be optimized into sibling calls, nor
+ can we allow a call to a function in a different compilation unit to
+ be optimized into a sibcall. Except if the function is known not to
+ return, in which case our caller doesn't care what the gp is. */
+#define FUNCTION_OK_FOR_SIBCALL(DECL) \
+ (DECL \
+ && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
+ || ! TREE_PUBLIC (DECL)))
+
/* Try to output insns to set TARGET equal to the constant C if it can be
done in less than N insns. Do all computations in MODE. Returns the place
where the output has been placed if it can be done and the insns have been
struct machine_function
{
- /* An offset to apply to the stack pointer when unwinding from EH. */
- struct rtx_def *eh_epilogue_sp_ofs;
-
/* If non-null, this rtx holds the return address for the function. */
struct rtx_def *ra_rtx;
};
No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 1
+
+/* Define registers used by the epilogue and return instruction. */
+
+#define EPILOGUE_USES(REGNO) ((REGNO) == 26)
\f
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts.
/* Before the prologue, RA lives in $26. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
+#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
+
+/* Describe how we implement __builtin_eh_return. */
+#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
+#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
+#define EH_RETURN_HANDLER_RTX \
+ gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
+ current_function_outgoing_args_size))
\f
/* Addressing modes, and classification of registers for them. */
&& GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
&& GET_CODE (XEXP (X, 1)) == CONST_INT) \
{ \
- push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
+ push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
goto WIN; \
GEN_INT (high)), \
GEN_INT (low)); \
\
- push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
+ push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
OPNUM, TYPE); \
goto WIN; \
\f
/* Control the assembler format that we output. */
-/* We don't emit these labels, so as to avoid getting linker errors about
- missing exception handling info. If we emit a gcc_compiled. label into
- text, and the file has no code, then the DEC assembler gives us a zero
- sized text section with no associated exception handling info. The
- DEC linker sees this text section, and gives a warning saying that
- the exception handling info is missing. */
-#define ASM_IDENTIFY_GCC(x)
-#define ASM_IDENTIFY_LANGUAGE(x)
-
/* Output to assembler file text saying following lines
may contain character constants, extra white space, comments, etc. */
#define ASM_APP_OFF ""
-#define TEXT_SECTION_ASM_OP ".text"
+#define TEXT_SECTION_ASM_OP "\t.text"
/* Output before read-only data. */
-#define READONLY_DATA_SECTION_ASM_OP ".rdata"
+#define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
/* Output before writable data. */
-#define DATA_SECTION_ASM_OP ".data"
+#define DATA_SECTION_ASM_OP "\t.data"
/* Define an extra section for read-only data, a routine to enter it, and
indicate that it is for read-only data.
while (0)
/* To get unaligned data, we have to turn off auto alignment. */
-#define UNALIGNED_SHORT_ASM_OP ".align 0\n\t.word"
-#define UNALIGNED_INT_ASM_OP ".align 0\n\t.long"
-#define UNALIGNED_DOUBLE_INT_ASM_OP ".align 0\n\t.quad"
+#define UNALIGNED_SHORT_ASM_OP "\t.align 0\n\t.word\t"
+#define UNALIGNED_INT_ASM_OP "\t.align 0\n\t.long\t"
+#define UNALIGNED_DOUBLE_INT_ASM_OP "\t.align 0\n\t.quad\t"
/* This is how to output an insn to push a register on the stack.
It need not be very fast code. */
/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
Used for C++ multiple inheritance. */
-
+/* ??? This is only used with the v2 ABI, and alpha.c makes assumptions
+ about current_function_is_thunk that are not valid with the v3 ABI. */
+#if 0
#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
do { \
const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
int reg; \
\
+ if (! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT) \
+ fprintf (FILE, "\tldgp $29,0($27)\n"); \
+ \
/* Mark end of prologue. */ \
output_end_prologue (FILE); \
\
/* Rely on the assembler to macro expand a large delta. */ \
+ fprintf (FILE, "\t.set at\n"); \
reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
\
assemble_name (FILE, fn_name); \
fputc ('\n', FILE); \
} \
+ fprintf (FILE, "\t.set noat\n"); \
} while (0)
+#endif
\f
/* Define results of standard character escape sequences. */
#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
/* Determine which codes are valid without a following integer. These must
- not be alphabetic (the characters are chosen so that
- PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
- using ASCII).
+ not be alphabetic.
+
+ ~ Generates the name of the current function.
& Generates fp-rounding mode suffix: nothing for normal, 'c' for
chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
- || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
+ || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-' \
+ || (CODE) == '~')
\f
/* Print a memory address as an operand to reference that memory location. */
{"mode_width_operand", {CONST_INT}}, \
{"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
{"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
+ {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
{"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
{"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
{"any_memory_operand", {MEM}}, \
{"hard_fp_register_operand", {SUBREG, REG}}, \
+ {"hard_int_register_operand", {SUBREG, REG}}, \
{"reg_not_elim_operand", {SUBREG, REG}}, \
{"reg_no_subreg_operand", {REG}}, \
{"addition_operation", {PLUS}},
that the ALPHA assembler does not choke. The mips-tfile program
will correctly put the stab into the object file. */
-#define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
-#define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
-#define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
+#define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
+#define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
+#define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
/* Forward references to tags are allowed. */
#define SDB_ALLOW_FORWARD_REFERENCES
#define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
-/* The linker will stick __main into the .init section. */
-#define HAS_INIT_SECTION
-#define LD_INIT_SWITCH "-init"
-#define LD_FINI_SWITCH "-fini"
-
/* The system headers under Alpha systems are generally C++-aware. */
#define NO_IMPLICIT_EXTERN_C