/* Optimize by combining instructions for GNU compiler.
Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of GCC.
BITS_PER_WORD would invoke undefined behavior. Work around it. */
#define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
- (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
+ (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
/* Maximum register number, which is the size of the tables below. */
if (oldval == newval)
return;
+ /* We'd like to catch as many invalid transformations here as
+ possible. Unfortunately, there are way too many mode changes
+ that are perfectly valid, so we'd waste too much effort for
+ little gain doing the checks here. Focus on catching invalid
+ transformations involving integer constants. */
+ if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
+ && GET_CODE (newval) == CONST_INT)
+ {
+ /* Sanity check that we're replacing oldval with a CONST_INT
+ that is a valid sign-extension for the original mode. */
+ if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
+ GET_MODE (oldval)))
+ abort ();
+
+ /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
+ CONST_INT is not valid, because after the replacement, the
+ original mode would be gone. Unfortunately, we can't tell
+ when do_SUBST is called to replace the operand thereof, so we
+ perform this test on oldval instead, checking whether an
+ invalid replacement took place before we got here. */
+ if ((GET_CODE (oldval) == SUBREG
+ && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
+ || (GET_CODE (oldval) == ZERO_EXTEND
+ && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
+ abort ();
+ }
+
if (undobuf.frees)
buf = undobuf.frees, undobuf.frees = buf->next;
else
rtx f;
unsigned int nregs;
{
- register rtx insn, next;
+ rtx insn, next;
#ifdef HAVE_cc0
- register rtx prev;
+ rtx prev;
#endif
- register int i;
- register rtx links, nextlinks;
+ int i;
+ rtx links, nextlinks;
int new_direct_jump_p = 0;
rtx link = XEXP (links, 0);
/* If the linked insn has been replaced by a note, then there
- is no point in persuing this chain any further. */
+ is no point in pursuing this chain any further. */
if (GET_CODE (link) == NOTE)
- break;
+ continue;
for (nextlinks = LOG_LINKS (link);
nextlinks;
nextlinks = XEXP (nextlinks, 1))
- if ((next = try_combine (insn, XEXP (links, 0),
+ if ((next = try_combine (insn, link,
XEXP (nextlinks, 0),
&new_direct_jump_p)) != 0)
goto retry;
;
}
}
+ clear_bb_flags ();
+ EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, this_basic_block,
+ BASIC_BLOCK (this_basic_block)->flags |= BB_DIRTY);
+ new_direct_jump_p |= purge_all_dead_edges (0);
delete_noop_moves (f);
- if (need_refresh)
- {
- compute_bb_for_insn (get_max_uid ());
- update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
- PROP_DEATH_NOTES);
- }
+ update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
+ PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
+ | PROP_KILL_DEAD_CODE);
/* Clean up. */
sbitmap_free (refresh_blocks);
<< GET_MODE_BITSIZE (GET_MODE (x))));
#endif
- reg_nonzero_bits[REGNO (x)]
- |= nonzero_bits (src, nonzero_bits_mode);
+ /* Don't call nonzero_bits if it cannot change anything. */
+ if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
+ reg_nonzero_bits[REGNO (x)]
+ |= nonzero_bits (src, nonzero_bits_mode);
num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
if (reg_sign_bit_copies[REGNO (x)] == 0
|| reg_sign_bit_copies[REGNO (x)] > num)
for the SH4 port. */
case USE:
/* Combining an isolated USE doesn't make sense.
- We depend here on combinable_i3_pat to reject them. */
+ We depend here on combinable_i3pat to reject them. */
/* The code below this loop only verifies that the inputs of
the SET in INSN do not change. We call reg_set_between_p
- to verify that the REG in the USE does not change betweeen
+ to verify that the REG in the USE does not change between
I3 and INSN.
If the USE in INSN was for a pseudo register, the matching
insn pattern will likely match any register; combining this
with any other USE would only be safe if we knew that the
used registers have identical values, or if there was
something to tell them apart, e.g. different modes. For
- now, we forgo such compilcated tests and simply disallow
+ now, we forgo such complicated tests and simply disallow
combining of USES of pseudo registers with any other USE. */
if (GET_CODE (XEXP (elt, 0)) == REG
&& GET_CODE (PATTERN (i3)) == PARALLEL)
for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
- return 0;
+ return 0;
}
/* If INSN is an asm, and DEST is a hard register, reject, since it has
static rtx
try_combine (i3, i2, i1, new_direct_jump_p)
- register rtx i3, i2, i1;
- register int *new_direct_jump_p;
+ rtx i3, i2, i1;
+ int *new_direct_jump_p;
{
/* New patterns for I3 and I2, respectively. */
rtx newpat, newi2pat = 0;
+ int substed_i2 = 0, substed_i1 = 0;
/* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
int added_sets_1, added_sets_2;
/* Total number of SETs to put into I3. */
int maxreg;
rtx temp;
- register rtx link;
+ rtx link;
int i;
/* Exit early if one of the insns involved can't be used for
abort ();
lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
- lo |= INTVAL (SET_SRC (PATTERN (i3)));
+ lo |= (INTVAL (SET_SRC (PATTERN (i3)))
+ & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
}
else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
hi = INTVAL (SET_SRC (PATTERN (i3)));
subst_low_cuid = INSN_CUID (i2);
newpat = subst (PATTERN (i3), i2dest, i2src, 0,
! i1_feeds_i3 && i1dest_in_i1src);
+ substed_i2 = 1;
/* Record whether i2's body now appears within i3's body. */
i2_is_used = n_occurrences;
isn't mentioned in any SETs in NEWPAT that are field assignments. */
if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
- 0, (rtx*)0))
+ 0, (rtx*) 0))
{
undo_all ();
return 0;
n_occurrences = 0;
subst_low_cuid = INSN_CUID (i1);
newpat = subst (newpat, i1dest, i1src, 0, 0);
+ substed_i1 = 1;
}
/* Fail if an autoincrement side-effect has been duplicated. Be careful
XVECEXP (newpat, 0, 0) = old;
}
- if (added_sets_1)
- XVECEXP (newpat, 0, --total_sets)
- = (GET_CODE (PATTERN (i1)) == PARALLEL
- ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
+ if (added_sets_1)
+ XVECEXP (newpat, 0, --total_sets)
+ = (GET_CODE (PATTERN (i1)) == PARALLEL
+ ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
- if (added_sets_2)
- {
- /* If there is no I1, use I2's body as is. We used to also not do
- the subst call below if I2 was substituted into I3,
- but that could lose a simplification. */
- if (i1 == 0)
- XVECEXP (newpat, 0, --total_sets) = i2pat;
- else
- /* See comment where i2pat is assigned. */
- XVECEXP (newpat, 0, --total_sets)
- = subst (i2pat, i1dest, i1src, 0, 0);
- }
+ if (added_sets_2)
+ {
+ /* If there is no I1, use I2's body as is. We used to also not do
+ the subst call below if I2 was substituted into I3,
+ but that could lose a simplification. */
+ if (i1 == 0)
+ XVECEXP (newpat, 0, --total_sets) = i2pat;
+ else
+ /* See comment where i2pat is assigned. */
+ XVECEXP (newpat, 0, --total_sets)
+ = subst (i2pat, i1dest, i1src, 0, 0);
+ }
}
/* We come here when we are replacing a destination in I2 with the
}
}
+ /* If we've split a jump pattern, we'll wind up with a sequence even
+ with one instruction. We can handle that below, so extract it. */
+ if (m_split && GET_CODE (m_split) == SEQUENCE
+ && XVECLEN (m_split, 0) == 1)
+ m_split = PATTERN (XVECEXP (m_split, 0, 0));
+
if (m_split && GET_CODE (m_split) != SEQUENCE)
{
insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
INSN_CODE (i3) = insn_code_number;
PATTERN (i3) = newpat;
+
+ if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
+ {
+ rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
+
+ reset_used_flags (call_usage);
+ call_usage = copy_rtx (call_usage);
+
+ if (substed_i2)
+ replace_rtx (call_usage, i2dest, i2src);
+
+ if (substed_i1)
+ replace_rtx (call_usage, i1dest, i1src);
+
+ CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
+ }
+
if (undobuf.other_insn)
INSN_CODE (undobuf.other_insn) = other_code_number;
&& GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
&& GET_CODE (SET_SRC (x)) == CONST_INT
&& ((INTVAL (XEXP (SET_DEST (x), 1))
- + INTVAL (XEXP (SET_DEST (x), 2)))
+ + INTVAL (XEXP (SET_DEST (x), 2)))
<= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
&& ! side_effects_p (XEXP (SET_DEST (x), 0)))
{
SUBST (SET_SRC (x),
gen_binary (IOR, mode,
gen_binary (AND, mode, dest,
- GEN_INT (~(mask << pos)
- & GET_MODE_MASK (mode))),
+ gen_int_mode (~(mask << pos),
+ mode)),
GEN_INT (src << pos)));
SUBST (SET_DEST (x), dest);
&& GET_CODE (XEXP (SET_SRC (x), 0)) == REG
&& (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
&& GET_CODE (SET_DEST (x)) == REG
- && (split = find_single_use (SET_DEST (x), insn, (rtx*)0)) != 0
+ && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
&& (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
&& XEXP (*split, 0) == SET_DEST (x)
&& XEXP (*split, 1) == const0_rtx)
static rtx
subst (x, from, to, in_dest, unique_copy)
- register rtx x, from, to;
+ rtx x, from, to;
int in_dest;
int unique_copy;
{
- register enum rtx_code code = GET_CODE (x);
+ enum rtx_code code = GET_CODE (x);
enum machine_mode op0_mode = VOIDmode;
- register const char *fmt;
- register int len, i;
+ const char *fmt;
+ int len, i;
rtx new;
/* Two expressions are equal if they are identical copies of a shared
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
{
if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
return new;
- SUBST (XEXP (x, i), new);
+ if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
+ {
+ if (VECTOR_MODE_P (GET_MODE (x)))
+ return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
+
+ x = simplify_subreg (GET_MODE (x), new,
+ GET_MODE (SUBREG_REG (x)),
+ SUBREG_BYTE (x));
+ if (! x)
+ abort ();
+ }
+ else if (GET_CODE (new) == CONST_INT
+ && GET_CODE (x) == ZERO_EXTEND)
+ {
+ x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
+ new, GET_MODE (XEXP (x, 0)));
+ if (! x)
+ abort ();
+ }
+ else
+ SUBST (XEXP (x, i), new);
}
}
}
&& subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
return gen_lowpart_for_combine (mode, SUBREG_REG (x));
+ if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
+ break;
{
rtx temp;
temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
return temp;
}
+ /* Don't change the mode of the MEM if that would change the meaning
+ of the address. */
+ if (GET_CODE (SUBREG_REG (x)) == MEM
+ && (MEM_VOLATILE_P (SUBREG_REG (x))
+ || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
+ return gen_rtx_CLOBBER (mode, const0_rtx);
+
/* Note that we cannot do any narrowing for non-constants since
we might have been counting on using the fact that some bits were
zero. We now do this in the SET. */
if (GET_CODE (XEXP (x, 0)) == NOT)
return plus_constant (XEXP (XEXP (x, 0), 0), 1);
- /* (neg (minus X Y)) can become (minus Y X). */
+ /* (neg (minus X Y)) can become (minus Y X). This transformation
+ isn't safe for modes with signed zeros, since if X and Y are
+ both +0, (minus Y X) is the same as (minus X Y). If the rounding
+ mode is towards +infinity (or -infinity) then the two expressions
+ will be rounded differently. */
if (GET_CODE (XEXP (x, 0)) == MINUS
- && (! FLOAT_MODE_P (mode)
- /* x-y != -(y-x) with IEEE floating point. */
- || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
- || flag_unsafe_math_optimizations))
+ && !HONOR_SIGNED_ZEROS (mode)
+ && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
XEXP (XEXP (x, 0), 0));
if (XEXP (x, 1) == const0_rtx)
return XEXP (x, 0);
- /* In IEEE floating point, x-0 is not the same as x. */
- if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
- || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
- || flag_unsafe_math_optimizations)
+ /* x - 0 is the same as x unless x's mode has signed zeros and
+ allows rounding towards -infinity. Under those conditions,
+ 0 - 0 is -0. */
+ if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
+ && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
&& XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
return XEXP (x, 0);
break;
simplify_gen_unary (NEG, mode,
simplify_gen_unary (ABS, mode, true_rtx, mode),
mode);
- default:
- break;
+ default:
+ break;
}
/* Look for MIN or MAX. */
len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
/* If the inner object has VOIDmode (the only way this can happen
- is if it is a ASM_OPERANDS), we can't do anything since we don't
+ is if it is an ASM_OPERANDS), we can't do anything since we don't
know how much masking to do. */
if (len == 0)
return x;
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
&& GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
{
- int byte_offset = SUBREG_BYTE (XEXP (SET_DEST (x), 0));
-
inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
- pos = GEN_INT (BITS_PER_WORD * (byte_offset / UNITS_PER_WORD));
+ pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
}
else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
&& GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
if (mode == tmode)
return new;
+ if (GET_CODE (new) == CONST_INT)
+ return gen_int_mode (INTVAL (new), mode);
+
/* If we know that no extraneous bits are set, and that the high
bit is not set, convert the extraction to the cheaper of
sign and zero extension, that are equivalent in these cases. */
/* Get the mode to use should INNER not be a MEM, the mode for the position,
and the mode for the result. */
- if (in_dest && mode_for_extraction(EP_insv, -1) != MAX_MACHINE_MODE)
+ if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
{
wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
pos_mode = mode_for_extraction (EP_insv, 2);
rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
/* If we know that no extraneous bits are set, and that the high
- bit is not set, convert extraction to cheaper one - eighter
+ bit is not set, convert extraction to cheaper one - either
SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
cases. */
if (flag_expensive_optimizations
NULL_RTX, 0);
/* If we have something other than a SUBREG, we might have
- done an expansion, so rerun outselves. */
+ done an expansion, so rerun ourselves. */
if (GET_CODE (newer) != SUBREG)
newer = make_compound_operation (newer, in_code);
need it. */
if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
- && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
+ && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
+ == (HOST_WIDE_INT) mask))
x = XEXP (x, 0);
/* If it remains an AND, try making another AND with the bits
smask |= (HOST_WIDE_INT) -1 << width;
if (GET_CODE (XEXP (x, 1)) == CONST_INT
- && exact_log2 (- smask) >= 0)
- {
-#ifdef STACK_BIAS
- if (STACK_BIAS
- && (XEXP (x, 0) == stack_pointer_rtx
- || XEXP (x, 0) == frame_pointer_rtx))
- {
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
- unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
-
- sp_mask &= ~(sp_alignment - 1);
- if ((sp_mask & ~smask) == 0
- && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
- return force_to_mode (plus_constant (XEXP (x, 0),
- ((INTVAL (XEXP (x, 1)) -
- STACK_BIAS) & smask)
- + STACK_BIAS),
- mode, smask, reg, next_select);
- }
-#endif
- if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
- && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
- return force_to_mode (plus_constant (XEXP (x, 0),
- (INTVAL (XEXP (x, 1))
- & smask)),
- mode, smask, reg, next_select);
- }
+ && exact_log2 (- smask) >= 0
+ && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
+ && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
+ return force_to_mode (plus_constant (XEXP (x, 0),
+ (INTVAL (XEXP (x, 1)) & smask)),
+ mode, smask, reg, next_select);
}
/* ... fall through ... */
binop:
/* For most binary operations, just propagate into the operation and
- change the mode if we have an operation of that mode. */
+ change the mode if we have an operation of that mode. */
op0 = gen_lowpart_for_combine (op_mode,
force_to_mode (XEXP (x, 0), mode, mask,
{
int i = -1;
- /* If the considered data is wider then HOST_WIDE_INT, we can't
+ /* If the considered data is wider than HOST_WIDE_INT, we can't
represent a mask for all its bits in a single scalar.
But we only care about the lower bits, so calculate these. */
}
}
- /* If MASK is 1, convert this to a LSHIFTRT. This can be done
+ /* If MASK is 1, convert this to an LSHIFTRT. This can be done
even if the shift count isn't a constant. */
if (mask == 1)
x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
case NEG:
/* If we just want the low-order bit, the NEG isn't needed since it
- won't change the low-order bit. */
+ won't change the low-order bit. */
if (mask == 1)
return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
}
}
- /* Similarly for MULT, AND and UMIN, execpt that for these the result
+ /* Similarly for MULT, AND and UMIN, except that for these the result
is always zero. */
if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
&& (code == MULT || code == AND || code == UMIN)
&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
&& exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
{
- *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
+ *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
return x;
}
if (side_effects_p (x))
return x;
- if (cond == EQ && rtx_equal_p (x, reg) && !FLOAT_MODE_P (cond))
+ /* If either operand of the condition is a floating point value,
+ then we have to avoid collapsing an EQ comparison. */
+ if (cond == EQ
+ && rtx_equal_p (x, reg)
+ && ! FLOAT_MODE_P (GET_MODE (x))
+ && ! FLOAT_MODE_P (GET_MODE (val)))
return val;
+
if (cond == UNEQ && rtx_equal_p (x, reg))
return val;
}
}
}
+ else if (code == SUBREG)
+ {
+ enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
+ rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
+
+ if (SUBREG_REG (x) != r)
+ {
+ /* We must simplify subreg here, before we lose track of the
+ original inner_mode. */
+ new = simplify_subreg (GET_MODE (x), r,
+ inner_mode, SUBREG_BYTE (x));
+ if (new)
+ return new;
+ else
+ SUBST (SUBREG_REG (x), r);
+ }
+
+ return x;
+ }
+ /* We don't have to handle SIGN_EXTEND here, because even in the
+ case of replacing something with a modeless CONST_INT, a
+ CONST_INT is already (supposed to be) a valid sign extension for
+ its narrower mode, which implies it's already properly
+ sign-extended for the wider mode. Now, for ZERO_EXTEND, the
+ story is different. */
+ else if (code == ZERO_EXTEND)
+ {
+ enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
+ rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
+
+ if (XEXP (x, 0) != r)
+ {
+ /* We must simplify the zero_extend here, before we lose
+ track of the original inner_mode. */
+ new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
+ r, inner_mode);
+ if (new)
+ return new;
+ else
+ SUBST (XEXP (x, 0), r);
+ }
+
+ return x;
+ }
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
int i;
/* Simplify VAROP knowing that we will be only looking at some of the
- bits in it. */
+ bits in it.
+
+ Note by passing in CONSTOP, we guarantee that the bits not set in
+ CONSTOP are not significant and will never be examined. We must
+ ensure that is the case by explicitly masking out those bits
+ before returning. */
varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
- /* If VAROP is a CLOBBER, we will fail so return it; if it is a
- CONST_INT, we are done. */
- if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
+ /* If VAROP is a CLOBBER, we will fail so return it. */
+ if (GET_CODE (varop) == CLOBBER)
return varop;
+ /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
+ to VAROP and return the new constant. */
+ if (GET_CODE (varop) == CONST_INT)
+ return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
+
/* See what bits may be nonzero in VAROP. Unlike the general case of
a call to nonzero_bits, here we don't care about bits outside
MODE. */
nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
- nonzero = trunc_int_for_mode (nonzero, mode);
/* Turn off all bits in the constant that are known to already be zero.
Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
return const0_rtx;
/* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
- a power of two, we can replace this with a ASHIFT. */
+ a power of two, we can replace this with an ASHIFT. */
if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
&& (i = exact_log2 (constop)) >= 0)
return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
simplify_and_const_int (NULL_RTX, GET_MODE (varop),
XEXP (varop, 1), constop))));
+ /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
+ the AND and see if one of the operands simplifies to zero. If so, we
+ may eliminate it. */
+
+ if (GET_CODE (varop) == PLUS
+ && exact_log2 (constop + 1) >= 0)
+ {
+ rtx o0, o1;
+
+ o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
+ o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
+ if (o0 == const0_rtx)
+ return o1;
+ if (o1 == const0_rtx)
+ return o0;
+ }
+
/* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
if we already had one (just check for the simplest cases). */
if (x && GET_CODE (XEXP (x, 0)) == SUBREG
/* If we are only masking insignificant bits, return VAROP. */
if (constop == nonzero)
x = varop;
-
- /* Otherwise, return an AND. See how much, if any, of X we can use. */
- else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
- x = gen_binary (AND, mode, varop, GEN_INT (constop));
-
else
{
- if (GET_CODE (XEXP (x, 1)) != CONST_INT
- || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
- SUBST (XEXP (x, 1), GEN_INT (constop));
+ /* Otherwise, return an AND. */
+ constop = trunc_int_for_mode (constop, mode);
+ /* See how much, if any, of X we can use. */
+ if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
+ x = gen_binary (AND, mode, varop, GEN_INT (constop));
+
+ else
+ {
+ if (GET_CODE (XEXP (x, 1)) != CONST_INT
+ || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
+ SUBST (XEXP (x, 1), GEN_INT (constop));
- SUBST (XEXP (x, 0), varop);
+ SUBST (XEXP (x, 0), varop);
+ }
}
return x;
nonzero &= GET_MODE_MASK (ptr_mode);
#endif
-#ifdef STACK_BOUNDARY
- /* If this is the stack pointer, we may know something about its
- alignment. If PUSH_ROUNDING is defined, it is possible for the
- stack to be momentarily aligned only to that amount, so we pick
- the least alignment. */
-
- /* We can't check for arg_pointer_rtx here, because it is not
- guaranteed to have as much alignment as the stack pointer.
- In particular, in the Irix6 n64 ABI, the stack has 128 bit
- alignment but the argument pointer has only 64 bit alignment. */
-
- if ((x == frame_pointer_rtx
- || x == stack_pointer_rtx
- || x == hard_frame_pointer_rtx
- || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
- && REGNO (x) <= LAST_VIRTUAL_REGISTER))
-#ifdef STACK_BIAS
- && !STACK_BIAS
-#endif
- )
+ /* Include declared information about alignment of pointers. */
+ /* ??? We don't properly preserve REG_POINTER changes across
+ pointer-to-integer casts, so we can't trust it except for
+ things that we know must be pointers. See execute/960116-1.c. */
+ if ((x == stack_pointer_rtx
+ || x == frame_pointer_rtx
+ || x == arg_pointer_rtx)
+ && REGNO_POINTER_ALIGN (REGNO (x)))
{
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
+ unsigned HOST_WIDE_INT alignment
+ = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
#ifdef PUSH_ROUNDING
- if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
- sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
+ /* If PUSH_ROUNDING is defined, it is possible for the
+ stack to be momentarily aligned only to that amount,
+ so we pick the least alignment. */
+ if (x == stack_pointer_rtx && PUSH_ARGS)
+ alignment = MIN (PUSH_ROUNDING (1), alignment);
#endif
- /* We must return here, otherwise we may get a worse result from
- one of the choices below. There is nothing useful below as
- far as the stack pointer is concerned. */
- return nonzero &= ~(sp_alignment - 1);
+ nonzero &= ~(alignment - 1);
}
-#endif
/* If X is a register whose nonzero bits value is current, use it.
Otherwise, if X is a register whose value we can find, use that
for this register. */
if (reg_last_set_value[REGNO (x)] != 0
- && reg_last_set_mode[REGNO (x)] == mode
+ && (reg_last_set_mode[REGNO (x)] == mode
+ || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
+ && GET_MODE_CLASS (mode) == MODE_INT))
&& (reg_last_set_label[REGNO (x)] == label_tick
|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
&& REG_N_SETS (REGNO (x)) == 1
&& ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
REGNO (x))))
&& INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
- return reg_last_set_nonzero_bits[REGNO (x)];
+ return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
tem = get_last_value (x);
| ((HOST_WIDE_INT) (-1)
<< GET_MODE_BITSIZE (GET_MODE (x))));
#endif
- return nonzero_bits (tem, mode);
+ return nonzero_bits (tem, mode) & nonzero;
}
else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
- return reg_nonzero_bits[REGNO (x)] & nonzero;
+ {
+ unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
+
+ if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
+ /* We don't know anything about the upper bits. */
+ mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
+ return nonzero & mask;
+ }
else
return nonzero;
case XOR: case IOR:
case UMIN: case UMAX: case SMIN: case SMAX:
- nonzero &= (nonzero_bits (XEXP (x, 0), mode)
- | nonzero_bits (XEXP (x, 1), mode));
+ {
+ unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
+
+ /* Don't call nonzero_bits for the second time if it cannot change
+ anything. */
+ if ((nonzero & nonzero0) != nonzero)
+ nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
+ }
break;
case PLUS: case MINUS:
switch (code)
{
case PLUS:
-#ifdef STACK_BIAS
- if (STACK_BIAS
- && (XEXP (x, 0) == stack_pointer_rtx
- || XEXP (x, 0) == frame_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
- {
- int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
-
- nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
- nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
- width0 = floor_log2 (nz0) + 1;
- width1 = floor_log2 (nz1) + 1;
- low0 = floor_log2 (nz0 & -nz0);
- low1 = floor_log2 (nz1 & -nz1);
- }
-#endif
result_width = MAX (width0, width1) + 1;
result_low = MIN (low0, low1);
break;
been zero-extended, we know that at least the high-order bits
are zero, though others might be too. */
- if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
+ if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
nonzero = (GET_MODE_MASK (GET_MODE (x))
& nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
if (tem != 0)
return num_sign_bit_copies (tem, mode);
- if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
+ if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
+ && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
return reg_sign_bit_copies[REGNO (x)];
break;
if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
&& (code == PLUS || code == MINUS)
&& GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
- result = MAX ((GET_MODE_BITSIZE (Pmode)
- - GET_MODE_BITSIZE (ptr_mode) + 1),
+ result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
+ - GET_MODE_BITSIZE (ptr_mode) + 1),
result);
#endif
return result;
return num_sign_bit_copies (XEXP (x, 0), mode);
case UMOD:
- /* The result must be <= the scond operand. */
+ /* The result must be <= the second operand. */
return num_sign_bit_copies (XEXP (x, 1), mode);
case DIV:
are ASHIFTRT and ROTATE, which are always done in their original mode, */
static rtx
-simplify_shift_const (x, code, result_mode, varop, input_count)
+simplify_shift_const (x, code, result_mode, varop, orig_count)
rtx x;
enum rtx_code code;
enum machine_mode result_mode;
rtx varop;
- int input_count;
+ int orig_count;
{
enum rtx_code orig_code = code;
- int orig_count = input_count;
unsigned int count;
int signed_count;
enum machine_mode mode = result_mode;
int complement_p = 0;
rtx new;
+ /* Make sure and truncate the "natural" shift on the way in. We don't
+ want to do this inside the loop as it makes it more difficult to
+ combine shifts. */
+#ifdef SHIFT_COUNT_TRUNCATED
+ if (SHIFT_COUNT_TRUNCATED)
+ orig_count &= GET_MODE_BITSIZE (mode) - 1;
+#endif
+
/* If we were given an invalid count, don't do anything except exactly
what was requested. */
- if (input_count < 0 || input_count >= (int) GET_MODE_BITSIZE (mode))
+ if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
{
if (x)
return x;
- return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
+ return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
}
- count = input_count;
-
- /* Make sure and truncate the "natural" shift on the way in. We don't
- want to do this inside the loop as it makes it more difficult to
- combine shifts. */
-#ifdef SHIFT_COUNT_TRUNCATED
- if (SHIFT_COUNT_TRUNCATED)
- count %= GET_MODE_BITSIZE (mode);
-#endif
+ count = orig_count;
/* Unless one of the branches of the `if' in this loop does a `continue',
we will `break' the loop after the `if'. */
/* We simplify the tests below and elsewhere by converting
ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
- `make_compound_operation' will convert it to a ASHIFTRT for
- those machines (such as VAX) that don't have a LSHIFTRT. */
+ `make_compound_operation' will convert it to an ASHIFTRT for
+ those machines (such as VAX) that don't have an LSHIFTRT. */
if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
&& code == ASHIFTRT
&& ((nonzero_bits (varop, shift_mode)
/* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
than C1 high-order bits equal to the sign bit, we can convert
- this to either an ASHIFT or a ASHIFTRT depending on the
+ this to either an ASHIFT or an ASHIFTRT depending on the
two counts.
We cannot do this if VAROP's mode is not SHIFT_MODE. */
if (new != 0)
x = new;
else
- {
- if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
- x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
-
- SUBST (XEXP (x, 0), varop);
- SUBST (XEXP (x, 1), const_rtx);
- }
+ x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
/* If we have an outer operation and we just made a shift, it is
possible that we could have simplified the shift were it not
x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
INTVAL (XEXP (x, 1)));
- /* If we were doing a LSHIFTRT in a wider mode than it was originally,
+ /* If we were doing an LSHIFTRT in a wider mode than it was originally,
turn off all the bits that the shift would have turned off. */
if (orig_code == LSHIFTRT && result_mode != shift_mode)
x = simplify_and_const_int (NULL_RTX, shift_mode, x,
rtx insn;
rtx *pnotes;
{
- register rtx pat = *pnewpat;
+ rtx pat = *pnewpat;
int insn_code_number;
int num_clobbers_to_add = 0;
int i;
rtx notes = 0;
- rtx old_notes;
+ rtx dummy_insn;
/* If PAT is a PARALLEL, check to see if it contains the CLOBBER
we use to indicate that something didn't match. If we find such a
&& XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
return -1;
- /* Remove the old notes prior to trying to recognize the new pattern. */
- old_notes = REG_NOTES (insn);
- REG_NOTES (insn) = 0;
+ /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
+ instruction for pattern recognition. */
+ dummy_insn = shallow_copy_rtx (insn);
+ PATTERN (dummy_insn) = pat;
+ REG_NOTES (dummy_insn) = 0;
- insn_code_number = recog (pat, insn, &num_clobbers_to_add);
+ insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
/* If it isn't, there is the possibility that we previously had an insn
that clobbered some register as a side effect, but the combined
if (pos == 1)
pat = XVECEXP (pat, 0, 0);
- insn_code_number = recog (pat, insn, &num_clobbers_to_add);
+ PATTERN (dummy_insn) = pat;
+ insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
}
/* Recognize all noop sets, these will be killed by followup pass. */
if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
- REG_NOTES (insn) = old_notes;
-
/* If we had any clobbers to add, make a new pattern than contains
them. Then check to make sure that all of them are dead. */
if (num_clobbers_to_add)
static rtx
gen_lowpart_for_combine (mode, x)
enum machine_mode mode;
- register rtx x;
+ rtx x;
{
rtx result;
|| GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
+ /* simplify_gen_subreg does not know how to handle the case where we try
+ to convert an integer constant to a vector.
+ ??? We could try to teach it to generate CONST_VECTORs. */
+ if (GET_MODE (x) == VOIDmode && VECTOR_MODE_P (mode))
+ return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
+
/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
won't know what to do. So we will strip off the SUBREG here and
process normally. */
if (GET_CODE (x) == MEM)
{
- register int offset = 0;
+ int offset = 0;
/* Refuse to work on a volatile memory ref or one with a mode-dependent
address. */
unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
temp >>= INTVAL (XEXP (op0, 1));
- op1 = GEN_INT (trunc_int_for_mode (temp, mode));
+ op1 = gen_int_mode (temp, mode);
op0 = XEXP (op0, 0);
continue;
}
&& XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
&& (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
MODE_INT, 1)) != BLKmode
- && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
- || ((unsigned HOST_WIDE_INT) -const_op
- <= GET_MODE_MASK (tmode))))
+ && (((unsigned HOST_WIDE_INT) const_op
+ + (GET_MODE_MASK (tmode) >> 1) + 1)
+ <= GET_MODE_MASK (tmode)))
{
op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
continue;
&& XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
&& (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
MODE_INT, 1)) != BLKmode
- && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
- || ((unsigned HOST_WIDE_INT) -const_op
- <= GET_MODE_MASK (tmode))))
+ && (((unsigned HOST_WIDE_INT) const_op
+ + (GET_MODE_MASK (tmode) >> 1) + 1)
+ <= GET_MODE_MASK (tmode)))
{
rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
rtx add_const = XEXP (XEXP (op0, 0), 1);
&& mode_width <= HOST_BITS_PER_WIDE_INT
&& (nonzero_bits (XEXP (op0, 0), mode)
& (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
- && (const_op == 0
- || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
- < mode_width)))
- {
+ && (((unsigned HOST_WIDE_INT) const_op
+ + (GET_CODE (op0) != LSHIFTRT
+ ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
+ + 1)
+ : 0))
+ <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
+ {
+ /* If the shift was logical, then we must make the condition
+ unsigned. */
+ if (GET_CODE (op0) == LSHIFTRT)
+ code = unsigned_condition (code);
+
const_op <<= INTVAL (XEXP (op0, 1));
op1 = GEN_INT (const_op);
op0 = XEXP (op0, 0);
/* Now make any compound operations involved in this comparison. Then,
check for an outmost SUBREG on OP0 that is not doing anything or is
- paradoxical. The latter case can only occur when it is known that the
- "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
- We can never remove a SUBREG for a non-equality comparison because the
- sign bit is in a different place in the underlying object. */
+ paradoxical. The latter transformation must only be performed when
+ it is known that the "extra" bits will be the same in op0 and op1 or
+ that they don't matter. There are three cases to consider:
+
+ 1. SUBREG_REG (op0) is a register. In this case the bits are don't
+ care bits and we can assume they have any convenient value. So
+ making the transformation is safe.
+
+ 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
+ In this case the upper bits of op0 are undefined. We should not make
+ the simplification in that case as we do not know the contents of
+ those bits.
+
+ 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
+ NIL. In that case we know those bits are zeros or ones. We must
+ also be sure that they are the same as the upper bits of op1.
+
+ We can never remove a SUBREG for a non-equality comparison because
+ the sign bit is in a different place in the underlying object. */
op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
op1 = make_compound_operation (op1, SET);
if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
+ /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
+ implemented. */
+ && GET_CODE (SUBREG_REG (op0)) == REG
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
- && (code == NE || code == EQ)
- && ((GET_MODE_SIZE (GET_MODE (op0))
- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
+ && (code == NE || code == EQ))
{
- op0 = SUBREG_REG (op0);
- op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
- }
+ if (GET_MODE_SIZE (GET_MODE (op0))
+ > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
+ {
+ op0 = SUBREG_REG (op0);
+ op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
+ }
+ else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
+ <= HOST_BITS_PER_WIDE_INT)
+ && (nonzero_bits (SUBREG_REG (op0),
+ GET_MODE (SUBREG_REG (op0)))
+ & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
+ {
+ tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
- else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
- && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
- && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
- && (code == NE || code == EQ)
- && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
- <= HOST_BITS_PER_WIDE_INT)
- && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
- & ~GET_MODE_MASK (GET_MODE (op0))) == 0
- && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
- op1),
- (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
- & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
- op0 = SUBREG_REG (op0), op1 = tem;
+ if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
+ & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
+ op0 = SUBREG_REG (op0), op1 = tem;
+ }
+ }
/* We now do the opposite procedure: Some machines don't have compare
insns in all modes. If OP0's mode is an integer mode smaller than a
tmode = GET_MODE_WIDER_MODE (tmode))
if (have_insn_for (COMPARE, tmode))
{
+ int zero_extended;
+
/* If the only nonzero bits in OP0 and OP1 are those in the
narrower mode and this is an equality or unsigned comparison,
we can use the wider mode. Similarly for sign-extended
values, in which case it is true for all comparisons. */
- if (((code == EQ || code == NE
- || code == GEU || code == GTU || code == LEU || code == LTU)
- && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
- && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
+ zero_extended = ((code == EQ || code == NE
+ || code == GEU || code == GTU
+ || code == LEU || code == LTU)
+ && (nonzero_bits (op0, tmode)
+ & ~GET_MODE_MASK (mode)) == 0
+ && ((GET_CODE (op1) == CONST_INT
+ || (nonzero_bits (op1, tmode)
+ & ~GET_MODE_MASK (mode)) == 0)));
+
+ if (zero_extended
|| ((num_sign_bit_copies (op0, tmode)
> GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
&& (num_sign_bit_copies (op1, tmode)
XEXP (op0, 1)));
op0 = gen_lowpart_for_combine (tmode, op0);
+ if (zero_extended && GET_CODE (op1) == CONST_INT)
+ op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
op1 = gen_lowpart_for_combine (tmode, op1);
break;
}
combine_reversed_comparison_code (exp)
rtx exp;
{
- enum rtx_code code1 = reversed_comparison_code (exp, NULL);
- rtx x;
-
- if (code1 != UNKNOWN
- || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
- return code1;
- /* Otherwise try and find where the condition codes were last set and
- use that. */
- x = get_last_value (XEXP (exp, 0));
- if (!x || GET_CODE (x) != COMPARE)
- return UNKNOWN;
- return reversed_comparison_code_parts (GET_CODE (exp),
- XEXP (x, 0), XEXP (x, 1), NULL);
+ enum rtx_code code1 = reversed_comparison_code (exp, NULL);
+ rtx x;
+
+ if (code1 != UNKNOWN
+ || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
+ return code1;
+ /* Otherwise try and find where the condition codes were last set and
+ use that. */
+ x = get_last_value (XEXP (exp, 0));
+ if (!x || GET_CODE (x) != COMPARE)
+ return UNKNOWN;
+ return reversed_comparison_code_parts (GET_CODE (exp),
+ XEXP (x, 0), XEXP (x, 1), NULL);
}
/* Return comparison with reversed code of EXP and operands OP0 and OP1.
Return NULL_RTX in case we fail to do the reversal. */
update_table_tick (x)
rtx x;
{
- register enum rtx_code code = GET_CODE (x);
- register const char *fmt = GET_RTX_FORMAT (code);
- register int i;
+ enum rtx_code code = GET_CODE (x);
+ const char *fmt = GET_RTX_FORMAT (code);
+ int i;
if (code == REG)
{
if (value)
{
+ enum machine_mode mode = GET_MODE (reg);
subst_low_cuid = INSN_CUID (insn);
- reg_last_set_mode[regno] = GET_MODE (reg);
- reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
+ reg_last_set_mode[regno] = mode;
+ if (GET_MODE_CLASS (mode) == MODE_INT
+ && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
+ mode = nonzero_bits_mode;
+ reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
reg_last_set_sign_bit_copies[regno]
= num_sign_bit_copies (value, GET_MODE (reg));
}
record_dead_and_set_regs (insn)
rtx insn;
{
- register rtx link;
+ rtx link;
unsigned int i;
for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
if (GET_CODE (insn) == CALL_INSN)
{
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
- if (call_used_regs[i])
+ if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
{
reg_last_set_value[i] = 0;
reg_last_set_mode[i] = 0;
}
last_call_cuid = mem_last_set = INSN_CUID (insn);
+
+ /* Don't bother recording what this insn does. It might set the
+ return value register, but we can't combine into a call
+ pattern anyway, so there's no point trying (and it may cause
+ a crash, if e.g. we wind up asking for last_set_value of a
+ SUBREG of the return value register). */
+ return;
}
note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
if (reg_last_set[regno] == insn)
{
- if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
+ if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
}
it's either a hard register, set more than once, or it's a live
at the beginning of the function, return 0.
- Because if it's not live at the beginnning of the function then the reg
+ Because if it's not live at the beginning of the function then the reg
is always set before being used (is never used without being set).
And, if it's set only once, and it's always set before use, then all
uses must have the same last value, even if it's not from this basic
static int
use_crosses_set_p (x, from_cuid)
- register rtx x;
+ rtx x;
int from_cuid;
{
- register const char *fmt;
- register int i;
- register enum rtx_code code = GET_CODE (x);
+ const char *fmt;
+ int i;
+ enum rtx_code code = GET_CODE (x);
if (code == REG)
{
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
return 1;
case CONST_INT:
case CONST:
case CONST_DOUBLE:
+ case CONST_VECTOR:
case PC:
case ADDR_VEC:
case ADDR_DIFF_VEC:
{
/* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
the address. */
- register rtx testreg = SET_DEST (x);
+ rtx testreg = SET_DEST (x);
while (GET_CODE (testreg) == SUBREG
|| GET_CODE (testreg) == ZERO_EXTRACT
/* Recursively scan the operands of this expression. */
{
- register const char *fmt = GET_RTX_FORMAT (code);
+ const char *fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
mark_used_regs_combine (XEXP (x, i));
else if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = 0; j < XVECLEN (x, i); j++)
mark_used_regs_combine (XVECEXP (x, i, j));
unsigned int regno;
rtx insn;
{
- register rtx note = find_regno_note (insn, REG_DEAD, regno);
+ rtx note = find_regno_note (insn, REG_DEAD, regno);
if (note)
{
rtx to_insn;
rtx *pnotes;
{
- register const char *fmt;
- register int len, i;
- register enum rtx_code code = GET_CODE (x);
+ const char *fmt;
+ int len, i;
+ enum rtx_code code = GET_CODE (x);
if (code == REG)
{
unsigned int regno = REGNO (x);
- register rtx where_dead = reg_last_death[regno];
- register rtx before_dead, after_dead;
+ rtx where_dead = reg_last_death[regno];
+ rtx before_dead, after_dead;
/* Don't move the register if it gets killed in between from and to */
if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
{
if (fmt[i] == 'E')
{
- register int j;
+ int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
to_insn, pnotes);
place = i3;
break;
+ case REG_VTABLE_REF:
+ /* ??? Should remain with *a particular* memory load. Given the
+ nature of vtable data, the last insn seems relatively safe. */
+ place = i3;
+ break;
+
case REG_NON_LOCAL_GOTO:
if (GET_CODE (i3) == JUMP_INSN)
place = i3;
else if (i2 && GET_CODE (i2) == JUMP_INSN)
place = i2;
else
- abort();
+ abort ();
break;
case REG_EH_REGION:
else
place = i2;
}
+
+ /* Don't attach REG_LABEL note to a JUMP_INSN which has
+ JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
+ if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
+ {
+ if (JUMP_LABEL (place) != XEXP (note, 0))
+ abort ();
+ if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
+ LABEL_NUSES (JUMP_LABEL (place))--;
+ place = 0;
+ }
+ if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
+ {
+ if (JUMP_LABEL (place2) != XEXP (note, 0))
+ abort ();
+ if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
+ LABEL_NUSES (JUMP_LABEL (place2))--;
+ place2 = 0;
+ }
break;
case REG_NONNEG:
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