* lib/target-supports.exp (check_effective_target_vect_int): New

[pf3gnuchains/gcc-fork.git] / gcc / combine.c

diff --git a/gcc/combine.c b/gcc/combine.c
index 24ebbc9..93c0990 100644 (file)
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -1176,6 +1176,8 @@ can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
       /* Don't substitute into an incremented register.  */
       || FIND_REG_INC_NOTE (i3, dest)
       || (succ && FIND_REG_INC_NOTE (succ, dest))
+      /* Don't substitute into a non-local goto, this confuses CFG.  */
+      || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
 #if 0
       /* Don't combine the end of a libcall into anything.  */
       /* ??? This gives worse code, and appears to be unnecessary, since no
@@ -6904,11 +6906,6 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
     return gen_lowpart (mode, x);
 
-  /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
-     MASK are already known to be zero in X, we need not do anything.  */
-  if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
-    return x;
-
   switch (code)
     {
     case CLOBBER:
@@ -7341,6 +7338,7 @@ force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
         in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
         which is equal to STORE_FLAG_VALUE.  */
       if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
+         && GET_MODE (XEXP (x, 0)) == mode
          && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
          && (nonzero_bits (XEXP (x, 0), mode)
              == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
@@ -9024,6 +9022,26 @@ simplify_shift_const (rtx x, enum rtx_code code,
              varop = XEXP (varop, 0);
              continue;
            }
+
+         /* Check for 'PLUS signbit', which is the canonical form of 'XOR
+            signbit', and attempt to change the PLUS to an XOR and move it to
+            the outer operation as is done above in the AND/IOR/XOR case
+            leg for shift(logical). See details in logical handling above
+            for reasoning in doing so.  */
+         if (code == LSHIFTRT
+             && GET_CODE (XEXP (varop, 1)) == CONST_INT
+             && mode_signbit_p (result_mode, XEXP (varop, 1))
+             && (new = simplify_binary_operation (code, result_mode,
+                                                  XEXP (varop, 1),
+                                                  GEN_INT (count))) != 0
+             && GET_CODE (new) == CONST_INT
+             && merge_outer_ops (&outer_op, &outer_const, XOR,
+                                 INTVAL (new), result_mode, &complement_p))
+           {
+             varop = XEXP (varop, 0);
+             continue;
+           }
+
          break;
 
        case MINUS:
@@ -9327,13 +9345,8 @@ gen_lowpart_for_combine (enum machine_mode mode, rtx x)
 
   result = gen_lowpart_common (mode, x);
 #ifdef CANNOT_CHANGE_MODE_CLASS
-  if (result != 0
-      && GET_CODE (result) == SUBREG
-      && REG_P (SUBREG_REG (result))
-      && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
-    bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
-                                     * MAX_MACHINE_MODE
-                                     + GET_MODE (result));
+  if (result != 0 && GET_CODE (result) == SUBREG)
+    record_subregs_of_mode (result);
 #endif
 
   if (result)