PR c++/15815

[pf3gnuchains/gcc-fork.git] / gcc / bt-load.c

diff --git a/gcc/bt-load.c b/gcc/bt-load.c
index 366e678..ae8c2e0 100644 (file)
--- a/gcc/bt-load.c
+++ b/gcc/bt-load.c
@@ -195,7 +195,7 @@ find_btr_reference (rtx *px, void *preg)
   if (px == preg)
     return -1;
   x = *px;
-  if (GET_CODE (x) != REG)
+  if (!REG_P (x))
     return 0;
   regno = REGNO (x);
   for (i = hard_regno_nregs[regno][GET_MODE (x)] - 1; i >= 0; i--)
@@ -234,7 +234,7 @@ insn_sets_btr_p (rtx insn, int check_const, int *regno)
       if (GET_CODE (dest) == SUBREG)
        dest = XEXP (dest, 0);
 
-      if (GET_CODE (dest) == REG
+      if (REG_P (dest)
          && TEST_HARD_REG_BIT (all_btrs, REGNO (dest)))
        {
          if (btr_referenced_p (src, NULL))
@@ -427,7 +427,7 @@ note_btr_set (rtx dest, rtx set ATTRIBUTE_UNUSED, void *data)
   defs_uses_info *info = data;
   int regno, end_regno;
 
-  if (GET_CODE (dest) != REG)
+  if (!REG_P (dest))
     return;
   regno = REGNO (dest);
   end_regno = regno + hard_regno_nregs[regno][GET_MODE (dest)];
@@ -1267,7 +1267,7 @@ migrate_btr_def (btr_def def, int min_cost)
   bitmap_copy (live_range, def->live_range);
 
 #ifdef INSN_SCHEDULING
-  if ((*targetm.sched.use_dfa_pipeline_interface) ())
+  if (targetm.sched.use_dfa_pipeline_interface ())
     def_latency = insn_default_latency (def->insn);
   else
     def_latency = result_ready_cost (def->insn);
@@ -1385,8 +1385,7 @@ migrate_btr_defs (enum reg_class btr_class, int allow_callee_save)
 
   while (!fibheap_empty (all_btr_defs))
     {
-      btr_def def =
-       (btr_def) fibheap_extract_min (all_btr_defs);
+      btr_def def = fibheap_extract_min (all_btr_defs);
       int min_cost = -fibheap_min_key (all_btr_defs);
       if (migrate_btr_def (def, min_cost))
        {
@@ -1412,14 +1411,14 @@ migrate_btr_defs (enum reg_class btr_class, int allow_callee_save)
 }
 
 void
-branch_target_load_optimize (rtx insns, bool after_prologue_epilogue_gen)
+branch_target_load_optimize (bool after_prologue_epilogue_gen)
 {
-  enum reg_class class = (*targetm.branch_target_register_class) ();
+  enum reg_class class = targetm.branch_target_register_class ();
   if (class != NO_REGS)
     {
       /* Initialize issue_rate.  */
       if (targetm.sched.issue_rate)
-       issue_rate = (*targetm.sched.issue_rate) ();
+       issue_rate = targetm.sched.issue_rate ();
       else
        issue_rate = 1;
 
@@ -1430,12 +1429,12 @@ branch_target_load_optimize (rtx insns, bool after_prologue_epilogue_gen)
       cleanup_cfg (optimize ? CLEANUP_EXPENSIVE : 0);
 #endif
 
-      life_analysis (insns, NULL, 0);
+      life_analysis (NULL, 0);
 
       /* Dominator info is also needed for migrate_btr_def.  */
       calculate_dominance_info (CDI_DOMINATORS);
       migrate_btr_defs (class,
-                      ((*targetm.branch_target_register_callee_saved)
+                      (targetm.branch_target_register_callee_saved
                        (after_prologue_epilogue_gen)));
 
       free_dominance_info (CDI_DOMINATORS);