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[pf3gnuchains/pf3gnuchains3x.git] / bfd / cpu-ia64-opc.c

diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c
index a3adc47..b797e44 100644 (file)
--- a/bfd/cpu-ia64-opc.c
+++ b/bfd/cpu-ia64-opc.c
@@ -1,22 +1,23 @@
-/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
+/* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009
    Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
-This file is part of BFD, the Binary File Descriptor library.
+   This file is part of BFD, the Binary File Descriptor library.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* Logically, this code should be part of libopcode but since some of
    the operand insertion/extraction functions help bfd to implement
@@ -80,19 +81,19 @@ ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
 static const char*
 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 {
-  ia64_insn new = 0;
+  ia64_insn new_insn = 0;
   int i;
 
   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
     {
-      new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
-             << self->field[i].shift);
+      new_insn |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+                 << self->field[i].shift);
       value >>= self->field[i].bits;
     }
   if (value)
     return "integer operand out of range";
 
-  *code |= new;
+  *code |= new_insn;
   return 0;
 }
 
@@ -162,22 +163,22 @@ ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
                 ia64_insn *code, int scale)
 {
   BFD_HOST_64_BIT svalue = value, sign_bit = 0;
-  ia64_insn new = 0;
+  ia64_insn new_insn = 0;
   int i;
 
   svalue >>= scale;
 
   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
     {
-      new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
-             << self->field[i].shift);
+      new_insn |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
+                 << self->field[i].shift);
       sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
       svalue >>= self->field[i].bits;
     }
   if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
     return "integer operand out of range";
 
-  *code |= new;
+  *code |= new_insn;
   return 0;
 }