+DEFTREECODE (STATEMENT_LIST, "statement_list", tcc_exceptional, 0)
+
+/* Value handles. Artificial nodes to represent expressions in
+ partial redundancy elimination (tree-ssa-pre.c). These nodes are
+ used for expression canonicalization. If two expressions compute
+ the same value, they will be assigned the same value handle. */
+DEFTREECODE (VALUE_HANDLE, "value_handle", tcc_exceptional, 0)
+
+/* Predicate assertion. Artificial expression generated by the optimizers
+ to keep track of predicate values. This expression may only appear on
+ the RHS of assignments.
+
+ Given X = ASSERT_EXPR <Y, EXPR>, the optimizers can infer
+ two things:
+
+ 1- X is a copy of Y.
+ 2- EXPR is a GIMPLE conditional expression (as defined by
+ is_gimple_condexpr) and is known to be true.
+
+ The type of the expression is the same as Y. */
+DEFTREECODE (ASSERT_EXPR, "assert_expr", tcc_expression, 2)
+
+/* Base class information. Holds information about a class as a
+ baseclass of itself or another class. */
+DEFTREECODE (TREE_BINFO, "tree_binfo", tcc_exceptional, 0)
+
+/* Records the size for an expression of variable size type. This is
+ for use in contexts in which we are accessing the entire object,
+ such as for a function call, or block copy.
+ Operand 0 is the real expression.
+ Operand 1 is the size of the type in the expression. */
+DEFTREECODE (WITH_SIZE_EXPR, "with_size_expr", tcc_expression, 2)
+
+/* Extract elements from two input vectors Operand 0 and Operand 1
+ size VS, according to the offset OFF defined by Operand 2 as
+ follows:
+ If OFF > 0, the last VS - OFF elements of vector OP0 are concatenated to
+ the first OFF elements of the vector OP1.
+ If OFF == 0, then the returned vector is OP1.
+ On different targets OFF may take different forms; It can be an address, in
+ which case its low log2(VS)-1 bits define the offset, or it can be a mask
+ generated by the builtin targetm.vectorize.mask_for_load_builtin_decl. */
+DEFTREECODE (REALIGN_LOAD_EXPR, "realign_load", tcc_expression, 3)
+
+/* Low-level memory addressing. Operands are SYMBOL (static or global
+ variable), BASE (register), INDEX (register), STEP (integer constant),
+ OFFSET (integer constant). Corresponding address is
+ SYMBOL + BASE + STEP * INDEX + OFFSET. Only variations and values valid on
+ the target are allowed.
+
+ The sixth argument is the reference to the original memory access, which
+ is preserved for the purposes of the RTL alias analysis. The seventh
+ argument is a tag representing results of the tree level alias analysis. */
+
+DEFTREECODE (TARGET_MEM_REF, "target_mem_ref", tcc_reference, 7)
+
+/* Reduction operations.
+ Operations that take a vector of elements and "reduce" it to a scalar
+ result (e.g. summing the elements of the vector, finding the minimum over
+ the vector elements, etc).
+ Operand 0 is a vector; the first element in the vector has the result.
+ Operand 1 is a vector. */
+DEFTREECODE (REDUC_MAX_EXPR, "reduc_max_expr", tcc_unary, 1)
+DEFTREECODE (REDUC_MIN_EXPR, "reduc_min_expr", tcc_unary, 1)
+DEFTREECODE (REDUC_PLUS_EXPR, "reduc_plus_expr", tcc_unary, 1)
+
+/* Whole vector left/right shift in bits.
+ Operand 0 is a vector to be shifted.
+ Operand 1 is an integer shift amount in bits. */
+DEFTREECODE (VEC_LSHIFT_EXPR, "vec_lshift_expr", tcc_binary, 2)
+DEFTREECODE (VEC_RSHIFT_EXPR, "vec_rshift_expr", tcc_binary, 2)