+/* When we have more one region, we need to change the original RTL
+ code after coloring. Let us consider two allocnos representing the
+ same pseudo-register outside and inside a region respectively.
+ They can get different hard-registers. The reload pass works on
+ pseudo registers basis and there is no way to say the reload that
+ pseudo could be in different registers and it is even more
+ difficult to say in what places of the code the pseudo should have
+ particular hard-registers. So in this case IRA has to create and
+ use a new pseudo-register inside the region and adds code to move
+ allocno values on the region's borders. This is done by the code
+ in this file.
+
+ The code makes top-down traversal of the regions and generate new
+ pseudos and the move code on the region borders. In some
+ complicated cases IRA can create a new pseudo used temporarily to
+ move allocno values when a swap of values stored in two
+ hard-registers is needed (e.g. two allocnos representing different
+ pseudos outside region got respectively hard registers 1 and 2 and
+ the corresponding allocnos inside the region got respectively hard
+ registers 2 and 1). At this stage, the new pseudo is marked as
+ spilled.
+
+ IRA still creates the pseudo-register and the moves on the region
+ borders even when the both corresponding allocnos were assigned to
+ the same hard-register. It is done because, if the reload pass for
+ some reason spills a pseudo-register representing the original
+ pseudo outside or inside the region, the effect will be smaller
+ because another pseudo will still be in the hard-register. In most
+ cases, this is better then spilling the original pseudo in its
+ whole live-range. If reload does not change the allocation for the
+ two pseudo-registers, the trivial move will be removed by
+ post-reload optimizations.
+
+ IRA does not generate a new pseudo and moves for the allocno values
+ if the both allocnos representing an original pseudo inside and
+ outside region assigned to the same hard register when the register
+ pressure in the region for the corresponding pressure class is less
+ than number of available hard registers for given pressure class.
+
+ IRA also does some optimizations to remove redundant moves which is
+ transformed into stores by the reload pass on CFG edges
+ representing exits from the region.
+
+ IRA tries to reduce duplication of code generated on CFG edges
+ which are enters and exits to/from regions by moving some code to
+ the edge sources or destinations when it is possible. */