+@smallexample
+@{ target @{ ! "hppa*-*-* ia64*-*-*" @} @}
+@{ target @{ powerpc*-*-* && lp64 @} @}
+@{ xfail @{ lp64 || vect_no_align @} @}
+@end smallexample
+
+@node Effective-Target Keywords
+@subsection Keywords describing target attributes
+
+Effective-target keywords identify sets of targets that support
+particular functionality. They are used to limit tests to be run only
+for particular targets, or to specify that particular sets of targets
+are expected to fail some tests.
+
+Effective-target keywords are defined in @file{lib/target-supports.exp} in
+the GCC testsuite, with the exception of those that are documented as
+being local to a particular test directory.
+
+The @samp{effective target} takes into account all of the compiler options
+with which the test will be compiled, including the multilib options.
+By convention, keywords ending in @code{_nocache} can also include options
+specified for the particular test in an earlier @code{dg-options} or
+@code{dg-add-options} directive.
+
+@subsubsection Data type sizes
+
+@table @code
+@item ilp32
+Target has 32-bit @code{int}, @code{long}, and pointers.
+
+@item lp64
+Target has 32-bit @code{int}, 64-bit @code{long} and pointers.
+
+@item llp64
+Target has 32-bit @code{int} and @code{long}, 64-bit @code{long long}
+and pointers.
+
+@item double64
+Target has 64-bit @code{double}.
+
+@item double64plus
+Target has @code{double} that is 64 bits or longer.
+
+@item int32plus
+Target has @code{int} that is at 32 bits or longer.
+
+@item int16
+Target has @code{int} that is 16 bits or shorter.
+
+@item large_double
+Target supports @code{double} that is longer than @code{float}.
+
+@item large_long_double
+Target supports @code{long double} that is longer than @code{double}.
+
+@item ptr32plus
+Target has pointers that are 32 bits or longer.
+
+@item size32plus
+Target supports array and structure sizes that are 32 bits or longer.
+
+@item 4byte_wchar_t
+Target has @code{wchar_t} that is at least 4 bytes.
+@end table
+
+@subsubsection Fortran-specific attributes
+
+@table @code
+@item fortran_integer_16
+Target supports Fortran @code{integer} that is 16 bytes or longer.
+
+@item fortran_large_int
+Target supports Fortran @code{integer} kinds larger than @code{integer(8)}.
+
+@item fortran_large_real
+Target supports Fortran @code{real} kinds larger than @code{real(8)}.
+@end table
+
+@subsubsection Vector-specific attributes
+
+@table @code
+@item vect_condition
+Target supports vector conditional operations.
+
+@item vect_double
+Target supports hardware vectors of @code{double}.
+
+@item vect_float
+Target supports hardware vectors of @code{float}.
+
+@item vect_int
+Target supports hardware vectors of @code{int}.
+
+@item vect_int_mult
+Target supports a vector widening multiplication of @code{short} operands
+into an @code{int} result, or supports promotion (unpacking) from
+@code{short} to @code{int} and a non-widening multiplication of @code{int}.
+
+@item vect_long
+Target supports hardware vectors of @code{long}.
+
+@item vect_long_long
+Target supports hardware vectors of @code{long long}.
+
+@item vect_aligned_arrays
+Target aligns arrays to vector alignment boundary.
+
+@item vect_hw_misalign
+Target supports a vector misalign access.
+
+@item vect_no_align
+Target does not support a vector alignment mechanism.
+
+@item vect_no_int_max
+Target does not support a vector max instruction on @code{int}.
+
+@item vect_no_int_add
+Target does not support a vector add instruction on @code{int}.
+
+@item vect_no_bitwise
+Target does not support vector bitwise instructions.
+
+@item vect_char_mult
+Target supports @code{vector char} multiplication.
+
+@item vect_short_mult
+Target supports @code{vector short} multiplication.
+
+@item vect_int_mult
+Target supports @code{vector int} multiplication.
+
+@item vect_extract_even_odd
+Target supports vector even/odd element extraction.
+
+@item vect_extract_even_odd_wide
+Target supports vector even/odd element extraction of vectors with elements
+@code{SImode} or larger.
+
+@item vect_interleave
+Target supports vector interleaving.
+
+@item vect_strided
+Target supports vector interleaving and extract even/odd.
+
+@item vect_strided_wide
+Target supports vector interleaving and extract even/odd for wide
+element types.
+
+@item vect_perm
+Target supports vector permutation.
+
+@item vect_shift
+Target supports a hardware vector shift operation.
+
+@item vect_widen_sum_hi_to_si
+Target supports a vector widening summation of @code{short} operands
+into @code{int} results, or can promote (unpack) from @code{short}
+to @code{int}.
+
+@item vect_widen_sum_qi_to_hi
+Target supports a vector widening summation of @code{char} operands
+into @code{short} results, or can promote (unpack) from @code{char}
+to @code{short}.
+
+@item vect_widen_sum_qi_to_si
+Target supports a vector widening summation of @code{char} operands
+into @code{int} results.
+
+@item vect_widen_mult_qi_to_hi
+Target supports a vector widening multiplication of @code{char} operands
+into @code{short} results, or can promote (unpack) from @code{char} to
+@code{short} and perform non-widening multiplication of @code{short}.
+
+@item vect_widen_mult_hi_to_si
+Target supports a vector widening multiplication of @code{short} operands
+into @code{int} results, or can promote (unpack) from @code{short} to
+@code{int} and perform non-widening multiplication of @code{int}.
+
+@item vect_sdot_qi
+Target supports a vector dot-product of @code{signed char}.
+
+@item vect_udot_qi
+Target supports a vector dot-product of @code{unsigned char}.
+
+@item vect_sdot_hi
+Target supports a vector dot-product of @code{signed short}.
+
+@item vect_udot_hi
+Target supports a vector dot-product of @code{unsigned short}.
+
+@item vect_pack_trunc
+Target supports a vector demotion (packing) of @code{short} to @code{char}
+and from @code{int} to @code{short} using modulo arithmetic.
+
+@item vect_unpack
+Target supports a vector promotion (unpacking) of @code{char} to @code{short}
+and from @code{char} to @code{int}.
+
+@item vect_intfloat_cvt
+Target supports conversion from @code{signed int} to @code{float}.
+
+@item vect_uintfloat_cvt
+Target supports conversion from @code{unsigned int} to @code{float}.
+
+@item vect_floatint_cvt
+Target supports conversion from @code{float} to @code{signed int}.
+
+@item vect_floatuint_cvt
+Target supports conversion from @code{float} to @code{unsigned int}.
+@end table
+
+@subsubsection Thread Local Storage attributes
+
+@table @code
+@item tls
+Target supports thread-local storage.
+
+@item tls_native
+Target supports native (rather than emulated) thread-local storage.
+
+@item tls_runtime
+Test system supports executing TLS executables.
+@end table
+
+@subsubsection Decimal floating point attributes
+
+@table @code
+@item dfp
+Targets supports compiling decimal floating point extension to C.
+
+@item dfp_nocache
+Including the options used to compile this particular test, the
+target supports compiling decimal floating point extension to C.
+
+@item dfprt
+Test system can execute decimal floating point tests.
+
+@item dfprt_nocache
+Including the options used to compile this particular test, the
+test system can execute decimal floating point tests.
+
+@item hard_dfp
+Target generates decimal floating point instructions with current options.
+@end table
+
+@subsubsection ARM-specific attributes
+
+@table @code
+@item arm32
+ARM target generates 32-bit code.
+
+@item arm_eabi
+ARM target adheres to the ABI for the ARM Architecture.
+
+@item arm_hard_vfp_ok
+ARM target supports @code{-mfpu=vfp -mfloat-abi=hard}.
+Some multilibs may be incompatible with these options.
+
+@item arm_iwmmxt_ok
+ARM target supports @code{-mcpu=iwmmxt}.
+Some multilibs may be incompatible with this option.
+
+@item arm_neon
+ARM target supports generating NEON instructions.
+
+@item arm_neon_hw
+Test system supports executing NEON instructions.
+
+@item arm_neon_ok
+ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp}.
+Some multilibs may be incompatible with these options.
+
+@item arm_thumb1_ok
+ARM target generates Thumb-1 code for @code{-mthumb}.
+
+@item arm_thumb2_ok
+ARM target generates Thumb-2 code for @code{-mthumb}.
+
+@item arm_vfp_ok
+ARM target supports @code{-mfpu=vfp -mfloat-abi=softfp}.
+Some multilibs may be incompatible with these options.
+@end table
+
+@subsubsection MIPS-specific attributes
+
+@table @code
+@item mips64
+MIPS target supports 64-bit instructions.
+
+@item nomips16
+MIPS target does not produce MIPS16 code.
+
+@item mips16_attribute
+MIPS target can generate MIPS16 code.
+
+@item mips_loongson
+MIPS target is a Loongson-2E or -2F target using an ABI that supports
+the Loongson vector modes.
+
+@item mips_newabi_large_long_double
+MIPS target supports @code{long double} larger than @code{double}
+when using the new ABI.
+
+@item mpaired_single
+MIPS target supports @code{-mpaired-single}.
+@end table
+
+@subsubsection PowerPC-specific attributes
+
+@table @code
+@item powerpc64
+Test system supports executing 64-bit instructions.
+
+@item powerpc_altivec
+PowerPC target supports AltiVec.
+
+@item powerpc_altivec_ok
+PowerPC target supports @code{-maltivec}.
+
+@item powerpc_fprs
+PowerPC target supports floating-point registers.
+
+@item powerpc_hard_double
+PowerPC target supports hardware double-precision floating-point.
+
+@item powerpc_ppu_ok
+PowerPC target supports @code{-mcpu=cell}.
+
+@item powerpc_spe
+PowerPC target supports PowerPC SPE.
+
+@item powerpc_spe_nocache
+Including the options used to compile this particular test, the
+PowerPC target supports PowerPC SPE.
+
+@item powerpc_spu
+PowerPC target supports PowerPC SPU.
+
+@item spu_auto_overlay
+SPU target has toolchain that supports automatic overlay generation.
+
+@item powerpc_vsx_ok
+PowerPC target supports @code{-mvsx}.
+
+@item powerpc_405_nocache
+Including the options used to compile this particular test, the
+PowerPC target supports PowerPC 405.
+
+@item vmx_hw
+PowerPC target supports executing AltiVec instructions.
+@end table
+
+@subsubsection Other hardware attributes
+
+@table @code
+@item avx
+Target supports compiling AVX instructions.
+
+@item cell_hw
+Test system can execute AltiVec and Cell PPU instructions.
+
+@item coldfire_fpu
+Target uses a ColdFire FPU.
+
+@item hard_float
+Target supports FPU instructions.
+
+@item sync_char_short
+Target supports atomic operations on @code{char} and @code{short}.
+
+@item sync_int_long
+Target supports atomic operations on @code{int} and @code{long}.
+
+@item ultrasparc_hw
+Test environment appears to run executables on a simulator that
+accepts only @code{EM_SPARC} executables and chokes on @code{EM_SPARC32PLUS}
+or @code{EM_SPARCV9} executables.
+
+@item vect_cmdline_needed
+Target requires a command line argument to enable a SIMD instruction set.
+@end table
+
+@subsubsection Environment attributes
+
+@table @code
+@item c
+The language for the compiler under test is C.
+
+@item c++
+The language for the compiler under test is C++.
+
+@item c99_runtime
+Target provides a full C99 runtime.
+
+@item correct_iso_cpp_string_wchar_protos
+Target @code{string.h} and @code{wchar.h} headers provide C++ required
+overloads for @code{strchr} etc. functions.
+
+@item dummy_wcsftime
+Target uses a dummy @code{wcsftime} function that always returns zero.
+
+@item fd_truncate
+Target can truncate a file from a file descriptor, as used by
+@file{libgfortran/io/unix.c:fd_truncate}; i.e. @code{ftruncate} or
+@code{chsize}.
+
+@item freestanding
+Target is @samp{freestanding} as defined in section 4 of the C99 standard.
+Effectively, it is a target which supports no extra headers or libraries
+other than what is considered essential.
+
+@item init_priority
+Target supports constructors with initialization priority arguments.
+
+@item inttypes_types
+Target has the basic signed and unsigned types in @code{inttypes.h}.
+This is for tests that GCC's notions of these types agree with those
+in the header, as some systems have only @code{inttypes.h}.
+
+@item lax_strtofp
+Target might have errors of a few ULP in string to floating-point
+conversion functions and overflow is not always detected correctly by
+those functions.
+
+@item newlib
+Target supports Newlib.
+
+@item pow10
+Target provides @code{pow10} function.
+
+@item pthread
+Target can compile using @code{pthread.h} with no errors or warnings.
+
+@item pthread_h
+Target has @code{pthread.h}.
+
+@item simulator
+Test system runs executables on a simulator (i.e. slowly) rather than
+hardware (i.e. fast).
+
+@item stdint_types
+Target has the basic signed and unsigned C types in @code{stdint.h}.
+This will be obsolete when GCC ensures a working @code{stdint.h} for
+all targets.
+
+@item trampolines
+Target supports trampolines.
+
+@item uclibc
+Target supports uClibc.
+
+@item unwrapped
+Target does not use a status wrapper.
+
+@item vxworks_kernel
+Target is a VxWorks kernel.
+
+@item vxworks_rtp
+Target is a VxWorks RTP.
+
+@item wchar
+Target supports wide characters.
+@end table
+
+@subsubsection Other attributes
+
+@table @code
+@item automatic_stack_alignment
+Target supports automatic stack alignment.
+
+@item cxa_atexit
+Target uses @code{__cxa_atexit}.
+
+@item default_packed
+Target has packed layout of structure members by default.