+ "TARGET_CPU_ZARCH"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0) (const_int 0))
+ (parallel
+ [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
+ (match_dup 1)))
+ (clobber (reg:CC 33))])
+ (parallel
+ [(set (match_dup 0) (neg:SI (match_dup 0)))
+ (clobber (reg:CC 33))])]
+ ""
+ [(set_attr "op_type" "NN")])
+
+(define_expand "sltu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sgtu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sleu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+(define_expand "sgeu"
+ [(match_operand:SI 0 "register_operand" "")]
+ "TARGET_CPU_ZARCH"
+ "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
+ operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
+
+
+;;
+;;- Multiply instructions.
+;;
+
+;
+; muldi3 instruction pattern(s).
+;
+
+(define_insn "*muldi3_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
+ (match_operand:DI 1 "register_operand" "0,0")))]
+ "TARGET_64BIT"
+ "@
+ msgfr\t%0,%2
+ msgf\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "imul")])
+
+(define_insn "muldi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
+ (match_operand:DI 2 "general_operand" "d,K,m")))]
+ "TARGET_64BIT"
+ "@
+ msgr\t%0,%2
+ mghi\t%0,%h2
+ msg\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RXY")
+ (set_attr "type" "imul")])
+
+;
+; mulsi3 instruction pattern(s).
+;
+
+(define_insn "*mulsi3_sign"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
+ (match_operand:SI 1 "register_operand" "0")))]
+ ""
+ "mh\t%0,%2"
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "imul")])
+
+(define_insn "mulsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,K,R,T")))]
+ ""
+ "@
+ msr\t%0,%2
+ mhi\t%0,%h2
+ ms\t%0,%2
+ msy\t%0,%2"
+ [(set_attr "op_type" "RRE,RI,RX,RXY")
+ (set_attr "type" "imul")])
+
+;
+; mulsidi3 instruction pattern(s).
+;
+
+(define_insn "mulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "%0,0"))
+ (sign_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
+ "!TARGET_64BIT"
+ "@
+ mr\t%0,%2
+ m\t%0,%2"
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "imul")])
+
+;
+; umulsidi3 instruction pattern(s).
+;
+
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "register_operand" "%0,0"))
+ (zero_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "@
+ mlr\t%0,%2
+ ml\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "imul")])
+
+;
+; muldf3 instruction pattern(s).
+;
+
+(define_expand "muldf3"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R")))]
+ "TARGET_HARD_FLOAT"
+ "")
+
+(define_insn "*muldf3"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+ "@
+ mdbr\t%0,%2
+ mdb\t%0,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
+(define_insn "*muldf3_ibm"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:DF 2 "general_operand" "f,R")))]
+ "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
+ "@
+ mdr\t%0,%2
+ md\t%0,%2"
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "fmuld")])
+
+(define_insn "*fmadddf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+ "@
+ madbr\t%0,%1,%2
+ madb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
+(define_insn "*fmsubdf"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
+ (match_operand:DF 2 "nonimmediate_operand" "f,R"))
+ (match_operand:DF 3 "register_operand" "0,0")))]
+ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
+ "@
+ msdbr\t%0,%1,%2
+ msdb\t%0,%1,%2"
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fmuld")])
+
+;
+; mulsf3 instruction pattern(s).
+;
+
+(define_expand "mulsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R")))]
+ "TARGET_HARD_FLOAT"
+ "")
+
+(define_insn "*mulsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SF 2 "general_operand" "f,R")))]