-(define_insn "*<code><mode>2_1"
- [(set (match_operand:X87MODEF 0 "register_operand" "=f")
- (absneg:X87MODEF (match_operand:X87MODEF 1 "register_operand" "0")))]
- "TARGET_80387
- && (reload_completed
- || !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))"
- "f<absnegprefix>"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "*<code>extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (absneg:DF (float_extend:DF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
- "f<absnegprefix>"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "DF")])
-
-(define_insn "*<code>extendsfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (absneg:XF (float_extend:XF
- (match_operand:SF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "f<absnegprefix>"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-
-(define_insn "*<code>extenddfxf2"
- [(set (match_operand:XF 0 "register_operand" "=f")
- (absneg:XF (float_extend:XF
- (match_operand:DF 1 "register_operand" "0"))))]
- "TARGET_80387"
- "f<absnegprefix>"
- [(set_attr "type" "fsgn")
- (set_attr "mode" "XF")])
-
-;; Copysign instructions
-
-(define_mode_iterator CSGNMODE [SF DF TF])
-(define_mode_attr CSGNVMODE [(SF "V4SF") (DF "V2DF") (TF "TF")])
-
-(define_expand "copysign<mode>3"
- [(match_operand:CSGNMODE 0 "register_operand" "")
- (match_operand:CSGNMODE 1 "nonmemory_operand" "")
- (match_operand:CSGNMODE 2 "register_operand" "")]
- "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
-{
- ix86_expand_copysign (operands);
- DONE;
-})
-
-(define_insn_and_split "copysign<mode>3_const"
- [(set (match_operand:CSGNMODE 0 "register_operand" "=x")
- (unspec:CSGNMODE
- [(match_operand:<CSGNVMODE> 1 "vector_move_operand" "xmC")
- (match_operand:CSGNMODE 2 "register_operand" "0")
- (match_operand:<CSGNVMODE> 3 "nonimmediate_operand" "xm")]
- UNSPEC_COPYSIGN))]
- "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
- "#"
- "&& reload_completed"
- [(const_int 0)]
-{
- ix86_split_copysign_const (operands);
- DONE;
-})
-
-(define_insn "copysign<mode>3_var"
- [(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x")
- (unspec:CSGNMODE
- [(match_operand:CSGNMODE 2 "register_operand" "x,0,0,x,x")
- (match_operand:CSGNMODE 3 "register_operand" "1,1,x,1,x")
- (match_operand:<CSGNVMODE> 4 "nonimmediate_operand" "X,xm,xm,0,0")
- (match_operand:<CSGNVMODE> 5 "nonimmediate_operand" "0,xm,1,xm,1")]
- UNSPEC_COPYSIGN))
- (clobber (match_scratch:<CSGNVMODE> 1 "=x,x,x,x,x"))]
- "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode))"
- "#")
-
-(define_split
- [(set (match_operand:CSGNMODE 0 "register_operand" "")
- (unspec:CSGNMODE
- [(match_operand:CSGNMODE 2 "register_operand" "")
- (match_operand:CSGNMODE 3 "register_operand" "")
- (match_operand:<CSGNVMODE> 4 "" "")
- (match_operand:<CSGNVMODE> 5 "" "")]
- UNSPEC_COPYSIGN))
- (clobber (match_scratch:<CSGNVMODE> 1 ""))]
- "((SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
- || (TARGET_SSE2 && (<MODE>mode == TFmode)))
- && reload_completed"
- [(const_int 0)]
-{
- ix86_split_copysign_var (operands);
- DONE;
-})
-\f
-;; One complement instructions
-
-(define_expand "one_cmpldi2"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
-
-(define_insn "*one_cmpldi2_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
- "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
- "not{q}\t%0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "DI")])
-
-(define_insn "*one_cmpldi2_2_rex64"
- [(set (reg FLAGS_REG)
- (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (not:DI (match_dup 1)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, DImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "DI")])
-
-(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
- (match_operator 2 "compare_operator"
- [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
- (const_int 0)]))
- (set (match_operand:DI 1 "nonimmediate_operand" "")
- (not:DI (match_dup 3)))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (match_dup 0)
- (match_op_dup 2
- [(xor:DI (match_dup 3) (const_int -1))
- (const_int 0)]))
- (set (match_dup 1)
- (xor:DI (match_dup 3) (const_int -1)))])]
- "")
-
-(define_expand "one_cmplsi2"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
- ""
- "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
-
-(define_insn "*one_cmplsi2_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
- "ix86_unary_operator_ok (NOT, SImode, operands)"
- "not{l}\t%0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "SI")])
-
-;; ??? Currently never generated - xor is used instead.
-(define_insn "*one_cmplsi2_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
- "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
- "not{l}\t%k0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "SI")])
-
-(define_insn "*one_cmplsi2_2"
- [(set (reg FLAGS_REG)
- (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
- (const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (not:SI (match_dup 1)))]
- "ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, SImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "SI")])
-
-(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
- (match_operator 2 "compare_operator"
- [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
- (const_int 0)]))
- (set (match_operand:SI 1 "nonimmediate_operand" "")
- (not:SI (match_dup 3)))]
- "ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (match_dup 0)
- (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
- (const_int 0)]))
- (set (match_dup 1)
- (xor:SI (match_dup 3) (const_int -1)))])]
- "")
-
-;; ??? Currently never generated - xor is used instead.
-(define_insn "*one_cmplsi2_2_zext"
- [(set (reg FLAGS_REG)
- (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (not:SI (match_dup 1))))]
- "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, SImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "SI")])
-
-(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
- (match_operator 2 "compare_operator"
- [(not:SI (match_operand:SI 3 "register_operand" ""))
- (const_int 0)]))
- (set (match_operand:DI 1 "register_operand" "")
- (zero_extend:DI (not:SI (match_dup 3))))]
- "ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (match_dup 0)
- (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
- (const_int 0)]))
- (set (match_dup 1)
- (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
- "")
-
-(define_expand "one_cmplhi2"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
- "TARGET_HIMODE_MATH"
- "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
-
-(define_insn "*one_cmplhi2_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
- "ix86_unary_operator_ok (NOT, HImode, operands)"
- "not{w}\t%0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "HI")])
-
-(define_insn "*one_cmplhi2_2"
- [(set (reg FLAGS_REG)
- (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (not:HI (match_dup 1)))]
- "ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NEG, HImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "HI")])
-
-(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
- (match_operator 2 "compare_operator"
- [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
- (const_int 0)]))
- (set (match_operand:HI 1 "nonimmediate_operand" "")
- (not:HI (match_dup 3)))]
- "ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (match_dup 0)
- (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
- (const_int 0)]))
- (set (match_dup 1)
- (xor:HI (match_dup 3) (const_int -1)))])]
- "")
-
-;; %%% Potential partial reg stall on alternative 1. What to do?
-(define_expand "one_cmplqi2"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
- "TARGET_QIMODE_MATH"
- "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
-
-(define_insn "*one_cmplqi2_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
- (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
- "ix86_unary_operator_ok (NOT, QImode, operands)"
- "@
- not{b}\t%0
- not{l}\t%k0"
- [(set_attr "type" "negnot")
- (set_attr "mode" "QI,SI")])
-
-(define_insn "*one_cmplqi2_2"
- [(set (reg FLAGS_REG)
- (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
- (const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
- (not:QI (match_dup 1)))]
- "ix86_match_ccmode (insn, CCNOmode)
- && ix86_unary_operator_ok (NOT, QImode, operands)"
- "#"
- [(set_attr "type" "alu1")
- (set_attr "mode" "QI")])
-
-(define_split
- [(set (match_operand 0 "flags_reg_operand" "")
- (match_operator 2 "compare_operator"
- [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
- (const_int 0)]))
- (set (match_operand:QI 1 "nonimmediate_operand" "")
- (not:QI (match_dup 3)))]
- "ix86_match_ccmode (insn, CCNOmode)"
- [(parallel [(set (match_dup 0)
- (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
- (const_int 0)]))
- (set (match_dup 1)
- (xor:QI (match_dup 3) (const_int -1)))])]
- "")
-\f
-;; Arithmetic shift instructions
-
-;; DImode shifts are implemented using the i386 "shift double" opcode,
-;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
-;; is variable, then the count is in %cl and the "imm" operand is dropped
-;; from the assembler input.
-;;
-;; This instruction shifts the target reg/mem as usual, but instead of
-;; shifting in zeros, bits are shifted in from reg operand. If the insn
-;; is a left shift double, bits are taken from the high order bits of
-;; reg, else if the insn is a shift right double, bits are taken from the
-;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
-;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
-;;
-;; Since sh[lr]d does not change the `reg' operand, that is done
-;; separately, making all shifts emit pairs of shift double and normal
-;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
-;; support a 63 bit shift, each shift where the count is in a reg expands
-;; to a pair of shifts, a branch, a shift by 32 and a label.
-;;
-;; If the shift count is a constant, we need never emit more than one
-;; shift pair, instead using moves and sign extension for counts greater
-;; than 31.
-
-(define_expand "ashlti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "reg_or_pm1_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (ASHIFT, TImode, operands); DONE;")
-
-;; This pattern must be defined before *ashlti3_1 to prevent
-;; combine pass from converting sse2_ashlti3 to *ashlti3_1.
-
-(define_insn "*avx_ashlti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (ashift:TI (match_operand:TI 1 "register_operand" "x")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_AVX"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix" "vex")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "sse2_ashlti3"
- [(set (match_operand:TI 0 "register_operand" "=x")
- (ashift:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
- "TARGET_SSE2"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
- return "pslldq\t{%2, %0|%0, %2}";
-}
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "1")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "*ashlti3_1"
- [(set (match_operand:TI 0 "register_operand" "=&r,r")
- (ashift:TI (match_operand:TI 1 "reg_or_pm1_operand" "n,0")
- (match_operand:QI 2 "nonmemory_operand" "Oc,Oc")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
-
-(define_peephole2
- [(match_scratch:DI 3 "r")
- (parallel [(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "TARGET_64BIT"
- [(const_int 0)]
- "ix86_split_ashl (operands, operands[3], TImode); DONE;")
-
-(define_split
- [(set (match_operand:TI 0 "register_operand" "")
- (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
- ? epilogue_completed : reload_completed)"
- [(const_int 0)]
- "ix86_split_ashl (operands, NULL_RTX, TImode); DONE;")
-
-(define_insn "x86_64_shld"
- [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
- (ior:DI (ashift:DI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "Jc"))
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
- (minus:QI (const_int 64) (match_dup 2)))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "shld{q}\t{%s2%1, %0|%0, %1, %2}"
- [(set_attr "type" "ishift")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")
- (set_attr "athlon_decode" "vector")
- (set_attr "amdfam10_decode" "vector")])
-
-(define_expand "x86_64_shift_adj_1"
- [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
- (const_int 64))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "")
- (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:DI 1 "register_operand" "")
- (match_dup 0)))
- (set (match_dup 1)
- (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:DI 3 "register_operand" "r")
- (match_dup 1)))]
- "TARGET_64BIT"
- "")
-
-(define_expand "x86_64_shift_adj_2"
- [(use (match_operand:DI 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
- "TARGET_64BIT"
-{
- rtx label = gen_label_rtx ();
- rtx tmp;
-
- emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64)));
-
- tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
- tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
- tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
- gen_rtx_LABEL_REF (VOIDmode, label),
- pc_rtx);
- tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
- JUMP_LABEL (tmp) = label;
-
- emit_move_insn (operands[0], operands[1]);
- ix86_expand_clear (operands[1]);
-
- emit_label (label);
- LABEL_NUSES (label) = 1;
-
- DONE;
-})
-
-(define_expand "ashldi3"
- [(set (match_operand:DI 0 "shiftdi_operand" "")
- (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
-
-(define_insn "*ashldi3_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
- (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
- (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- return "add{q}\t%0, %0";
-
- case TYPE_LEA:
- gcc_assert (CONST_INT_P (operands[2]));
- gcc_assert ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) <= 3);
- operands[1] = gen_rtx_MULT (DImode, operands[1],
- GEN_INT (1 << INTVAL (operands[2])));
- return "lea{q}\t{%a1, %0|%0, %a1}";
-
- default:
- if (REG_P (operands[2]))
- return "sal{q}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{q}\t%0";
- else
- return "sal{q}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "DI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "index_register_operand" "")
- (match_operand:QI 2 "immediate_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(set (match_dup 0)
- (mult:DI (match_dup 1)
- (match_dup 2)))]
- "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashldi3_cmp_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_63_operand" "J"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (ashift:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{q}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{q}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{q}\t%0";
- else
- return "sal{q}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "DI")])
-
-(define_insn "*ashldi3_cconly_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_63_operand" "J"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{q}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{q}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{q}\t%0";
- else
- return "sal{q}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "DI")])
-
-(define_insn "*ashldi3_1"
- [(set (match_operand:DI 0 "register_operand" "=&r,r")
- (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
- (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
-
-;; By default we don't ask for a scratch register, because when DImode
-;; values are manipulated, registers are already at a premium. But if
-;; we have one handy, we won't turn it away.
-(define_peephole2
- [(match_scratch:SI 3 "r")
- (parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "!TARGET_64BIT && TARGET_CMOVE"
- [(const_int 0)]
- "ix86_split_ashl (operands, operands[3], DImode); DONE;")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
- ? epilogue_completed : reload_completed)"
- [(const_int 0)]
- "ix86_split_ashl (operands, NULL_RTX, DImode); DONE;")
-
-(define_insn "x86_shld"
- [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
- (ior:SI (ashift:SI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "Ic"))
- (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
- (minus:QI (const_int 32) (match_dup 2)))))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "shld{l}\t{%s2%1, %0|%0, %1, %2}"
- [(set_attr "type" "ishift")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "SI")
- (set_attr "pent_pair" "np")
- (set_attr "athlon_decode" "vector")
- (set_attr "amdfam10_decode" "vector")])
-
-(define_expand "x86_shift_adj_1"
- [(set (reg:CCZ FLAGS_REG)
- (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
- (const_int 32))
- (const_int 0)))
- (set (match_operand:SI 0 "register_operand" "")
- (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SI 1 "register_operand" "")
- (match_dup 0)))
- (set (match_dup 1)
- (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
- (match_operand:SI 3 "register_operand" "r")
- (match_dup 1)))]
- "TARGET_CMOVE"
- "")
-
-(define_expand "x86_shift_adj_2"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:SI 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
- ""
-{
- rtx label = gen_label_rtx ();
- rtx tmp;
-
- emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
-
- tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
- tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
- tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
- gen_rtx_LABEL_REF (VOIDmode, label),
- pc_rtx);
- tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
- JUMP_LABEL (tmp) = label;
-
- emit_move_insn (operands[0], operands[1]);
- ix86_expand_clear (operands[1]);
-
- emit_label (label);
- LABEL_NUSES (label) = 1;
-
- DONE;
-})
-
-(define_expand "ashlsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
-
-(define_insn "*ashlsi3_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
- (match_operand:QI 2 "nonmemory_operand" "cI,M")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- return "add{l}\t%0, %0";
-
- case TYPE_LEA:
- return "#";
-
- default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{l}\t%0";
- else
- return "sal{l}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "index_register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])
- && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
- [(const_int 0)]
-{
- rtx pat;
- enum machine_mode mode = GET_MODE (operands[0]);
-
- if (GET_MODE_SIZE (mode) < 4)
- operands[0] = gen_lowpart (SImode, operands[0]);
- if (mode != Pmode)
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
-
- pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
- if (Pmode != SImode)
- pat = gen_rtx_SUBREG (SImode, pat, 0);
- emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
- DONE;
-})
-
-;; Rare case of shifting RSP is handled by generating move and shift
-(define_split
- [(set (match_operand 0 "register_operand" "")
- (ashift (match_operand 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(const_int 0)]
-{
- rtx pat, clob;
- emit_move_insn (operands[0], operands[1]);
- pat = gen_rtx_SET (VOIDmode, operands[0],
- gen_rtx_ASHIFT (GET_MODE (operands[0]),
- operands[0], operands[2]));
- clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
- emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
- DONE;
-})
-
-(define_insn "*ashlsi3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
- (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t%k0, %k0";
-
- case TYPE_LEA:
- return "#";
-
- default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{l}\t%k0";
- else
- return "sal{l}\t{%2, %k0|%k0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-;; Convert lea to the lea pattern to avoid flags dependency.
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
- (match_operand:QI 2 "const_int_operand" ""))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && reload_completed
- && true_regnum (operands[0]) != true_regnum (operands[1])"
- [(set (match_dup 0) (zero_extend:DI
- (subreg:SI (mult:SI (match_dup 1)
- (match_dup 2)) 0)))]
-{
- operands[1] = gen_lowpart (Pmode, operands[1]);
- operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
-})
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashlsi3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (ashift:SI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{l}\t%0";
- else
- return "sal{l}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashlsi3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{l}\t%0";
- else
- return "sal{l}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_insn "*ashlsi3_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{l}\t%k0, %k0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{l}\t%k0";
- else
- return "sal{l}\t{%2, %k0|%k0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "SI")])
-
-(define_expand "ashlhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
-
-(define_insn "*ashlhi3_1_lea"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
- (match_operand:QI 2 "nonmemory_operand" "cI,M")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_LEA:
- return "#";
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{w}\t%0";
- else
- return "sal{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(eq_attr "alternative" "1")
- (const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "HI,SI")])
-
-(define_insn "*ashlhi3_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "cI")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{w}\t%0";
- else
- return "sal{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashlhi3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (ashift:HI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{w}\t%0";
- else
- return "sal{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_insn "*ashlhi3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{w}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{w}\t%0";
- else
- return "sal{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_expand "ashlqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
-
-;; %%% Potential partial reg stall on alternative 2. What to do?
-
-(define_insn "*ashlqi3_1_lea"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
- (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_LEA:
- return "#";
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return "add{l}\t%k0, %k0";
- else
- return "add{b}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t%0";
- else
- return "sal{b}\t%0";
- }
- else
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%2, %k0|%k0, %2}";
- else
- return "sal{b}\t{%2, %0|%0, %2}";
- }
- }
-}
- [(set (attr "type")
- (cond [(eq_attr "alternative" "2")
- (const_string "lea")
- (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI,SI,SI")])
-
-(define_insn "*ashlqi3_1"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_PARTIAL_REG_STALL
- && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
- return "add{l}\t%k0, %k0";
- else
- return "add{b}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t%0";
- else
- return "sal{b}\t%0";
- }
- else
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%2, %k0|%k0, %2}";
- else
- return "sal{b}\t{%2, %0|%0, %2}";
- }
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI,SI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashlqi3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
- (ashift:QI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || (TARGET_DOUBLE_WITH_ADD && REG_P (operands[0])))))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{b}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{b}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{b}\t%0";
- else
- return "sal{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI")])
-
-(define_insn "*ashlqi3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (clobber (match_scratch:QI 0 "=q"))]
- "(optimize_function_for_size_p (cfun)
- || !TARGET_PARTIAL_FLAG_REG_STALL
- || (operands[2] == const1_rtx
- && (TARGET_SHIFT1
- || TARGET_DOUBLE_WITH_ADD)))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_ALU:
- gcc_assert (operands[2] == const1_rtx);
- return "add{b}\t%0, %0";
-
- default:
- if (REG_P (operands[2]))
- return "sal{b}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
- return "sal{b}\t%0";
- else
- return "sal{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
- (const_int 0))
- (match_operand 0 "register_operand" ""))
- (match_operand 2 "const1_operand" ""))
- (const_string "alu")
- ]
- (const_string "ishift")))
- (set (attr "length_immediate")
- (if_then_else
- (ior (eq_attr "type" "alu")
- (and (eq_attr "type" "ishift")
- (and (match_operand 2 "const1_operand" "")
- (ne (symbol_ref "TARGET_SHIFT1 || optimize_function_for_size_p (cfun)")
- (const_int 0)))))
- (const_string "0")
- (const_string "*")))
- (set_attr "mode" "QI")])
-
-;; See comment above `ashldi3' about how this works.
-
-(define_expand "ashrti3"
- [(set (match_operand:TI 0 "register_operand" "")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_64BIT"
- "ix86_expand_binary_operator (ASHIFTRT, TImode, operands); DONE;")
-
-(define_insn "*ashrti3_1"
- [(set (match_operand:TI 0 "register_operand" "=r")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Oc")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
-
-(define_peephole2
- [(match_scratch:DI 3 "r")
- (parallel [(set (match_operand:TI 0 "register_operand" "")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "TARGET_64BIT"
- [(const_int 0)]
- "ix86_split_ashr (operands, operands[3], TImode); DONE;")
-
-(define_split
- [(set (match_operand:TI 0 "register_operand" "")
- (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
- ? epilogue_completed : reload_completed)"
- [(const_int 0)]
- "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
-
-(define_insn "x86_64_shrd"
- [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
- (ior:DI (ashiftrt:DI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "Jc"))
- (ashift:DI (match_operand:DI 1 "register_operand" "r")
- (minus:QI (const_int 64) (match_dup 2)))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT"
- "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
- [(set_attr "type" "ishift")
- (set_attr "prefix_0f" "1")
- (set_attr "mode" "DI")
- (set_attr "athlon_decode" "vector")
- (set_attr "amdfam10_decode" "vector")])
-
-(define_expand "ashrdi3"
- [(set (match_operand:DI 0 "shiftdi_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
-
-(define_expand "x86_64_shift_adj_3"
- [(use (match_operand:DI 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
- ""
-{
- rtx label = gen_label_rtx ();
- rtx tmp;
-
- emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (64)));
-
- tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
- tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
- tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
- gen_rtx_LABEL_REF (VOIDmode, label),
- pc_rtx);
- tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
- JUMP_LABEL (tmp) = label;
-
- emit_move_insn (operands[0], operands[1]);
- emit_insn (gen_ashrdi3_63_rex64 (operands[1], operands[1], GEN_INT (63)));
-
- emit_label (label);
- LABEL_NUSES (label) = 1;
-
- DONE;
-})
-
-(define_insn "ashrdi3_63_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
- (match_operand:DI 2 "const_int_operand" "i,i")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && INTVAL (operands[2]) == 63
- && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "@
- {cqto|cqo}
- sar{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imovx,ishift")
- (set_attr "prefix_0f" "0,*")
- (set_attr "length_immediate" "0,*")
- (set_attr "modrm" "0,1")
- (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_1_one_bit_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "J,c")))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "@
- sar{q}\t{%2, %0|%0, %2}
- sar{q}\t{%b2, %0|%0, %b2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "DI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrdi3_one_bit_cmp_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_one_bit_cconly_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "DI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrdi3_cmp_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_63_operand" "J"))
- (const_int 0)))
- (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_cconly_rex64"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_63_operand" "J"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=r"))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
- "sar{q}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "DI")])
-
-(define_insn "*ashrdi3_1"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "Jc")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT"
- "#"
- [(set_attr "type" "multi")])
-
-;; By default we don't ask for a scratch register, because when DImode
-;; values are manipulated, registers are already at a premium. But if
-;; we have one handy, we won't turn it away.
-(define_peephole2
- [(match_scratch:SI 3 "r")
- (parallel [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))])
- (match_dup 3)]
- "!TARGET_64BIT && TARGET_CMOVE"
- [(const_int 0)]
- "ix86_split_ashr (operands, operands[3], DImode); DONE;")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
- ? epilogue_completed : reload_completed)"
- [(const_int 0)]
- "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
-
-(define_insn "x86_shrd"
- [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
- (ior:SI (ashiftrt:SI (match_dup 0)
- (match_operand:QI 2 "nonmemory_operand" "Ic"))
- (ashift:SI (match_operand:SI 1 "register_operand" "r")
- (minus:QI (const_int 32) (match_dup 2)))))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
- [(set_attr "type" "ishift")
- (set_attr "prefix_0f" "1")
- (set_attr "pent_pair" "np")
- (set_attr "mode" "SI")])
-
-(define_expand "x86_shift_adj_3"
- [(use (match_operand:SI 0 "register_operand" ""))
- (use (match_operand:SI 1 "register_operand" ""))
- (use (match_operand:QI 2 "register_operand" ""))]
- ""
-{
- rtx label = gen_label_rtx ();
- rtx tmp;
-
- emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
-
- tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
- tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
- tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
- gen_rtx_LABEL_REF (VOIDmode, label),
- pc_rtx);
- tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
- JUMP_LABEL (tmp) = label;
-
- emit_move_insn (operands[0], operands[1]);
- emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
-
- emit_label (label);
- LABEL_NUSES (label) = 1;
-
- DONE;
-})
-
-(define_expand "ashrsi3_31"
- [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
- (match_operand:SI 2 "const_int_operand" "i,i")))
- (clobber (reg:CC FLAGS_REG))])]
- "")
-
-(define_insn "*ashrsi3_31"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
- (match_operand:SI 2 "const_int_operand" "i,i")))
- (clobber (reg:CC FLAGS_REG))]
- "INTVAL (operands[2]) == 31
- && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "@
- {cltd|cdq}
- sar{l}\t{%2, %0|%0, %2}"
- [(set_attr "type" "imovx,ishift")
- (set_attr "prefix_0f" "0,*")
- (set_attr "length_immediate" "0,*")
- (set_attr "modrm" "0,1")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_31_zext"
- [(set (match_operand:DI 0 "register_operand" "=*d,r")
- (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
- (match_operand:SI 2 "const_int_operand" "i,i"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
- && INTVAL (operands[2]) == 31
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "@
- {cltd|cdq}
- sar{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "imovx,ishift")
- (set_attr "prefix_0f" "0,*")
- (set_attr "length_immediate" "0,*")
- (set_attr "modrm" "0,1")
- (set_attr "mode" "SI")])
-
-(define_expand "ashrsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- ""
- "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
-
-(define_insn "*ashrsi3_1_one_bit"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1_one_bit_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t%k0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "@
- sar{l}\t{%2, %0|%0, %2}
- sar{l}\t{%b2, %0|%0, %b2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,c"))))
- (clobber (reg:CC FLAGS_REG))]
- "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "@
- sar{l}\t{%2, %k0|%k0, %2}
- sar{l}\t{%b2, %k0|%k0, %b2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "SI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrsi3_one_bit_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_one_bit_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_one_bit_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t%k0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "SI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrsi3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:SI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "SI")])
-
-(define_insn "*ashrsi3_cmp_zext"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=r")
- (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
- "TARGET_64BIT
- && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
- "sar{l}\t{%2, %k0|%k0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "SI")])
-
-(define_expand "ashrhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_HIMODE_MATH"
- "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
-
-(define_insn "*ashrhi3_1_one_bit"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" "")))
- (clobber (reg:CC FLAGS_REG))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_1"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
- (match_operand:QI 2 "nonmemory_operand" "I,c")))
- (clobber (reg:CC FLAGS_REG))]
- "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "@
- sar{w}\t{%2, %0|%0, %2}
- sar{w}\t{%b2, %0|%0, %b2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "HI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrhi3_one_bit_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:HI (match_dup 1) (match_dup 2)))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_one_bit_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const1_operand" ""))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\t%0"
- [(set_attr "type" "ishift")
- (set_attr "length_immediate" "0")
- (set_attr "mode" "HI")])
-
-;; This pattern can't accept a variable shift count, since shifts by
-;; zero don't affect the flags. We assume that shifts by constant
-;; zero are optimized away.
-(define_insn "*ashrhi3_cmp"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
- (ashiftrt:HI (match_dup 1) (match_dup 2)))]
- "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "HI")])
-
-(define_insn "*ashrhi3_cconly"
- [(set (reg FLAGS_REG)
- (compare
- (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_1_to_31_operand" "I"))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
- && ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
- "sar{w}\t{%2, %0|%0, %2}"
- [(set_attr "type" "ishift")
- (set_attr "mode" "HI")])
-
-(define_expand "ashrqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))]
- "TARGET_QIMODE_MATH"
- "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")