+\f
+;; -----------------------------------------------------------------
+;; COMBINE PATTERNS
+;; -----------------------------------------------------------------
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "or.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "or\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (xor:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:HI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[1])
+ && (REGNO (operands[0]) != REGNO (operands[1]))"
+ "xor.w\\t%T1,%f0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (xor:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "0")))]
+ "REG_P (operands[0])
+ && REG_P (operands[1])
+ && REGNO (operands[0]) != REGNO (operands[1])"
+ "xor\\t%X1,%s0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (ior:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "0"))
+ (ashift:HI (match_operand:HI 2 "register_operand" "r")
+ (const_int 8))))]
+ "REG_P (operands[0])
+ && REG_P (operands[2])
+ && REGNO (operands[0]) != REGNO (operands[2])"
+ "mov.b\\t%s2,%t0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))
+ (ashift:SI (match_operand:SI 2 "register_operand" "r")
+ (const_int 16))))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && REG_P (operands[0])
+ && REG_P (operands[2])
+ && (REGNO (operands[0]) != REGNO (operands[2]))"
+ "mov.w\\t%f2,%e0"
+ [(set_attr "cc" "clobber")
+ (set_attr "length" "2")])
+
+(define_insn_and_split ""
+ [(set (pc)
+ (if_then_else (eq (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ "#"
+ ""
+ [(set (cc0)
+ (match_dup 0))
+ (set (pc)
+ (if_then_else (ge (cc0)
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")
+
+(define_insn_and_split ""
+ [(set (pc)
+ (if_then_else (ne (zero_extract:SI (subreg:SI (match_operand:QI 0 "register_operand" "") 0)
+ (const_int 1)
+ (const_int 7))
+ (const_int 0))
+ (label_ref (match_operand 1 "" ""))
+ (pc)))]
+ ""
+ "#"
+ ""
+ [(set (cc0)
+ (match_dup 0))
+ (set (pc)
+ (if_then_else (lt (cc0)
+ (const_int 0))
+ (label_ref (match_dup 1))
+ (pc)))]
+ "")